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-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini61
-rwxr-xr-xtests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt1258
3 files changed, 670 insertions, 657 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 358d71402..431cc37fd 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -129,18 +129,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=262144
subblock_size=0
system=system
@@ -423,18 +423,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=131072
subblock_size=0
system=system
@@ -455,24 +455,24 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -482,10 +482,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +519,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -541,15 +541,28 @@ master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[0]
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index b2c42f9a9..d895f3126 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:51:51
-gem5 started Aug 13 2012 17:17:24
-gem5 executing on zizzer
+gem5 compiled Nov 1 2012 14:46:44
+gem5 started Nov 1 2012 15:18:34
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 14993500 because target called exit()
+Exiting @ tick 19857000 because target called exit()
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 6142b96e8..b523abef7 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,57 +1,57 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 20334000 # Number of ticks simulated
-final_tick 20334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 19857000 # Number of ticks simulated
+final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 80964 # Simulator instruction rate (inst/s)
-host_op_rate 80958 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 129154883 # Simulator tick rate (ticks/s)
-host_mem_usage 217900 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 50642 # Simulator instruction rate (inst/s)
+host_op_rate 50640 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 78893380 # Simulator tick rate (ticks/s)
+host_mem_usage 214784 # Number of bytes of host memory used
+host_seconds 0.25 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22784 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62656 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 356 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 979 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1960853743 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1120487853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3081341595 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1960853743 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1960853743 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1960853743 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1120487853 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3081341595 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 979 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62208 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 972 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2004733847 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1128065670 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3132799517 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2004733847 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2004733847 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2004733847 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1128065670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3132799517 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 972 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 979 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 62656 # Total number of bytes read from memory
+system.physmem.cpureqs 972 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 62208 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62656 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 62208 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 52 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 71 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 123 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 81 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 51 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 70 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 122 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 76 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 74 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 99 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 76 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 75 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 100 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 26 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 76 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 20181000 # Total gap between requests
+system.physmem.totGap 19816500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 979 # Categorize read packet sizes
+system.physmem.readPktSize::6 972 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 340 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 122 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 49 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 318 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 215 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 98 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 50 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 11431477 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 34163477 # Sum of mem lat for all requests
-system.physmem.totBusLat 3916000 # Total cycles spent in databus access
-system.physmem.totBankLat 18816000 # Total cycles spent in bank access
-system.physmem.avgQLat 11676.69 # Average queueing delay per request
-system.physmem.avgBankLat 19219.61 # Average bank access latency per request
+system.physmem.totQLat 11651972 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 34145972 # Sum of mem lat for all requests
+system.physmem.totBusLat 3888000 # Total cycles spent in databus access
+system.physmem.totBankLat 18606000 # Total cycles spent in bank access
+system.physmem.avgQLat 11987.63 # Average queueing delay per request
+system.physmem.avgBankLat 19141.98 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 34896.30 # Average memory access latency
-system.physmem.avgRdBW 3081.34 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 35129.60 # Average memory access latency
+system.physmem.avgRdBW 3132.80 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 3081.34 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3132.80 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 19.26 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.68 # Average read queue length over time
+system.physmem.busUtil 19.58 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.72 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 740 # Number of row buffer hits during reads
+system.physmem.readRowHits 733 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.59 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 20613.89 # Average gap between requests
+system.physmem.avgGap 20387.35 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4607 # DTB read hits
-system.cpu.dtb.read_misses 109 # DTB read misses
+system.cpu.dtb.read_hits 4359 # DTB read hits
+system.cpu.dtb.read_misses 96 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4716 # DTB read accesses
-system.cpu.dtb.write_hits 2105 # DTB write hits
-system.cpu.dtb.write_misses 77 # DTB write misses
+system.cpu.dtb.read_accesses 4455 # DTB read accesses
+system.cpu.dtb.write_hits 2014 # DTB write hits
+system.cpu.dtb.write_misses 72 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2182 # DTB write accesses
-system.cpu.dtb.data_hits 6712 # DTB hits
-system.cpu.dtb.data_misses 186 # DTB misses
+system.cpu.dtb.write_accesses 2086 # DTB write accesses
+system.cpu.dtb.data_hits 6373 # DTB hits
+system.cpu.dtb.data_misses 168 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6898 # DTB accesses
-system.cpu.itb.fetch_hits 5687 # ITB hits
-system.cpu.itb.fetch_misses 59 # ITB misses
+system.cpu.dtb.data_accesses 6541 # DTB accesses
+system.cpu.itb.fetch_hits 5250 # ITB hits
+system.cpu.itb.fetch_misses 57 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5746 # ITB accesses
+system.cpu.itb.fetch_accesses 5307 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -219,358 +219,358 @@ system.cpu.itb.data_acv 0 # DT
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 40669 # number of cpu cycles simulated
+system.cpu.numCycles 39715 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6981 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3954 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1690 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 5146 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 870 # Number of BTB hits
+system.cpu.BPredUnit.lookups 6348 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3569 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1446 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 4530 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 874 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 937 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 1717 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 38666 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6981 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1807 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 6508 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2004 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 376 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5687 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 915 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 27168 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.423218 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.808405 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 898 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 184 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1772 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 5994 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1779 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5250 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 858 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 26295 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.345161 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.748208 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 20660 76.05% 76.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 537 1.98% 78.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 399 1.47% 79.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 504 1.86% 81.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 464 1.71% 83.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 436 1.60% 84.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 485 1.79% 86.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 591 2.18% 88.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 3092 11.38% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 20301 77.20% 77.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 545 2.07% 79.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 388 1.48% 80.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 414 1.57% 82.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 431 1.64% 83.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 401 1.53% 85.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 440 1.67% 87.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 561 2.13% 89.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2814 10.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 27168 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.171654 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.950749 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38149 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 6961 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5575 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 517 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2929 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 646 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 395 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 33907 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 727 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2929 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 38897 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 984 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 5237 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2250 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 31157 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
-system.cpu.rename.LSQFullEvents 2290 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 23416 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 38564 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 38530 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 26295 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.159839 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.890621 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 37128 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 7028 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5161 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 465 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2623 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 533 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 326 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 31237 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 663 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2623 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37789 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3807 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1133 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 4855 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2198 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 28851 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full
+system.cpu.rename.LSQFullEvents 2210 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 21669 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 35547 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 35513 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 14276 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 53 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 6217 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3020 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1445 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 12529 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 51 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 6010 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2907 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2972 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1380 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads.
+system.cpu.memDep1.insertedLoads 2775 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1297 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 27184 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 71 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 22298 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 13301 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 8222 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 27168 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.820745 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.402255 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 25429 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21088 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11668 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 7282 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 26295 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.801978 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.371425 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17752 65.34% 65.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3320 12.22% 77.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2545 9.37% 86.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1596 5.87% 92.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1085 3.99% 96.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 559 2.06% 98.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 231 0.85% 99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 61 0.22% 99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 19 0.07% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17201 65.42% 65.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3228 12.28% 77.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2604 9.90% 87.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1566 5.96% 93.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 907 3.45% 97.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 493 1.87% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 226 0.86% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 55 0.21% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 15 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 27168 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 26295 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 13 6.70% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 118 60.82% 67.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 63 32.47% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 117 60.31% 65.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 66 34.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7510 66.63% 66.65% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2596 23.03% 89.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1160 10.29% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 6973 65.93% 65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2492 23.56% 89.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1106 10.46% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 11271 # Type of FU issued
+system.cpu.iq.FU_type_0::total 10576 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7311 66.30% 66.32% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.33% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.33% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.35% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2558 23.20% 89.54% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1153 10.46% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 7011 66.70% 66.71% # Type of FU issued
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+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.74% # Type of FU issued
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+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.74% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.74% # Type of FU issued
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+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.74% # Type of FU issued
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+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.74% # Type of FU issued
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+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.74% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.74% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.74% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.74% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.74% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.74% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.74% # Type of FU issued
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+system.cpu.iq.FU_type_1::MemRead 2403 22.86% 89.60% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1093 10.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 11027 # Type of FU issued
+system.cpu.iq.FU_type_1::total 10512 # Type of FU issued
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu 14821 66.47% 66.49% # Type of FU issued
-system.cpu.iq.FU_type::IntMult 2 0.01% 66.49% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv 0 0.00% 66.49% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.51% # Type of FU issued
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-system.cpu.iq.FU_type::SimdMult 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdShift 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type::MemRead 5154 23.11% 89.63% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite 2313 10.37% 100.00% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu 13984 66.31% 66.33% # Type of FU issued
+system.cpu.iq.FU_type::IntMult 2 0.01% 66.34% # Type of FU issued
+system.cpu.iq.FU_type::IntDiv 0 0.00% 66.34% # Type of FU issued
+system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::FloatMult 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdMult 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdShift 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type::MemRead 4895 23.21% 89.57% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite 2199 10.43% 100.00% # Type of FU issued
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::total 22298 # Type of FU issued
-system.cpu.iq.rate 0.548280 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 100 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 94 # FU busy when requested
+system.cpu.iq.FU_type::total 21088 # Type of FU issued
+system.cpu.iq.rate 0.530983 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested
system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.004485 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.004216 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.008700 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 72061 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 40564 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19339 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate::0 0.004458 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.004742 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.009200 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 68733 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 37173 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 18381 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 22466 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21256 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1837 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 580 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1724 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 295 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 77 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 355 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1789 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 515 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1592 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 432 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 238 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2929 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 685 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 27441 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 749 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5992 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2825 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 71 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 275 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1233 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1508 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20701 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2373 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2359 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4732 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1597 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2623 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 887 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 25678 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 656 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 5682 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2660 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 31 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 235 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1060 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1295 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 19629 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2279 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 2190 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4469 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1459 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 114 # number of nop insts executed
-system.cpu.iew.exec_nop::1 72 # number of nop insts executed
-system.cpu.iew.exec_nop::total 186 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3487 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3445 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6932 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1642 # Number of branches executed
-system.cpu.iew.exec_branches::1 1642 # Number of branches executed
-system.cpu.iew.exec_branches::total 3284 # Number of branches executed
-system.cpu.iew.exec_stores::0 1114 # Number of stores executed
-system.cpu.iew.exec_stores::1 1086 # Number of stores executed
-system.cpu.iew.exec_stores::total 2200 # Number of stores executed
-system.cpu.iew.exec_rate 0.509012 # Inst execution rate
-system.cpu.iew.wb_sent::0 9936 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9721 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 19657 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9778 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19359 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5047 # num instructions producing a value
-system.cpu.iew.wb_producers::1 4925 # num instructions producing a value
-system.cpu.iew.wb_producers::total 9972 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6570 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6411 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 12981 # num instructions consuming a value
+system.cpu.iew.exec_nop::0 110 # number of nop insts executed
+system.cpu.iew.exec_nop::1 69 # number of nop insts executed
+system.cpu.iew.exec_nop::total 179 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3341 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3226 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6567 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1545 # Number of branches executed
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+system.cpu.iew.exec_branches::total 3108 # Number of branches executed
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+system.cpu.iew.exec_rate 0.494247 # Inst execution rate
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+system.cpu.iew.wb_consumers::total 12340 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
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-system.cpu.iew.wb_rate::1 0.235585 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.476014 # insts written-back per cycle
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system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1316 # The number of times a branch was mispredicted
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+system.cpu.commit.branchMispredicts 1134 # The number of times a branch was mispredicted
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 21479 79.33% 79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2818 10.41% 89.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1191 4.40% 94.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 503 1.86% 95.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 353 1.30% 97.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 251 0.93% 98.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 184 0.68% 98.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 85 0.31% 99.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 213 0.79% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 20568 78.45% 78.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2989 11.40% 89.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1062 4.05% 93.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 514 1.96% 95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 342 1.30% 97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 238 0.91% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 201 0.77% 98.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 72 0.27% 99.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 232 0.88% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 27077 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 26218 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
@@ -601,83 +601,83 @@ system.cpu.commit.int_insts::total 12614 # Nu
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 129384 # The number of ROB reads
-system.cpu.rob.rob_writes 57896 # The number of ROB writes
-system.cpu.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13501 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 123093 # The number of ROB reads
+system.cpu.rob.rob_writes 54044 # The number of ROB writes
+system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13420 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
-system.cpu.cpi::0 6.382454 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 6.381453 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.190977 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.156680 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.156704 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.313384 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 26029 # number of integer regfile reads
-system.cpu.int_regfile_writes 14619 # number of integer regfile writes
+system.cpu.cpi::0 6.232737 # CPI: Cycles Per Instruction
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+system.cpu.cpi_total 3.116124 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.160443 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.160468 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.320911 # IPC: Total IPC of All Threads
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system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
-system.cpu.icache.replacements::0 6 # number of replacements
+system.cpu.icache.replacements::0 7 # number of replacements
system.cpu.icache.replacements::1 0 # number of replacements
-system.cpu.icache.replacements::total 6 # number of replacements
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-system.cpu.icache.total_refs 4652 # Total number of references to valid blocks.
+system.cpu.icache.replacements::total 7 # number of replacements
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system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks.
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+system.cpu.icache.avg_refs 6.742400 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::cpu.inst 0.151064 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.151064 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 4652 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 4652 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 4652 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 4652 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 4652 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses
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-system.cpu.icache.ReadReq_miss_latency::total 56036996 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 56036996 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 56036996 # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::total 5682 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 5682 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 5682 # number of overall (read+write) accesses
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-system.cpu.icache.overall_miss_rate::total 0.181274 # miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 54404.850485 # average ReadReq miss latency
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-system.cpu.icache.blocked_cycles::no_mshrs 2136 # number of cycles access was blocked
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.987379 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55066.987379 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55066.987379 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55066.987379 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 2360 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 38.142857 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
@@ -693,207 +693,207 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 625
system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 37870497 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37870497 # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37870497 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 37870497 # number of overall MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.109996 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.109996 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60592.795200 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60592.795200 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60592.795200 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements::0 0 # number of replacements
system.cpu.dcache.replacements::1 0 # number of replacements
system.cpu.dcache.replacements::total 0 # number of replacements
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -902,50 +902,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------