diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt | 436 |
1 files changed, 218 insertions, 218 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt index b23a2b88f..cdfe6dd6a 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000167 # Number of seconds simulated -sim_ticks 167328500 # Number of ticks simulated -final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 167318000 # Number of ticks simulated +final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54302 # Simulator instruction rate (inst/s) -host_op_rate 54316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79708249 # Simulator tick rate (ticks/s) -host_mem_usage 244184 # Number of bytes of host memory used -host_seconds 2.10 # Real time elapsed on the host +host_inst_rate 259842 # Simulator instruction rate (inst/s) +host_op_rate 259907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 381385356 # Simulator tick rate (ticks/s) +host_mem_usage 261864 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host sim_insts 113991 # Number of instructions simulated sim_ops 114022 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory system.physmem.bytes_read::total 69760 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 52672 # Nu system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1090 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 166995000 # Total gap between requests +system.physmem.totGap 166987000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -201,15 +201,15 @@ system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # By system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation -system.physmem.totQLat 15434500 # Total ticks spent queuing -system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 15449500 # Total ticks spent queuing +system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.26 # Data bus utilization in percentage @@ -221,59 +221,59 @@ system.physmem.readRowHits 874 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 153206.42 # Average gap between requests +system.physmem.avgGap 153199.08 # Average gap between requests system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ) -system.physmem_0.averagePower 555.501490 # Core power per rank (mW) -system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.517657 # Core power per rank (mW) +system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ) -system.physmem_1.averagePower 539.085991 # Core power per rank (mW) -system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ) +system.physmem_1.averagePower 539.101715 # Core power per rank (mW) +system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 31621 # Number of BP lookups -system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15507 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31578 # Number of BP lookups +system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15512 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 43 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 334657 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 334636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 113991 # Number of instructions committed system.cpu.committedOps 114022 # Number of ops (including micro ops) committed -system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.935819 # CPI: cycles per instruction -system.cpu.ipc 0.340620 # IPC: instructions per cycle +system.cpu.cpi 2.935635 # CPI: cycles per instruction +system.cpu.ipc 0.340642 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction @@ -344,38 +344,38 @@ system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 114022 # Class of committed instruction -system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked -system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked +system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits -system.cpu.dcache.overall_hits::total 44060 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits +system.cpu.dcache.overall_hits::total 44057 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses @@ -384,42 +384,42 @@ system.cpu.dcache.demand_misses::cpu.data 459 # n system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses system.cpu.dcache.overall_misses::total 459 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,14 +442,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 268 system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses @@ -458,68 +458,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18 # number of replacements -system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101823 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits -system.cpu.icache.overall_hits::total 49677 # number of overall hits +system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101789 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits +system.cpu.icache.overall_hits::total 49660 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses system.cpu.icache.overall_misses::total 823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,36 +534,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 823 system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id @@ -571,7 +571,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits @@ -594,16 +594,16 @@ system.cpu.l2cache.overall_misses::cpu.data 267 # system.cpu.l2cache.overall_misses::total 1090 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) @@ -632,16 +632,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -662,16 +662,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 267 system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -686,23 +686,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution @@ -740,7 +740,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 891 # Transaction distribution system.membus.trans_dist::ReadExReq 199 # Transaction distribution system.membus.trans_dist::ReadExResp 199 # Transaction distribution @@ -761,7 +761,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1090 # Request fanout histogram -system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) |