diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing')
5 files changed, 1425 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini new file mode 100644 index 000000000..6c2c774c6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json new file mode 100644 index 000000000..16fd9afa3 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout new file mode 100755 index 000000000..baa378d02 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:30 +gem5 executing on zizzer, pid 34063 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) +Exiting @ tick 138549500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt new file mode 100644 index 000000000..918afc87c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt @@ -0,0 +1,519 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000139 # Number of seconds simulated +sim_ticks 138549500 # Number of ticks simulated +final_tick 138549500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 338688 # Simulator instruction rate (inst/s) +host_op_rate 338651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 708977788 # Simulator tick rate (ticks/s) +host_mem_usage 242940 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +sim_insts 66173 # Number of instructions simulated +sim_ops 66173 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 33600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16064 # Number of bytes read from this memory +system.physmem.bytes_read::total 49664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 33600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 33600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 251 # Number of read requests responded to by this memory +system.physmem.num_reads::total 776 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 242512604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 115944121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 358456725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 242512604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 242512604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 242512604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 115944121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 358456725 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 138549500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 277099 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 66173 # Number of instructions committed +system.cpu.committedOps 66173 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 5169 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls +system.cpu.num_int_insts 66174 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 89437 # number of times the integer registers were read +system.cpu.num_int_register_writes 43419 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 24255 # number of memory refs +system.cpu.num_load_insts 11810 # Number of load instructions +system.cpu.num_store_insts 12445 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 277099 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 15480 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction +system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction +system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction +system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 66183 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 195.060322 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 24002 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 251 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 95.625498 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 195.060322 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.047622 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.047622 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.061279 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 48757 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 48757 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 11758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12243 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12243 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 24001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 24001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 24001 # number of overall hits +system.cpu.dcache.overall_hits::total 24001 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 200 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 200 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses +system.cpu.dcache.overall_misses::total 251 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3213000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3213000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12600000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12600000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15813000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15813000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15813000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15813000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12443 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12443 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24252 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24252 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24252 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24252 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016073 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.016073 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010350 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010350 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010350 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010350 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 251 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 251 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3162000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3162000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12400000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12400000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15562000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15562000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016073 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016073 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010350 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.010350 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 10 # number of replacements +system.cpu.icache.tags.tagsinuse 190.684855 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 65659 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 525 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 125.064762 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 190.684855 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093108 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093108 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 515 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.251465 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 132893 # Number of tag accesses +system.cpu.icache.tags.data_accesses 132893 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 65659 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65659 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65659 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65659 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65659 # number of overall hits +system.cpu.icache.overall_hits::total 65659 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 525 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 525 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 525 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 525 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 525 # number of overall misses +system.cpu.icache.overall_misses::total 525 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33076500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33076500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33076500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33076500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33076500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33076500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66184 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12675500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 39189000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26513500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12675500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 39189000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.904762 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.904762 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 786 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 50304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 776 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 776 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 787500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 376500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 776 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 576 # Transaction distribution +system.membus.trans_dist::ReadExReq 200 # Transaction distribution +system.membus.trans_dist::ReadExResp 200 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1552 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 49664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 49664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 776 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 776 # Request fanout histogram +system.membus.reqLayer0.occupancy 777000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3880000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |