diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt | 1551 |
1 files changed, 792 insertions, 759 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt index 3ac8f22bf..88923d3c0 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt @@ -1,763 +1,796 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000339 # Number of seconds simulated -sim_ticks 339173000 # Number of ticks simulated -final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215547 # Simulator instruction rate (inst/s) -host_op_rate 215545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244214530 # Simulator tick rate (ticks/s) -host_mem_usage 263004 # Number of bytes of host memory used -host_seconds 1.39 # Real time elapsed on the host -sim_insts 299354 # Number of instructions simulated -sim_ops 299354 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory -system.physmem.bytes_read::total 95040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1485 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 175 # Per bank write bursts -system.physmem.perBankRdBursts::1 68 # Per bank write bursts -system.physmem.perBankRdBursts::2 18 # Per bank write bursts -system.physmem.perBankRdBursts::3 72 # Per bank write bursts -system.physmem.perBankRdBursts::4 169 # Per bank write bursts -system.physmem.perBankRdBursts::5 291 # Per bank write bursts -system.physmem.perBankRdBursts::6 95 # Per bank write bursts -system.physmem.perBankRdBursts::7 4 # Per bank write bursts -system.physmem.perBankRdBursts::8 9 # Per bank write bursts -system.physmem.perBankRdBursts::9 115 # Per bank write bursts -system.physmem.perBankRdBursts::10 155 # Per bank write bursts -system.physmem.perBankRdBursts::11 169 # Per bank write bursts -system.physmem.perBankRdBursts::12 48 # Per bank write bursts -system.physmem.perBankRdBursts::13 55 # Per bank write bursts -system.physmem.perBankRdBursts::14 15 # Per bank write bursts -system.physmem.perBankRdBursts::15 27 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338956500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1485 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation -system.physmem.totQLat 20061750 # Total ticks spent queuing -system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.19 # Data bus utilization in percentage -system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1195 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 228253.54 # Average gap between requests -system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ) -system.physmem_0.averagePower 553.841711 # Core power per rank (mW) -system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states -system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states -system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ) -system.physmem_1.averagePower 536.767851 # Core power per rank (mW) -system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states -system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 80662 # Number of BP lookups -system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38260 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678346 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 299354 # Number of instructions committed -system.cpu.committedOps 299354 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.266033 # CPI: cycles per instruction -system.cpu.ipc 0.441300 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction -system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction -system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction -system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 11 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 5 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction -system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 299354 # Class of committed instruction -system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked -system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits -system.cpu.dcache.overall_hits::total 119892 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses -system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 80 # number of replacements -system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses -system.cpu.icache.tags.data_accesses 273390 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits -system.cpu.icache.overall_hits::total 134928 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses -system.cpu.icache.overall_misses::total 1178 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 80 # number of writebacks -system.cpu.icache.writebacks::total 80 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1178 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1178 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1178 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 13 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 202 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 202 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1167 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1167 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 116 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 116 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1167 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 318 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1167 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 318 # number of overall misses -system.cpu.l2cache.overall_misses::total 1485 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1178 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1178 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 118 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 118 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 320 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1498 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 320 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1498 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990662 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990662 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.983051 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.983051 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.993750 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.991322 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990662 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1167 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1167 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 116 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 116 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 80512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1498 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.036527 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1496 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1498 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 869000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1767000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1283 # Transaction distribution -system.membus.trans_dist::ReadExReq 202 # Transaction distribution -system.membus.trans_dist::ReadExResp 202 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1485 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1485 # Request fanout histogram -system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) +sim_seconds 0.000432 +sim_ticks 432134500 +final_tick 432134500 +sim_freq 1000000000000 +host_inst_rate 3359 +host_op_rate 3369 +host_tick_rate 3337861 +host_mem_usage 272860 +host_seconds 129.46 +sim_insts 434949 +sim_ops 436252 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 432134500 +system.physmem.bytes_read::cpu.inst 85184 +system.physmem.bytes_read::cpu.data 34432 +system.physmem.bytes_read::total 119616 +system.physmem.bytes_inst_read::cpu.inst 85184 +system.physmem.bytes_inst_read::total 85184 +system.physmem.num_reads::cpu.inst 1331 +system.physmem.num_reads::cpu.data 538 +system.physmem.num_reads::total 1869 +system.physmem.bw_read::cpu.inst 197123812 +system.physmem.bw_read::cpu.data 79678896 +system.physmem.bw_read::total 276802708 +system.physmem.bw_inst_read::cpu.inst 197123812 +system.physmem.bw_inst_read::total 197123812 +system.physmem.bw_total::cpu.inst 197123812 +system.physmem.bw_total::cpu.data 79678896 +system.physmem.bw_total::total 276802708 +system.physmem.readReqs 1869 +system.physmem.writeReqs 0 +system.physmem.readBursts 1869 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 119616 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 119616 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 257 +system.physmem.perBankRdBursts::1 275 +system.physmem.perBankRdBursts::2 180 +system.physmem.perBankRdBursts::3 185 +system.physmem.perBankRdBursts::4 157 +system.physmem.perBankRdBursts::5 101 +system.physmem.perBankRdBursts::6 126 +system.physmem.perBankRdBursts::7 65 +system.physmem.perBankRdBursts::8 51 +system.physmem.perBankRdBursts::9 72 +system.physmem.perBankRdBursts::10 18 +system.physmem.perBankRdBursts::11 38 +system.physmem.perBankRdBursts::12 89 +system.physmem.perBankRdBursts::13 78 +system.physmem.perBankRdBursts::14 74 +system.physmem.perBankRdBursts::15 103 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 432038000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 1869 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 1648 +system.physmem.rdQLenPdf::1 209 +system.physmem.rdQLenPdf::2 12 +system.physmem.rdQLenPdf::3 0 +system.physmem.rdQLenPdf::4 0 +system.physmem.rdQLenPdf::5 0 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 414 +system.physmem.bytesPerActivate::mean 284.599033 +system.physmem.bytesPerActivate::gmean 203.186885 +system.physmem.bytesPerActivate::stdev 239.597136 +system.physmem.bytesPerActivate::0-127 97 23.42% 23.42% +system.physmem.bytesPerActivate::128-255 125 30.19% 53.62% +system.physmem.bytesPerActivate::256-383 69 16.66% 70.28% +system.physmem.bytesPerActivate::384-511 58 14.00% 84.29% +system.physmem.bytesPerActivate::512-639 23 5.55% 89.85% +system.physmem.bytesPerActivate::640-767 14 3.38% 93.23% +system.physmem.bytesPerActivate::768-895 8 1.93% 95.16% +system.physmem.bytesPerActivate::896-1023 8 1.93% 97.10% +system.physmem.bytesPerActivate::1024-1151 12 2.89% 99.99% +system.physmem.bytesPerActivate::total 414 +system.physmem.totQLat 27138750 +system.physmem.totMemAccLat 62182500 +system.physmem.totBusLat 9345000 +system.physmem.avgQLat 14520.46 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 33270.46 +system.physmem.avgRdBW 276.80 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 276.80 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 2.16 +system.physmem.busUtilRead 2.16 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.06 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 1445 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 77.31 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 231159.97 +system.physmem.pageHitRate 77.31 +system.physmem_0.actEnergy 2156280 +system.physmem_0.preEnergy 1130910 +system.physmem_0.readEnergy 9610440 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 33805200 +system.physmem_0.actBackEnergy 22735020 +system.physmem_0.preBackEnergy 728640 +system.physmem_0.actPowerDownEnergy 167294430 +system.physmem_0.prePowerDownEnergy 5186400 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 242647320 +system.physmem_0.averagePower 561.508139 +system.physmem_0.totalIdleTime 380124250 +system.physmem_0.memoryStateTime::IDLE 312000 +system.physmem_0.memoryStateTime::REF 14300000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 13499750 +system.physmem_0.memoryStateTime::ACT 37116000 +system.physmem_0.memoryStateTime::ACT_PDN 366906750 +system.physmem_1.actEnergy 871080 +system.physmem_1.preEnergy 440220 +system.physmem_1.readEnergy 3734220 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 15366000 +system.physmem_1.actBackEnergy 9609630 +system.physmem_1.preBackEnergy 719520 +system.physmem_1.actPowerDownEnergy 53643840 +system.physmem_1.prePowerDownEnergy 14784960 +system.physmem_1.selfRefreshEnergy 62387520 +system.physmem_1.totalEnergy 161556990 +system.physmem_1.averagePower 373.857683 +system.physmem_1.totalIdleTime 409147000 +system.physmem_1.memoryStateTime::IDLE 1209000 +system.physmem_1.memoryStateTime::REF 6518000 +system.physmem_1.memoryStateTime::SREF 253044500 +system.physmem_1.memoryStateTime::PRE_PDN 38497750 +system.physmem_1.memoryStateTime::ACT 15214500 +system.physmem_1.memoryStateTime::ACT_PDN 117650750 +system.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.branchPred.lookups 119617 +system.cpu.branchPred.condPredicted 84602 +system.cpu.branchPred.condIncorrect 8795 +system.cpu.branchPred.BTBLookups 74150 +system.cpu.branchPred.BTBHits 39240 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 52.919757 +system.cpu.branchPred.usedRAS 0 +system.cpu.branchPred.RASInCorrect 0 +system.cpu.branchPred.indirectLookups 24116 +system.cpu.branchPred.indirectHits 14470 +system.cpu.branchPred.indirectMisses 9646 +system.cpu.branchPredindirectMispredicted 4958 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 220 +system.cpu.pwrStateResidencyTicks::ON 432134500 +system.cpu.numCycles 864269 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 434949 +system.cpu.committedOps 436252 +system.cpu.discardedOps 24002 +system.cpu.numFetchSuspends 0 +system.cpu.cpi 1.987058 +system.cpu.ipc 0.503256 +system.cpu.op_class_0::No_OpClass 224 0.05% 0.05% +system.cpu.op_class_0::IntAlu 256681 58.83% 58.88% +system.cpu.op_class_0::IntMult 710 0.16% 59.05% +system.cpu.op_class_0::IntDiv 992 0.22% 59.27% +system.cpu.op_class_0::FloatAdd 133 0.03% 59.30% +system.cpu.op_class_0::FloatCmp 170 0.03% 59.34% +system.cpu.op_class_0::FloatCvt 128 0.02% 59.37% +system.cpu.op_class_0::FloatMult 30 0.00% 59.38% +system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.38% +system.cpu.op_class_0::FloatDiv 11 0.00% 59.38% +system.cpu.op_class_0::FloatMisc 0 0.00% 59.38% +system.cpu.op_class_0::FloatSqrt 5 0.00% 59.38% +system.cpu.op_class_0::SimdAdd 0 0.00% 59.38% +system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.38% +system.cpu.op_class_0::SimdAlu 0 0.00% 59.38% +system.cpu.op_class_0::SimdCmp 0 0.00% 59.38% +system.cpu.op_class_0::SimdCvt 0 0.00% 59.38% +system.cpu.op_class_0::SimdMisc 0 0.00% 59.38% +system.cpu.op_class_0::SimdMult 0 0.00% 59.38% +system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.38% +system.cpu.op_class_0::SimdShift 0 0.00% 59.38% +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.38% +system.cpu.op_class_0::SimdSqrt 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatMult 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 59.38% +system.cpu.op_class_0::MemRead 109574 25.11% 84.50% +system.cpu.op_class_0::MemWrite 66842 15.32% 99.82% +system.cpu.op_class_0::FloatMemRead 571 0.13% 99.95% +system.cpu.op_class_0::FloatMemWrite 181 0.04% 99.99% +system.cpu.op_class_0::IprAccess 0 0.00% 99.99% +system.cpu.op_class_0::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class_0::total 436252 +system.cpu.tickCycles 588283 +system.cpu.idleCycles 275986 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.dcache.tags.replacements 1 +system.cpu.dcache.tags.tagsinuse 417.816714 +system.cpu.dcache.tags.total_refs 180665 +system.cpu.dcache.tags.sampled_refs 539 +system.cpu.dcache.tags.avg_refs 335.185528 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 417.816714 +system.cpu.dcache.tags.occ_percent::cpu.data 0.102006 +system.cpu.dcache.tags.occ_percent::total 0.102006 +system.cpu.dcache.tags.occ_task_id_blocks::1024 538 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 504 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.131347 +system.cpu.dcache.tags.tag_accesses 363297 +system.cpu.dcache.tags.data_accesses 363297 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.dcache.ReadReq_hits::cpu.data 112284 +system.cpu.dcache.ReadReq_hits::total 112284 +system.cpu.dcache.WriteReq_hits::cpu.data 64864 +system.cpu.dcache.WriteReq_hits::total 64864 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1758 +system.cpu.dcache.LoadLockedReq_hits::total 1758 +system.cpu.dcache.StoreCondReq_hits::cpu.data 1759 +system.cpu.dcache.StoreCondReq_hits::total 1759 +system.cpu.dcache.demand_hits::cpu.data 177148 +system.cpu.dcache.demand_hits::total 177148 +system.cpu.dcache.overall_hits::cpu.data 177148 +system.cpu.dcache.overall_hits::total 177148 +system.cpu.dcache.ReadReq_misses::cpu.data 313 +system.cpu.dcache.ReadReq_misses::total 313 +system.cpu.dcache.WriteReq_misses::cpu.data 400 +system.cpu.dcache.WriteReq_misses::total 400 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 +system.cpu.dcache.LoadLockedReq_misses::total 1 +system.cpu.dcache.demand_misses::cpu.data 713 +system.cpu.dcache.demand_misses::total 713 +system.cpu.dcache.overall_misses::cpu.data 713 +system.cpu.dcache.overall_misses::total 713 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28002500 +system.cpu.dcache.ReadReq_miss_latency::total 28002500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33938000 +system.cpu.dcache.WriteReq_miss_latency::total 33938000 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 92000 +system.cpu.dcache.demand_miss_latency::cpu.data 61940500 +system.cpu.dcache.demand_miss_latency::total 61940500 +system.cpu.dcache.overall_miss_latency::cpu.data 61940500 +system.cpu.dcache.overall_miss_latency::total 61940500 +system.cpu.dcache.ReadReq_accesses::cpu.data 112597 +system.cpu.dcache.ReadReq_accesses::total 112597 +system.cpu.dcache.WriteReq_accesses::cpu.data 65264 +system.cpu.dcache.WriteReq_accesses::total 65264 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1759 +system.cpu.dcache.LoadLockedReq_accesses::total 1759 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1759 +system.cpu.dcache.StoreCondReq_accesses::total 1759 +system.cpu.dcache.demand_accesses::cpu.data 177861 +system.cpu.dcache.demand_accesses::total 177861 +system.cpu.dcache.overall_accesses::cpu.data 177861 +system.cpu.dcache.overall_accesses::total 177861 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002779 +system.cpu.dcache.ReadReq_miss_rate::total 0.002779 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006128 +system.cpu.dcache.WriteReq_miss_rate::total 0.006128 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000568 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000568 +system.cpu.dcache.demand_miss_rate::cpu.data 0.004008 +system.cpu.dcache.demand_miss_rate::total 0.004008 +system.cpu.dcache.overall_miss_rate::cpu.data 0.004008 +system.cpu.dcache.overall_miss_rate::total 0.004008 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89464.856230 +system.cpu.dcache.ReadReq_avg_miss_latency::total 89464.856230 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84845 +system.cpu.dcache.WriteReq_avg_miss_latency::total 84845 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92000 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 86873.071528 +system.cpu.dcache.demand_avg_miss_latency::total 86873.071528 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 86873.071528 +system.cpu.dcache.overall_avg_miss_latency::total 86873.071528 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 1 +system.cpu.dcache.writebacks::total 1 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3 +system.cpu.dcache.ReadReq_mshr_hits::total 3 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 172 +system.cpu.dcache.WriteReq_mshr_hits::total 172 +system.cpu.dcache.demand_mshr_hits::cpu.data 175 +system.cpu.dcache.demand_mshr_hits::total 175 +system.cpu.dcache.overall_mshr_hits::cpu.data 175 +system.cpu.dcache.overall_mshr_hits::total 175 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 310 +system.cpu.dcache.ReadReq_mshr_misses::total 310 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 228 +system.cpu.dcache.WriteReq_mshr_misses::total 228 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 +system.cpu.dcache.demand_mshr_misses::cpu.data 538 +system.cpu.dcache.demand_mshr_misses::total 538 +system.cpu.dcache.overall_mshr_misses::cpu.data 538 +system.cpu.dcache.overall_mshr_misses::total 538 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27518000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27518000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19817000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19817000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 91000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 91000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47335000 +system.cpu.dcache.demand_mshr_miss_latency::total 47335000 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47335000 +system.cpu.dcache.overall_mshr_miss_latency::total 47335000 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002753 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002753 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003493 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003493 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.000568 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000568 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003024 +system.cpu.dcache.demand_mshr_miss_rate::total 0.003024 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003024 +system.cpu.dcache.overall_mshr_miss_rate::total 0.003024 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88767.741935 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88767.741935 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86916.666666 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86916.666666 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 91000 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 91000 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87983.271375 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87983.271375 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87983.271375 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87983.271375 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.icache.tags.replacements 114 +system.cpu.icache.tags.tagsinuse 830.110556 +system.cpu.icache.tags.total_refs 160527 +system.cpu.icache.tags.sampled_refs 1338 +system.cpu.icache.tags.avg_refs 119.975336 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 830.110556 +system.cpu.icache.tags.occ_percent::cpu.inst 0.405327 +system.cpu.icache.tags.occ_percent::total 0.405327 +system.cpu.icache.tags.occ_task_id_blocks::1024 1224 +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 +system.cpu.icache.tags.age_task_id_blocks_1024::1 105 +system.cpu.icache.tags.age_task_id_blocks_1024::2 1067 +system.cpu.icache.tags.occ_task_id_percent::1024 0.597656 +system.cpu.icache.tags.tag_accesses 325070 +system.cpu.icache.tags.data_accesses 325070 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.icache.ReadReq_hits::cpu.inst 160527 +system.cpu.icache.ReadReq_hits::total 160527 +system.cpu.icache.demand_hits::cpu.inst 160527 +system.cpu.icache.demand_hits::total 160527 +system.cpu.icache.overall_hits::cpu.inst 160527 +system.cpu.icache.overall_hits::total 160527 +system.cpu.icache.ReadReq_misses::cpu.inst 1339 +system.cpu.icache.ReadReq_misses::total 1339 +system.cpu.icache.demand_misses::cpu.inst 1339 +system.cpu.icache.demand_misses::total 1339 +system.cpu.icache.overall_misses::cpu.inst 1339 +system.cpu.icache.overall_misses::total 1339 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 114378500 +system.cpu.icache.ReadReq_miss_latency::total 114378500 +system.cpu.icache.demand_miss_latency::cpu.inst 114378500 +system.cpu.icache.demand_miss_latency::total 114378500 +system.cpu.icache.overall_miss_latency::cpu.inst 114378500 +system.cpu.icache.overall_miss_latency::total 114378500 +system.cpu.icache.ReadReq_accesses::cpu.inst 161866 +system.cpu.icache.ReadReq_accesses::total 161866 +system.cpu.icache.demand_accesses::cpu.inst 161866 +system.cpu.icache.demand_accesses::total 161866 +system.cpu.icache.overall_accesses::cpu.inst 161866 +system.cpu.icache.overall_accesses::total 161866 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008272 +system.cpu.icache.ReadReq_miss_rate::total 0.008272 +system.cpu.icache.demand_miss_rate::cpu.inst 0.008272 +system.cpu.icache.demand_miss_rate::total 0.008272 +system.cpu.icache.overall_miss_rate::cpu.inst 0.008272 +system.cpu.icache.overall_miss_rate::total 0.008272 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85420.836445 +system.cpu.icache.ReadReq_avg_miss_latency::total 85420.836445 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85420.836445 +system.cpu.icache.demand_avg_miss_latency::total 85420.836445 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85420.836445 +system.cpu.icache.overall_avg_miss_latency::total 85420.836445 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 114 +system.cpu.icache.writebacks::total 114 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 +system.cpu.icache.ReadReq_mshr_misses::total 1339 +system.cpu.icache.demand_mshr_misses::cpu.inst 1339 +system.cpu.icache.demand_mshr_misses::total 1339 +system.cpu.icache.overall_mshr_misses::cpu.inst 1339 +system.cpu.icache.overall_mshr_misses::total 1339 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 113040500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 113040500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 113040500 +system.cpu.icache.demand_mshr_miss_latency::total 113040500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 113040500 +system.cpu.icache.overall_mshr_miss_latency::total 113040500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008272 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008272 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008272 +system.cpu.icache.demand_mshr_miss_rate::total 0.008272 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008272 +system.cpu.icache.overall_mshr_miss_rate::total 0.008272 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84421.583271 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84421.583271 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84421.583271 +system.cpu.icache.demand_avg_mshr_miss_latency::total 84421.583271 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84421.583271 +system.cpu.icache.overall_avg_mshr_miss_latency::total 84421.583271 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 1298.103428 +system.cpu.l2cache.tags.total_refs 123 +system.cpu.l2cache.tags.sampled_refs 1869 +system.cpu.l2cache.tags.avg_refs 0.065810 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 880.639127 +system.cpu.l2cache.tags.occ_blocks::cpu.data 417.464301 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026874 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012739 +system.cpu.l2cache.tags.occ_percent::total 0.039614 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1869 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1678 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.057037 +system.cpu.l2cache.tags.tag_accesses 17813 +system.cpu.l2cache.tags.data_accesses 17813 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 1 +system.cpu.l2cache.WritebackDirty_hits::total 1 +system.cpu.l2cache.WritebackClean_hits::writebacks 114 +system.cpu.l2cache.WritebackClean_hits::total 114 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7 +system.cpu.l2cache.ReadCleanReq_hits::total 7 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_hits::total 1 +system.cpu.l2cache.demand_hits::cpu.inst 7 +system.cpu.l2cache.demand_hits::cpu.data 1 +system.cpu.l2cache.demand_hits::total 8 +system.cpu.l2cache.overall_hits::cpu.inst 7 +system.cpu.l2cache.overall_hits::cpu.data 1 +system.cpu.l2cache.overall_hits::total 8 +system.cpu.l2cache.ReadExReq_misses::cpu.data 228 +system.cpu.l2cache.ReadExReq_misses::total 228 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1332 +system.cpu.l2cache.ReadCleanReq_misses::total 1332 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 310 +system.cpu.l2cache.ReadSharedReq_misses::total 310 +system.cpu.l2cache.demand_misses::cpu.inst 1332 +system.cpu.l2cache.demand_misses::cpu.data 538 +system.cpu.l2cache.demand_misses::total 1870 +system.cpu.l2cache.overall_misses::cpu.inst 1332 +system.cpu.l2cache.overall_misses::cpu.data 538 +system.cpu.l2cache.overall_misses::total 1870 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19473500 +system.cpu.l2cache.ReadExReq_miss_latency::total 19473500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 110960000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 110960000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 27129500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 27129500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 110960000 +system.cpu.l2cache.demand_miss_latency::cpu.data 46603000 +system.cpu.l2cache.demand_miss_latency::total 157563000 +system.cpu.l2cache.overall_miss_latency::cpu.inst 110960000 +system.cpu.l2cache.overall_miss_latency::cpu.data 46603000 +system.cpu.l2cache.overall_miss_latency::total 157563000 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1 +system.cpu.l2cache.WritebackDirty_accesses::total 1 +system.cpu.l2cache.WritebackClean_accesses::writebacks 114 +system.cpu.l2cache.WritebackClean_accesses::total 114 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 228 +system.cpu.l2cache.ReadExReq_accesses::total 228 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1339 +system.cpu.l2cache.ReadCleanReq_accesses::total 1339 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 311 +system.cpu.l2cache.ReadSharedReq_accesses::total 311 +system.cpu.l2cache.demand_accesses::cpu.inst 1339 +system.cpu.l2cache.demand_accesses::cpu.data 539 +system.cpu.l2cache.demand_accesses::total 1878 +system.cpu.l2cache.overall_accesses::cpu.inst 1339 +system.cpu.l2cache.overall_accesses::cpu.data 539 +system.cpu.l2cache.overall_accesses::total 1878 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994772 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994772 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.996784 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.996784 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994772 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.demand_miss_rate::total 0.995740 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994772 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.overall_miss_rate::total 0.995740 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85410.087719 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85410.087719 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83303.303303 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83303.303303 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87514.516129 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87514.516129 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83303.303303 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86622.676579 +system.cpu.l2cache.demand_avg_miss_latency::total 84258.288770 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83303.303303 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86622.676579 +system.cpu.l2cache.overall_avg_miss_latency::total 84258.288770 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 228 +system.cpu.l2cache.ReadExReq_mshr_misses::total 228 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1332 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1332 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 310 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 310 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1332 +system.cpu.l2cache.demand_mshr_misses::cpu.data 538 +system.cpu.l2cache.demand_mshr_misses::total 1870 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1332 +system.cpu.l2cache.overall_mshr_misses::cpu.data 538 +system.cpu.l2cache.overall_mshr_misses::total 1870 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17193500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17193500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 97650000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 97650000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24029500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24029500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97650000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 41223000 +system.cpu.l2cache.demand_mshr_miss_latency::total 138873000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97650000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 41223000 +system.cpu.l2cache.overall_mshr_miss_latency::total 138873000 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994772 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994772 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.996784 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.996784 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994772 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995740 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994772 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995740 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75410.087719 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75410.087719 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73310.810810 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73310.810810 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77514.516129 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77514.516129 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73310.810810 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76622.676579 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74263.636363 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73310.810810 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76622.676579 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74263.636363 +system.cpu.toL2Bus.snoop_filter.tot_requests 1993 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 116 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.toL2Bus.trans_dist::ReadResp 1649 +system.cpu.toL2Bus.trans_dist::WritebackDirty 1 +system.cpu.toL2Bus.trans_dist::WritebackClean 114 +system.cpu.toL2Bus.trans_dist::ReadExReq 228 +system.cpu.toL2Bus.trans_dist::ReadExResp 228 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1339 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 311 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2791 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1079 +system.cpu.toL2Bus.pkt_count::total 3870 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92928 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34560 +system.cpu.toL2Bus.pkt_size::total 127488 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1878 +system.cpu.toL2Bus.snoop_fanout::mean 0.000532 +system.cpu.toL2Bus.snoop_fanout::stdev 0.023075 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1877 99.94% 99.94% +system.cpu.toL2Bus.snoop_fanout::1 1 0.05% 99.99% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 1878 +system.cpu.toL2Bus.reqLayer0.occupancy 1111500 +system.cpu.toL2Bus.reqLayer0.utilization 0.2 +system.cpu.toL2Bus.respLayer0.occupancy 2007000 +system.cpu.toL2Bus.respLayer0.utilization 0.4 +system.cpu.toL2Bus.respLayer1.occupancy 808500 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 1869 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 432134500 +system.membus.trans_dist::ReadResp 1641 +system.membus.trans_dist::ReadExReq 228 +system.membus.trans_dist::ReadExResp 228 +system.membus.trans_dist::ReadSharedReq 1641 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3738 +system.membus.pkt_count::total 3738 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 119616 +system.membus.pkt_size::total 119616 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1869 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1869 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1869 +system.membus.reqLayer0.occupancy 2203500 +system.membus.reqLayer0.utilization 0.5 +system.membus.respLayer1.occupancy 9944750 +system.membus.respLayer1.utilization 2.3 ---------- End Simulation Statistics ---------- |