diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt | 458 |
1 files changed, 229 insertions, 229 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt index c2cf1b21c..042307b53 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000339 # Number of seconds simulated -sim_ticks 339160000 # Number of ticks simulated -final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 339173000 # Number of ticks simulated +final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25032 # Simulator instruction rate (inst/s) -host_op_rate 25032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28360795 # Simulator tick rate (ticks/s) -host_mem_usage 244952 # Number of bytes of host memory used -host_seconds 11.96 # Real time elapsed on the host +host_inst_rate 215547 # Simulator instruction rate (inst/s) +host_op_rate 215545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244214530 # Simulator tick rate (ticks/s) +host_mem_usage 263004 # Number of bytes of host memory used +host_seconds 1.39 # Real time elapsed on the host sim_insts 299354 # Number of instructions simulated sim_ops 299354 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory system.physmem.bytes_read::total 95040 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 74688 # Nu system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1485 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338943500 # Total gap between requests +system.physmem.totGap 338956500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation -system.physmem.totQLat 19805250 # Total ticks spent queuing -system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 20061750 # Total ticks spent queuing +system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.19 # Data bus utilization in percentage @@ -221,58 +221,58 @@ system.physmem.readRowHits 1195 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 228244.78 # Average gap between requests +system.physmem.avgGap 228253.54 # Average gap between requests system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ) -system.physmem_0.averagePower 553.629673 # Core power per rank (mW) -system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states +system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ) +system.physmem_0.averagePower 553.841711 # Core power per rank (mW) +system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ) -system.physmem_1.averagePower 537.082660 # Core power per rank (mW) -system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states +system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ) +system.physmem_1.averagePower 536.767851 # Core power per rank (mW) +system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 80709 # Number of BP lookups -system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38294 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 80662 # Number of BP lookups +system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38260 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678320 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678346 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 299354 # Number of instructions committed system.cpu.committedOps 299354 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.265946 # CPI: cycles per instruction -system.cpu.ipc 0.441317 # IPC: instructions per cycle +system.cpu.cpi 2.266033 # CPI: cycles per instruction +system.cpu.ipc 0.441300 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction @@ -344,34 +344,34 @@ system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 299354 # Class of committed instruction -system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked -system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked +system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits -system.cpu.dcache.overall_hits::total 119907 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits +system.cpu.dcache.overall_hits::total 119892 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses @@ -380,22 +380,22 @@ system.cpu.dcache.demand_misses::cpu.data 511 # n system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses @@ -404,14 +404,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,84 +432,84 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 320 system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 80 # number of replacements -system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 273696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits -system.cpu.icache.overall_hits::total 135081 # number of overall hits +system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses +system.cpu.icache.tags.data_accesses 273390 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits +system.cpu.icache.overall_hits::total 134928 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses system.cpu.icache.overall_misses::total 1178 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,36 +524,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1178 system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id @@ -561,7 +561,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits @@ -588,16 +588,16 @@ system.cpu.l2cache.overall_misses::cpu.data 318 # system.cpu.l2cache.overall_misses::total 1485 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) @@ -626,16 +626,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -656,16 +656,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 318 system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses @@ -680,23 +680,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution @@ -734,7 +734,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1283 # Transaction distribution system.membus.trans_dist::ReadExReq 202 # Transaction distribution system.membus.trans_dist::ReadExResp 202 # Transaction distribution @@ -755,9 +755,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1485 # Request fanout histogram -system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |