diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt | 645 |
1 files changed, 645 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..fef27ae57 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt @@ -0,0 +1,645 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.006394 # Number of seconds simulated +sim_ticks 6393532 # Number of ticks simulated +final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 13428 # Simulator instruction rate (inst/s) +host_op_rate 13428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 286950 # Simulator tick rate (ticks/s) +host_mem_usage 412476 # Number of bytes of host memory used +host_seconds 22.28 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6256384 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 6256384 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 97756 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 97756 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 97760 # Number of read requests accepted +system.mem_ctrls.writeReqs 97756 # Number of write requests accepted +system.mem_ctrls.readBursts 97760 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 97756 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 3295040 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2961600 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 3443712 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 6256640 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 6256384 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 46275 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 43917 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 352 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1012 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 26 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 3288 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5256 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 9431 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 7439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1368 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1039 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 2533 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14031 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 3005 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1537 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 918 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 359 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 1066 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 34 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3555 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 5446 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9633 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8466 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1431 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 1069 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2579 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 14351 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 3053 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1590 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 923 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 6393460 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 97760 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 97756 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 51485 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 306 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 334 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2779 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 3333 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 3383 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 3473 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 3559 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 3516 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 3321 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 3315 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 20661 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.074440 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 208.715959 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 320.266569 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 5014 24.27% 24.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 6296 30.47% 54.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 3457 16.73% 71.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1315 6.36% 77.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 736 3.56% 81.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 594 2.87% 84.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 389 1.88% 86.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 293 1.42% 87.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 2567 12.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 20661 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 3312 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.540459 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.485552 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.332467 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 139 4.20% 4.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1517 45.80% 50.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1421 42.90% 92.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 229 6.91% 99.82% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 5 0.15% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.03% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 3312 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 3312 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.246377 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.229566 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.773105 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2986 90.16% 90.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.42% 90.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 147 4.44% 95.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 153 4.62% 99.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 11 0.33% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.03% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 3312 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1034437 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 2012652 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 257425 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.09 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39.09 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 515.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 538.62 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 978.59 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 978.55 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.23 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.21 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 36136 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 48490 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 70.19 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.06 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.70 # Average gap between requests +system.mem_ctrls.pageHitRate 80.35 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 95226180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 51522576 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 321836928 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 250476480 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 501546240.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 829542432 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 11702016 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1925180016 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 78745728 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 34138560 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 4099917156 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 641.260129 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 4543849 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 6758 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 212226 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 116933 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 205067 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1630662 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 4221886 # Time in different power states +system.mem_ctrls_1.actEnergy 52336200 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 28311528 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 266327712 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 198927936 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 482492400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 818266464 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 13925376 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1847919480 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 72638976 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 80402640 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 3861548712 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 603.977381 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 4562502 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 13661 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 204136 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 321205 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 189164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1612911 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 4052455 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 6393532 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 6393532 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 6393532 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 195516 # delay histogram for all message +system.ruby.delayHist | 195516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 195516 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 417744 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 417744 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 417744 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 417743 +system.ruby.latency_hist_seqr::mean 14.304941 +system.ruby.latency_hist_seqr::gmean 2.506373 +system.ruby.latency_hist_seqr::stdev 29.993401 +system.ruby.latency_hist_seqr | 367877 88.06% 88.06% | 46330 11.09% 99.15% | 2431 0.58% 99.74% | 380 0.09% 99.83% | 382 0.09% 99.92% | 309 0.07% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00% +system.ruby.latency_hist_seqr::total 417743 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 319983 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 319983 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 319983 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 97760 +system.ruby.miss_latency_hist_seqr::mean 57.853989 +system.ruby.miss_latency_hist_seqr::gmean 50.720255 +system.ruby.miss_latency_hist_seqr::stdev 36.989317 +system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 97760 +system.ruby.Directory.incomplete_times_seqr 97759 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.645070 +system.ruby.network.routers0.msg_count.Control::2 97760 +system.ruby.network.routers0.msg_count.Data::2 97756 +system.ruby.network.routers0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.msg_bytes.Control::2 782080 +system.ruby.network.routers0.msg_bytes.Data::2 7038432 +system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.645070 +system.ruby.network.routers1.msg_count.Control::2 97760 +system.ruby.network.routers1.msg_count.Data::2 97756 +system.ruby.network.routers1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.msg_bytes.Control::2 782080 +system.ruby.network.routers1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.645070 +system.ruby.network.routers2.msg_count.Control::2 97760 +system.ruby.network.routers2.msg_count.Data::2 97756 +system.ruby.network.routers2.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.msg_bytes.Control::2 782080 +system.ruby.network.routers2.msg_bytes.Data::2 7038432 +system.ruby.network.routers2.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 293280 +system.ruby.network.msg_count.Data 293268 +system.ruby.network.msg_count.Response_Data 293280 +system.ruby.network.msg_count.Writeback_Control 293268 +system.ruby.network.msg_byte.Control 2346240 +system.ruby.network.msg_byte.Data 21115296 +system.ruby.network.msg_byte.Response_Data 21116160 +system.ruby.network.msg_byte.Writeback_Control 2346144 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.645195 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers0.throttle1.link_utilization 7.644945 +system.ruby.network.routers0.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers0.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle0.link_utilization 7.644945 +system.ruby.network.routers1.throttle0.msg_count.Control::2 97760 +system.ruby.network.routers1.throttle0.msg_count.Data::2 97756 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 782080 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle1.link_utilization 7.645195 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle0.link_utilization 7.645195 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle1.link_utilization 7.644945 +system.ruby.network.routers2.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers2.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7038432 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 97760 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 97756 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 97756 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 97756 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 69843 +system.ruby.LD.latency_hist_seqr::mean 28.322194 +system.ruby.LD.latency_hist_seqr::gmean 7.510857 +system.ruby.LD.latency_hist_seqr::stdev 36.108227 +system.ruby.LD.latency_hist_seqr | 55897 80.03% 80.03% | 12888 18.45% 98.49% | 741 1.06% 99.55% | 131 0.19% 99.73% | 105 0.15% 99.88% | 76 0.11% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 69843 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 33083 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 33083 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 33083 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 36760 +system.ruby.LD.miss_latency_hist_seqr::mean 52.911425 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.miss_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 36760 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 48546 +system.ruby.ST.latency_hist_seqr::mean 14.735838 +system.ruby.ST.latency_hist_seqr::gmean 3.058930 +system.ruby.ST.latency_hist_seqr::stdev 27.657147 +system.ruby.ST.latency_hist_seqr | 44298 91.25% 91.25% | 3958 8.15% 99.40% | 180 0.37% 99.77% | 35 0.07% 99.85% | 42 0.09% 99.93% | 23 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 10 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 48546 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 33996 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33996 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 33996 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 14550 +system.ruby.ST.miss_latency_hist_seqr::mean 46.829553 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.miss_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.miss_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 14550 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 299354 +system.ruby.IFETCH.latency_hist_seqr::mean 10.964664 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.878483 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.751002 +system.ruby.IFETCH.latency_hist_seqr | 267682 89.42% 89.42% | 29484 9.85% 99.27% | 1510 0.50% 99.77% | 214 0.07% 99.84% | 235 0.08% 99.92% | 210 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 299354 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 252904 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 252904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 252904 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.miss_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 46450 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 97760 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.853989 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.720255 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.989317 +system.ruby.Directory.miss_mach_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 97760 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36760 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.911425 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36760 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 14550 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.829553 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 14550 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46450 +system.ruby.Directory_Controller.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 97756 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 69843 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 299354 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 48546 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 97760 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 36760 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 46450 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 14550 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 33083 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 252904 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 33996 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 83210 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 14550 0.00% 0.00% + +---------- End Simulation Statistics ---------- |