diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby')
5 files changed, 3823 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini new file mode 100644 index 000000000..0a11055d6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 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+type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json new file mode 100644 index 000000000..e041cd07a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": 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"system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": 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"type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout new file mode 100755 index 000000000..6698d57dd --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34074 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 6393532 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..fef27ae57 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt @@ -0,0 +1,645 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.006394 # Number of seconds simulated +sim_ticks 6393532 # Number of ticks simulated +final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 13428 # Simulator instruction rate (inst/s) +host_op_rate 13428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 286950 # Simulator tick rate (ticks/s) +host_mem_usage 412476 # Number of bytes of host memory used +host_seconds 22.28 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6256384 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 6256384 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 97756 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 97756 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 97760 # Number of read requests accepted +system.mem_ctrls.writeReqs 97756 # Number of write requests accepted +system.mem_ctrls.readBursts 97760 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 97756 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 3295040 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2961600 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 3443712 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 6256640 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 6256384 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 46275 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 43917 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 352 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1012 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 26 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 3288 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5256 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 9431 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 7439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1368 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1039 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 2533 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14031 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 3005 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1537 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 918 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 359 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 1066 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 34 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3555 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 5446 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9633 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8466 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1431 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 1069 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2579 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 14351 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 3053 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1590 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 923 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 6393460 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 97760 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 97756 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 51485 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 306 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 334 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2779 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 3333 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 3383 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 3473 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 3559 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 3516 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 3321 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 3315 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 20661 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.074440 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 208.715959 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 320.266569 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 5014 24.27% 24.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 6296 30.47% 54.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 3457 16.73% 71.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1315 6.36% 77.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 736 3.56% 81.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 594 2.87% 84.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 389 1.88% 86.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 293 1.42% 87.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 2567 12.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 20661 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 3312 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.540459 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.485552 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.332467 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 139 4.20% 4.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1517 45.80% 50.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1421 42.90% 92.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 229 6.91% 99.82% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 5 0.15% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.03% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 3312 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 3312 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.246377 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.229566 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.773105 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2986 90.16% 90.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.42% 90.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 147 4.44% 95.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 153 4.62% 99.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 11 0.33% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.03% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 3312 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1034437 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 2012652 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 257425 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.09 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39.09 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 515.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 538.62 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 978.59 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 978.55 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.23 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.21 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 36136 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 48490 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 70.19 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.06 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.70 # Average gap between requests +system.mem_ctrls.pageHitRate 80.35 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 95226180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 51522576 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 321836928 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 250476480 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 501546240.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 829542432 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 11702016 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1925180016 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 78745728 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 34138560 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 4099917156 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 641.260129 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 4543849 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 6758 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 212226 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 116933 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 205067 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1630662 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 4221886 # Time in different power states +system.mem_ctrls_1.actEnergy 52336200 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 28311528 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 266327712 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 198927936 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 482492400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 818266464 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 13925376 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1847919480 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 72638976 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 80402640 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 3861548712 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 603.977381 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 4562502 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 13661 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 204136 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 321205 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 189164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1612911 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 4052455 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 6393532 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 6393532 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 6393532 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 195516 # delay histogram for all message +system.ruby.delayHist | 195516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 195516 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 417744 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 417744 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 417744 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 417743 +system.ruby.latency_hist_seqr::mean 14.304941 +system.ruby.latency_hist_seqr::gmean 2.506373 +system.ruby.latency_hist_seqr::stdev 29.993401 +system.ruby.latency_hist_seqr | 367877 88.06% 88.06% | 46330 11.09% 99.15% | 2431 0.58% 99.74% | 380 0.09% 99.83% | 382 0.09% 99.92% | 309 0.07% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00% +system.ruby.latency_hist_seqr::total 417743 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 319983 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 319983 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 319983 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 97760 +system.ruby.miss_latency_hist_seqr::mean 57.853989 +system.ruby.miss_latency_hist_seqr::gmean 50.720255 +system.ruby.miss_latency_hist_seqr::stdev 36.989317 +system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 97760 +system.ruby.Directory.incomplete_times_seqr 97759 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.645070 +system.ruby.network.routers0.msg_count.Control::2 97760 +system.ruby.network.routers0.msg_count.Data::2 97756 +system.ruby.network.routers0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.msg_bytes.Control::2 782080 +system.ruby.network.routers0.msg_bytes.Data::2 7038432 +system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.645070 +system.ruby.network.routers1.msg_count.Control::2 97760 +system.ruby.network.routers1.msg_count.Data::2 97756 +system.ruby.network.routers1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.msg_bytes.Control::2 782080 +system.ruby.network.routers1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.645070 +system.ruby.network.routers2.msg_count.Control::2 97760 +system.ruby.network.routers2.msg_count.Data::2 97756 +system.ruby.network.routers2.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.msg_bytes.Control::2 782080 +system.ruby.network.routers2.msg_bytes.Data::2 7038432 +system.ruby.network.routers2.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 293280 +system.ruby.network.msg_count.Data 293268 +system.ruby.network.msg_count.Response_Data 293280 +system.ruby.network.msg_count.Writeback_Control 293268 +system.ruby.network.msg_byte.Control 2346240 +system.ruby.network.msg_byte.Data 21115296 +system.ruby.network.msg_byte.Response_Data 21116160 +system.ruby.network.msg_byte.Writeback_Control 2346144 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.645195 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers0.throttle1.link_utilization 7.644945 +system.ruby.network.routers0.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers0.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle0.link_utilization 7.644945 +system.ruby.network.routers1.throttle0.msg_count.Control::2 97760 +system.ruby.network.routers1.throttle0.msg_count.Data::2 97756 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 782080 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle1.link_utilization 7.645195 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle0.link_utilization 7.645195 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle1.link_utilization 7.644945 +system.ruby.network.routers2.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers2.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7038432 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 97760 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 97756 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 97756 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 97756 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 69843 +system.ruby.LD.latency_hist_seqr::mean 28.322194 +system.ruby.LD.latency_hist_seqr::gmean 7.510857 +system.ruby.LD.latency_hist_seqr::stdev 36.108227 +system.ruby.LD.latency_hist_seqr | 55897 80.03% 80.03% | 12888 18.45% 98.49% | 741 1.06% 99.55% | 131 0.19% 99.73% | 105 0.15% 99.88% | 76 0.11% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 69843 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 33083 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 33083 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 33083 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 36760 +system.ruby.LD.miss_latency_hist_seqr::mean 52.911425 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.miss_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 36760 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 48546 +system.ruby.ST.latency_hist_seqr::mean 14.735838 +system.ruby.ST.latency_hist_seqr::gmean 3.058930 +system.ruby.ST.latency_hist_seqr::stdev 27.657147 +system.ruby.ST.latency_hist_seqr | 44298 91.25% 91.25% | 3958 8.15% 99.40% | 180 0.37% 99.77% | 35 0.07% 99.85% | 42 0.09% 99.93% | 23 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 10 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 48546 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 33996 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33996 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 33996 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 14550 +system.ruby.ST.miss_latency_hist_seqr::mean 46.829553 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.miss_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.miss_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 14550 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 299354 +system.ruby.IFETCH.latency_hist_seqr::mean 10.964664 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.878483 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.751002 +system.ruby.IFETCH.latency_hist_seqr | 267682 89.42% 89.42% | 29484 9.85% 99.27% | 1510 0.50% 99.77% | 214 0.07% 99.84% | 235 0.08% 99.92% | 210 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 299354 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 252904 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 252904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 252904 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.miss_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 46450 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 97760 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.853989 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.720255 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.989317 +system.ruby.Directory.miss_mach_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 97760 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36760 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.911425 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36760 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 14550 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.829553 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 14550 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46450 +system.ruby.Directory_Controller.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 97756 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 69843 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 299354 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 48546 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 97760 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 36760 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 46450 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 14550 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 33083 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 252904 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 33996 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 83210 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 14550 0.00% 0.00% + +---------- End Simulation Statistics ---------- |