diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing')
5 files changed, 3168 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini new file mode 100644 index 000000000..22d4ff3c2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json new file mode 100644 index 000000000..2675fc23a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + 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"eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout new file mode 100755 index 000000000..44893f204 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34077 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 113397000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt new file mode 100644 index 000000000..7007d9f9a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt @@ -0,0 +1,1020 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 113397000 # Number of ticks simulated +final_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 22733 # Simulator instruction rate (inst/s) +host_op_rate 22733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11398414 # Simulator tick rate (ticks/s) +host_mem_usage 246096 # Number of bytes of host memory used +host_seconds 9.95 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory +system.physmem.bytes_read::total 85120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1330 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1330 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 85120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 174 # Per bank write bursts +system.physmem.perBankRdBursts::1 18 # Per bank write bursts +system.physmem.perBankRdBursts::2 15 # Per bank write bursts +system.physmem.perBankRdBursts::3 82 # Per bank write bursts +system.physmem.perBankRdBursts::4 195 # Per bank write bursts +system.physmem.perBankRdBursts::5 254 # Per bank write bursts +system.physmem.perBankRdBursts::6 22 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 25 # Per bank write bursts +system.physmem.perBankRdBursts::9 103 # Per bank write bursts +system.physmem.perBankRdBursts::10 149 # Per bank write bursts +system.physmem.perBankRdBursts::11 145 # Per bank write bursts +system.physmem.perBankRdBursts::12 50 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 29 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 113291000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1330 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation +system.physmem.totQLat 16749000 # Total ticks spent queuing +system.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.86 # Data bus utilization in percentage +system.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1108 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 85181.20 # Average gap between requests +system.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ) +system.physmem_0.averagePower 587.821160 # Core power per rank (mW) +system.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states +system.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ) +system.physmem_1.averagePower 574.770608 # Core power per rank (mW) +system.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 78040 # Number of BP lookups +system.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups +system.cpu.branchPred.BTBHits 36023 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6672 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8160 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226795 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 336548 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78040 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 60631 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70165 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68795 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 133 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261697 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 261697 # Type of FU issued +system.cpu.iq.rate 1.153892 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6752 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 98174 # number of memory reference insts executed +system.cpu.iew.exec_branches 57098 # Number of branches executed +system.cpu.iew.exec_stores 39775 # Number of stores executed +system.cpu.iew.exec_rate 1.120642 # Inst execution rate +system.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 251000 # cumulative count of insts written-back +system.cpu.iew.wb_producers 95690 # num instructions producing a value +system.cpu.iew.wb_consumers 132115 # num instructions consuming a value +system.cpu.iew.wb_rate 1.106726 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle +system.cpu.commit.committedInsts 226159 # Number of instructions committed +system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 88940 # Number of memory references committed +system.cpu.commit.loads 51711 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 50405 # Number of branches committed +system.cpu.commit.fp_insts 862 # Number of committed floating point instructions. +system.cpu.commit.int_insts 225991 # Number of committed integer instructions. +system.cpu.commit.function_calls 16616 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 226159 # Class of committed instruction +system.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 422850 # The number of ROB reads +system.cpu.rob.rob_writes 556608 # The number of ROB writes +system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 226159 # Number of Instructions Simulated +system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.002812 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads +system.cpu.ipc 0.997196 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 329004 # number of integer regfile reads +system.cpu.int_regfile_writes 174767 # number of integer regfile writes +system.cpu.fp_regfile_reads 880 # number of floating regfile reads +system.cpu.fp_regfile_writes 753 # number of floating regfile writes +system.cpu.misc_regfile_reads 448 # number of misc regfile reads +system.cpu.misc_regfile_writes 313 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179361 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits +system.cpu.dcache.overall_hits::total 87597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses +system.cpu.dcache.overall_misses::total 1933 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # 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number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1029 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1029 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 97 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 97 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1330 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13709000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13709000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74966500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74966500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7641500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7641500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74966500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21350500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96317000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74966500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21350500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96317000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.998498 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.998498 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67200.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67200.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72853.741497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72853.741497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78778.350515 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78778.350515 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1126 # Transaction distribution +system.membus.trans_dist::ReadExReq 204 # Transaction distribution +system.membus.trans_dist::ReadExResp 204 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1330 # Request fanout histogram +system.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |