diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64f')
25 files changed, 12256 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini new file mode 100644 index 000000000..4631a10f3 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json new file mode 100644 index 000000000..0a349ce2a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "do_quiesce": true, + "type": "MinorCPU", + "executeCycleInput": true, + "executeAllowEarlyMemoryIssue": true, + "executeInputBufferSize": 7, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "socket_id": 0, + "progress_interval": 0, + "p_state_clk_gate_min": 1000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": 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"type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": 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"system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": 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+ "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout new file mode 100755 index 000000000..695544b14 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34076 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 270200000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt new file mode 100644 index 000000000..a1e10e23b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt @@ -0,0 +1,765 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000270 # Number of seconds simulated +sim_ticks 270200000 # Number of ticks simulated +final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 24805 # Simulator instruction rate (inst/s) +host_op_rate 24804 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29619482 # Simulator tick rate (ticks/s) +host_mem_usage 244928 # Number of bytes of host memory used +host_seconds 9.12 # Real time elapsed on the host +sim_insts 226275 # Number of instructions simulated +sim_ops 226275 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory +system.physmem.bytes_read::total 86336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1349 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 173 # Per bank write bursts +system.physmem.perBankRdBursts::1 19 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 76 # Per bank write bursts +system.physmem.perBankRdBursts::4 196 # Per bank write bursts +system.physmem.perBankRdBursts::5 259 # Per bank write bursts +system.physmem.perBankRdBursts::6 19 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 26 # Per bank write bursts +system.physmem.perBankRdBursts::9 99 # Per bank write bursts +system.physmem.perBankRdBursts::10 157 # Per bank write bursts +system.physmem.perBankRdBursts::11 158 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts +system.physmem.perBankRdBursts::14 17 # Per bank write bursts +system.physmem.perBankRdBursts::15 33 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 269959000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1349 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation +system.physmem.totQLat 15283750 # Total ticks spent queuing +system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.50 # Data bus utilization in percentage +system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1101 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 200117.87 # Average gap between requests +system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ) +system.physmem_0.averagePower 548.697113 # Core power per rank (mW) +system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states +system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states +system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ) +system.physmem_1.averagePower 540.858753 # Core power per rank (mW) +system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states +system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 61485 # Number of BP lookups +system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups +system.cpu.branchPred.BTBHits 29457 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 540400 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226275 # Number of instructions committed +system.cpu.committedOps 226275 # Number of ops (including micro ops) committed +system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.388244 # CPI: cycles per instruction +system.cpu.ipc 0.418718 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction +system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction +system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction +system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction +system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 11 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 5 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction +system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 226275 # Class of committed instruction +system.cpu.tickCycles 340080 # Number of cycles that the object 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83566.225166 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 69 # number of replacements +system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor 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number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1048 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1048 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1349 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1048 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses +system.cpu.l2cache.overall_misses::total 1349 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles 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+system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 302 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1353 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 302 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1353 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997146 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997146 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.989691 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.989691 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1048 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1048 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 91008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1353 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000739 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.027186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1352 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1353 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 780000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1576500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1144 # Transaction distribution +system.membus.trans_dist::ReadExReq 205 # Transaction distribution +system.membus.trans_dist::ReadExResp 205 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1349 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1349 # Request fanout histogram +system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini new file mode 100644 index 000000000..22d4ff3c2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + 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+pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json new file mode 100644 index 000000000..2675fc23a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": 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"system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout new file mode 100755 index 000000000..44893f204 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34077 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 113397000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt new file mode 100644 index 000000000..7007d9f9a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt @@ -0,0 +1,1020 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 113397000 # Number of ticks simulated +final_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 22733 # Simulator instruction rate (inst/s) +host_op_rate 22733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11398414 # Simulator tick rate (ticks/s) +host_mem_usage 246096 # Number of bytes of host memory used +host_seconds 9.95 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory +system.physmem.bytes_read::total 85120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1330 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1330 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 85120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 174 # Per bank write bursts +system.physmem.perBankRdBursts::1 18 # Per bank write bursts +system.physmem.perBankRdBursts::2 15 # Per bank write bursts +system.physmem.perBankRdBursts::3 82 # Per bank write bursts +system.physmem.perBankRdBursts::4 195 # Per bank write bursts +system.physmem.perBankRdBursts::5 254 # Per bank write bursts +system.physmem.perBankRdBursts::6 22 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 25 # Per bank write bursts +system.physmem.perBankRdBursts::9 103 # Per bank write bursts +system.physmem.perBankRdBursts::10 149 # Per bank write bursts +system.physmem.perBankRdBursts::11 145 # Per bank write bursts +system.physmem.perBankRdBursts::12 50 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 29 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 113291000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # 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+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation +system.physmem.totQLat 16749000 # Total ticks spent queuing +system.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.86 # Data bus utilization in percentage +system.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1108 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 85181.20 # Average gap between requests +system.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ) +system.physmem_0.averagePower 587.821160 # Core power per rank (mW) +system.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states +system.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ) +system.physmem_1.averagePower 574.770608 # Core power per rank (mW) +system.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 78040 # Number of BP lookups +system.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups +system.cpu.branchPred.BTBHits 36023 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6672 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8160 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226795 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 336548 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78040 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 60631 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70165 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68795 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 133 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261697 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 261697 # Type of FU issued +system.cpu.iq.rate 1.153892 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6752 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 98174 # number of memory reference insts executed +system.cpu.iew.exec_branches 57098 # Number of branches executed +system.cpu.iew.exec_stores 39775 # Number of stores executed +system.cpu.iew.exec_rate 1.120642 # Inst execution rate +system.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 251000 # cumulative count of insts written-back +system.cpu.iew.wb_producers 95690 # num instructions producing a value +system.cpu.iew.wb_consumers 132115 # num instructions consuming a value +system.cpu.iew.wb_rate 1.106726 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle +system.cpu.commit.committedInsts 226159 # Number of instructions committed +system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 88940 # Number of memory references committed +system.cpu.commit.loads 51711 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 50405 # Number of branches committed +system.cpu.commit.fp_insts 862 # Number of committed floating point instructions. +system.cpu.commit.int_insts 225991 # Number of committed integer instructions. +system.cpu.commit.function_calls 16616 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 226159 # Class of committed instruction +system.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 422850 # The number of ROB reads +system.cpu.rob.rob_writes 556608 # The number of ROB writes +system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 226159 # Number of Instructions Simulated +system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.002812 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads +system.cpu.ipc 0.997196 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 329004 # number of integer regfile reads +system.cpu.int_regfile_writes 174767 # number of integer regfile writes +system.cpu.fp_regfile_reads 880 # number of floating regfile reads +system.cpu.fp_regfile_writes 753 # number of floating regfile writes +system.cpu.misc_regfile_reads 448 # number of misc regfile reads +system.cpu.misc_regfile_writes 313 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179361 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits +system.cpu.dcache.overall_hits::total 87597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses +system.cpu.dcache.overall_misses::total 1933 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16055500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16055500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24812500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24812500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003362 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003362 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90278.350515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90278.350515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78703.431373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78703.431373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 69 # number of replacements +system.cpu.icache.tags.tagsinuse 535.650396 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59273 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1034 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 57.323985 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 535.650396 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.261548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.261548 # Average percentage of cache occupancy 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miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1126 # Transaction distribution +system.membus.trans_dist::ReadExReq 204 # Transaction distribution +system.membus.trans_dist::ReadExResp 204 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1330 # Request fanout histogram +system.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini new file mode 100644 index 000000000..50ff7280f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json new file mode 100644 index 000000000..ecd3e1c52 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout new file mode 100755 index 000000000..1aedc7412 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:33 +gem5 executing on zizzer, pid 34079 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 113137000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt new file mode 100644 index 000000000..9a7a22440 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 113137000 # Number of ticks simulated +final_tick 113137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 28615 # Simulator instruction rate (inst/s) +host_op_rate 28615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14314809 # Simulator tick rate (ticks/s) +host_mem_usage 234404 # Number of bytes of host memory used +host_seconds 7.90 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 905100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 339455 # Number of bytes read from this memory +system.physmem.bytes_read::total 1244555 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 905100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 905100 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 226262 # Number of bytes written to this memory +system.physmem.bytes_written::total 226262 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 226275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 51711 # Number of read requests responded to by this memory +system.physmem.num_reads::total 277986 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 37229 # Number of write requests responded to by this memory +system.physmem.num_writes::total 37229 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000035355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3000388909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11000424264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000035355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000035355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1999893934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1999893934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000035355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5000282843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13000318198 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 113137000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226275 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 226275 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 277986 # Transaction distribution +system.membus.trans_dist::ReadResp 277986 # Transaction distribution +system.membus.trans_dist::WriteReq 37229 # Transaction distribution +system.membus.trans_dist::WriteResp 37229 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 452550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 177880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630430 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 905100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 565717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1470817 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 315215 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 315215 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 315215 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini new file mode 100644 index 000000000..eb91af64f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 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int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 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system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] 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+type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json new file mode 100644 index 000000000..10ddc0f69 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + 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"max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout new file mode 100755 index 000000000..5fb7ec2e1 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:42 +gem5 executing on zizzer, pid 34083 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 4665394 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..2726406d4 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.004665 # Number of seconds simulated +sim_ticks 4665394 # Number of ticks simulated +final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 17585 # Simulator instruction rate (inst/s) +host_op_rate 17585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 362753 # Simulator tick rate (ticks/s) +host_mem_usage 412420 # Number of bytes of host memory used +host_seconds 12.86 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 4623808 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 4623808 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4623552 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 4623552 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 72247 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 72247 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 72243 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 72243 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 991086283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 991086283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 991031411 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 991031411 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1982117695 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1982117695 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 72247 # Number of read requests accepted +system.mem_ctrls.writeReqs 72243 # Number of write requests accepted +system.mem_ctrls.readBursts 72247 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 72243 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 2375168 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2248640 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2474112 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 4623808 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 4623552 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 35135 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 33568 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 641 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 2702 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5567 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 5413 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 5211 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1018 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 201 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 679 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1777 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 10251 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 39 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 620 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 374 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 689 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 35 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 2847 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 5733 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 5572 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 5809 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1085 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 201 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 742 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 1831 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 10392 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 1454 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1229 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 39 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 626 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 4665243 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 72247 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 72243 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 37112 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 208 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 255 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2030 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2392 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2414 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2512 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2548 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2499 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2385 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2380 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2383 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2380 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 13232 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 366.340992 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 230.810737 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 342.245951 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3082 23.29% 23.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3681 27.82% 51.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1764 13.33% 64.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 976 7.38% 71.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 696 5.26% 77.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 455 3.44% 80.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 307 2.32% 82.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 275 2.08% 84.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1996 15.08% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 13232 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2379 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.599412 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.547106 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.309736 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 94 3.95% 3.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1021 42.92% 46.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1131 47.54% 94.41% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 122 5.13% 99.54% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 10 0.42% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2379 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2379 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.249685 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.232515 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.782399 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2139 89.91% 89.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 18 0.76% 90.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 109 4.58% 95.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 94 3.95% 99.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 19 0.80% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2379 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 719075 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 1424203 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 185560 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.38 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 38.38 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 509.10 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 530.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 991.09 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 991.03 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.98 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.14 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.97 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 27462 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 35070 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.00 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.68 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.29 # Average gap between requests +system.mem_ctrls.pageHitRate 82.51 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 60632880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 32801496 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 239275680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 184946688 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 366325440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 608748144 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8669568 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1381360344 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 69824640 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 28732560 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 2981317440 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 639.028009 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 3307806 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 5774 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 155020 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 96709 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 181835 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1196757 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 3029299 # Time in different power states +system.mem_ctrls_1.actEnergy 33886440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 18326952 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 184691808 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 137924928 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 348500880.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 590211744 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 11048832 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1320078504 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 60484992 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 72883440 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 2778038520 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 595.456358 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 3342297 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 12341 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 147456 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 289875 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 157513 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1163300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 2894909 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 4665394 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 4665394 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 4665394 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 144490 # delay histogram for all message +system.ruby.delayHist | 144490 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 144490 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 315216 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 315216 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 315216 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 315215 +system.ruby.latency_hist_seqr::mean 13.800673 +system.ruby.latency_hist_seqr::gmean 2.449814 +system.ruby.latency_hist_seqr::stdev 29.448647 +system.ruby.latency_hist_seqr | 279385 88.63% 88.63% | 33252 10.55% 99.18% | 1716 0.54% 99.73% | 307 0.10% 99.82% | 278 0.09% 99.91% | 236 0.07% 99.99% | 20 0.01% 99.99% | 8 0.00% 100.00% | 0 0.00% 100.00% | 13 0.00% 100.00% +system.ruby.latency_hist_seqr::total 315215 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 242968 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 242968 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 242968 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 72247 +system.ruby.miss_latency_hist_seqr::mean 56.849572 +system.ruby.miss_latency_hist_seqr::gmean 49.864909 +system.ruby.miss_latency_hist_seqr::stdev 37.140999 +system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 72247 +system.ruby.Directory.incomplete_times_seqr 72246 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 242968 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 72247 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 315215 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.742647 +system.ruby.network.routers0.msg_count.Control::2 72247 +system.ruby.network.routers0.msg_count.Data::2 72243 +system.ruby.network.routers0.msg_count.Response_Data::4 72247 +system.ruby.network.routers0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers0.msg_bytes.Control::2 577976 +system.ruby.network.routers0.msg_bytes.Data::2 5201496 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.742647 +system.ruby.network.routers1.msg_count.Control::2 72247 +system.ruby.network.routers1.msg_count.Data::2 72243 +system.ruby.network.routers1.msg_count.Response_Data::4 72247 +system.ruby.network.routers1.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers1.msg_bytes.Control::2 577976 +system.ruby.network.routers1.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.742647 +system.ruby.network.routers2.msg_count.Control::2 72247 +system.ruby.network.routers2.msg_count.Data::2 72243 +system.ruby.network.routers2.msg_count.Response_Data::4 72247 +system.ruby.network.routers2.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers2.msg_bytes.Control::2 577976 +system.ruby.network.routers2.msg_bytes.Data::2 5201496 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 216741 +system.ruby.network.msg_count.Data 216729 +system.ruby.network.msg_count.Response_Data 216741 +system.ruby.network.msg_count.Writeback_Control 216729 +system.ruby.network.msg_byte.Control 1733928 +system.ruby.network.msg_byte.Data 15604488 +system.ruby.network.msg_byte.Response_Data 15605352 +system.ruby.network.msg_byte.Writeback_Control 1733832 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.742819 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 72247 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers0.throttle1.link_utilization 7.742476 +system.ruby.network.routers0.throttle1.msg_count.Control::2 72247 +system.ruby.network.routers0.throttle1.msg_count.Data::2 72243 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 577976 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.throttle0.link_utilization 7.742476 +system.ruby.network.routers1.throttle0.msg_count.Control::2 72247 +system.ruby.network.routers1.throttle0.msg_count.Data::2 72243 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 577976 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.throttle1.link_utilization 7.742819 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 72247 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.throttle0.link_utilization 7.742819 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 72247 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.throttle1.link_utilization 7.742476 +system.ruby.network.routers2.throttle1.msg_count.Control::2 72247 +system.ruby.network.routers2.throttle1.msg_count.Data::2 72243 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 577976 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5201496 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 72247 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 72247 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 72247 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 72243 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 72243 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 72243 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 51711 +system.ruby.LD.latency_hist_seqr::mean 28.269208 +system.ruby.LD.latency_hist_seqr::gmean 7.619512 +system.ruby.LD.latency_hist_seqr::stdev 36.060908 +system.ruby.LD.latency_hist_seqr | 41177 79.63% 79.63% | 9735 18.83% 98.45% | 541 1.05% 99.50% | 99 0.19% 99.69% | 79 0.15% 99.85% | 70 0.14% 99.98% | 7 0.01% 99.99% | 2 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 51711 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 24257 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 24257 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 24257 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 27454 +system.ruby.LD.miss_latency_hist_seqr::mean 52.362934 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.830488 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.811219 +system.ruby.LD.miss_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 27454 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 37229 +system.ruby.ST.latency_hist_seqr::mean 15.219587 +system.ruby.ST.latency_hist_seqr::gmean 3.175846 +system.ruby.ST.latency_hist_seqr::stdev 28.311515 +system.ruby.ST.latency_hist_seqr | 33814 90.83% 90.83% | 3147 8.45% 99.28% | 181 0.49% 99.77% | 30 0.08% 99.85% | 22 0.06% 99.91% | 24 0.06% 99.97% | 1 0.00% 99.97% | 1 0.00% 99.98% | 0 0.00% 99.98% | 9 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 37229 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 25699 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 25699 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 25699 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 11530 +system.ruby.ST.miss_latency_hist_seqr::mean 46.913356 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.729617 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.659248 +system.ruby.ST.miss_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 11530 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 226275 +system.ruby.IFETCH.latency_hist_seqr::mean 10.260700 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.811203 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.801914 +system.ruby.IFETCH.latency_hist_seqr | 204394 90.33% 90.33% | 20370 9.00% 99.33% | 994 0.44% 99.77% | 178 0.08% 99.85% | 177 0.08% 99.93% | 142 0.06% 99.99% | 12 0.01% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 226275 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 193012 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 193012 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 193012 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 33263 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.996873 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.865504 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.748066 +system.ruby.IFETCH.miss_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 33263 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 72247 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.849572 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.864909 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.140999 +system.ruby.Directory.miss_mach_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 72247 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 27454 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.362934 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.830488 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.811219 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 27454 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 11530 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.913356 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.729617 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.659248 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 11530 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 33263 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.996873 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.865504 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.748066 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 33263 +system.ruby.Directory_Controller.GETX 72247 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 72243 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 72247 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 72243 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 72247 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 72243 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 72247 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 51711 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 226275 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 37229 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 72247 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 27454 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 33263 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 11530 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 24257 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 193012 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 25699 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 60717 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 11530 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini new file mode 100644 index 000000000..47eb7a125 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json new file mode 100644 index 000000000..58b36202f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout new file mode 100755 index 000000000..5080c6704 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:33 +gem5 executing on zizzer, pid 34081 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 385535500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt new file mode 100644 index 000000000..b9ee4135f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt @@ -0,0 +1,521 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000386 # Number of seconds simulated +sim_ticks 385535500 # Number of ticks simulated +final_tick 385535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 27855 # Simulator instruction rate (inst/s) +host_op_rate 27855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47485128 # Simulator tick rate (ticks/s) +host_mem_usage 243704 # Number of bytes of host memory used +host_seconds 8.12 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 53632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18944 # Number of bytes read from this memory +system.physmem.bytes_read::total 72576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 838 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 296 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1134 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 139110406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 49136850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 188247256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 139110406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139110406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 139110406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 49136850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 188247256 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 385535500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 771071 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 771071 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 246.215915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 88644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 299.472973 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 246.215915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.060111 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.060111 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 178176 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 178176 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51622 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51622 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 88644 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 88644 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 88644 # number of overall hits +system.cpu.dcache.overall_hits::total 88644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 296 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 296 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 296 # number of overall misses +system.cpu.dcache.overall_misses::total 296 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5607000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5607000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13041000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13041000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18648000 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.596659 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.596659 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.440917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.440917 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 838 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 838 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1134 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 42319500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 42319500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14948000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 57267500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42319500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14948000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 57267500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998808 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999119 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999119 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.596659 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.596659 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1166 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 928 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 31 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 89 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1709 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2301 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 55680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 74624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1135 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1135 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1135 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 614000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1258500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1134 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 927 # Transaction distribution +system.membus.trans_dist::ReadExReq 207 # Transaction distribution +system.membus.trans_dist::ReadExResp 207 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 927 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2268 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 72576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1134 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1134 # Request fanout histogram +system.membus.reqLayer0.occupancy 1134500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 5670000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |