diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt | 761 |
1 files changed, 0 insertions, 761 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt deleted file mode 100644 index b9db11c0c..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt +++ /dev/null @@ -1,761 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000257 # Number of seconds simulated -sim_ticks 257396500 # Number of ticks simulated -final_tick 257396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23064 # Simulator instruction rate (inst/s) -host_op_rate 23064 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29446323 # Simulator tick rate (ticks/s) -host_mem_usage 244684 # Number of bytes of host memory used -host_seconds 8.74 # Real time elapsed on the host -sim_insts 201609 # Number of instructions simulated -sim_ops 201609 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 70720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18880 # Number of bytes read from this memory -system.physmem.bytes_read::total 89600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 70720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 70720 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 274751211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 73349871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 348101081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 274751211 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 274751211 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 274751211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 73349871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 348101081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1400 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1400 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 89600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 89600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 195 # Per bank write bursts -system.physmem.perBankRdBursts::1 221 # Per bank write bursts -system.physmem.perBankRdBursts::2 35 # Per bank write bursts -system.physmem.perBankRdBursts::3 87 # Per bank write bursts -system.physmem.perBankRdBursts::4 141 # Per bank write bursts -system.physmem.perBankRdBursts::5 86 # Per bank write bursts -system.physmem.perBankRdBursts::6 5 # Per bank write bursts -system.physmem.perBankRdBursts::7 106 # Per bank write bursts -system.physmem.perBankRdBursts::8 78 # Per bank write bursts -system.physmem.perBankRdBursts::9 96 # Per bank write bursts -system.physmem.perBankRdBursts::10 80 # Per bank write bursts -system.physmem.perBankRdBursts::11 128 # Per bank write bursts -system.physmem.perBankRdBursts::12 40 # Per bank write bursts -system.physmem.perBankRdBursts::13 27 # Per bank write bursts -system.physmem.perBankRdBursts::14 51 # Per bank write bursts -system.physmem.perBankRdBursts::15 24 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 257156500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1400 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.270073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.910663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.246990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 71 25.91% 25.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 59 21.53% 47.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52 18.98% 66.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26 9.49% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14 5.11% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 23 8.39% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8 2.92% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.09% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 18 6.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 274 # Bytes accessed per row activation -system.physmem.totQLat 19864500 # Total ticks spent queuing -system.physmem.totMemAccLat 46114500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14188.93 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32938.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 348.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 348.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.72 # Data bus utilization in percentage -system.physmem.busUtilRead 2.72 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1124 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 183683.21 # Average gap between requests -system.physmem.pageHitRate 80.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1299480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 690690 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6254640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14953950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 477120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 94483770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6205440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 144648210 # Total energy per rank (pJ) -system.physmem_0.averagePower 561.964316 # Core power per rank (mW) -system.physmem_0.totalIdleTime 223185500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states -system.physmem_0.memoryStateTime::REF 8580000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16154500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25250500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 207201500 # Time in different power states -system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 349140 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3741360 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14751360.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9433500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3408960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 53834790 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 13144800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18682440 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 118017510 # Total energy per rank (pJ) -system.physmem_1.averagePower 458.502938 # Core power per rank (mW) -system.physmem_1.totalIdleTime 227632750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 6246000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 75541750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 34227000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15120250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 118067250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 58095 # Number of BP lookups -system.cpu.branchPred.condPredicted 37339 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4808 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47628 # Number of BTB lookups -system.cpu.branchPred.BTBHits 25748 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.060637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9498 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5462 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 4036 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2282 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 130 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 257396500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 514793 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 201609 # Number of instructions committed -system.cpu.committedOps 201609 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12686 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.553423 # CPI: cycles per instruction -system.cpu.ipc 0.391631 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 132 0.07% 0.07% # Class of committed instruction -system.cpu.op_class_0::IntAlu 120936 59.99% 60.05% # Class of committed instruction -system.cpu.op_class_0::IntMult 297 0.15% 60.20% # Class of committed instruction -system.cpu.op_class_0::IntDiv 166 0.08% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::MemRead 46389 23.01% 83.29% # Class of committed instruction -system.cpu.op_class_0::MemWrite 33689 16.71% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 201609 # Class of committed instruction -system.cpu.tickCycles 299839 # Number of cycles that the object actually ticked -system.cpu.idleCycles 214954 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 237.251323 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 81600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 275.675676 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 237.251323 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.057923 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.057923 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 164496 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 164496 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 48321 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48321 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 33279 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 33279 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 81600 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 81600 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 81600 # number of overall hits -system.cpu.dcache.overall_hits::total 81600 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32769500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32769500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41612500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41612500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41612500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41612500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82100 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82100 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82100 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82100 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001880 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001880 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012141 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012141 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006090 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006090 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006090 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006090 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 97175.824176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 97175.824176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80121.026895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80121.026895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83225 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83225 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 198 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 198 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 204 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 204 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 85 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 85 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 211 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 211 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25093000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25093000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003605 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003605 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96011.764706 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96011.764706 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80246.445498 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80246.445498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 581.971054 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 86953 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1105 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 78.690498 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 581.971054 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.284166 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.284166 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1061 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.518066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 177221 # Number of tag accesses -system.cpu.icache.tags.data_accesses 177221 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 86953 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 86953 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 86953 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 86953 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 86953 # number of overall hits -system.cpu.icache.overall_hits::total 86953 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1105 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1105 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1105 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1105 # number of overall misses -system.cpu.icache.overall_misses::total 1105 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 95598500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 95598500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 95598500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 95598500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 95598500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 95598500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 88058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 88058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 88058 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 88058 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 88058 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 88058 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.012549 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.012549 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.012549 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.012549 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.012549 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.012549 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 86514.479638 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 86514.479638 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 86514.479638 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 86514.479638 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 44 # number of writebacks -system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1105 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1105 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1105 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1105 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 94493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 94493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 94493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 94493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 94493500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 94493500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.012549 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.012549 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.012549 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85514.479638 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85514.479638 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 828.582477 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 45 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1400 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.032143 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 591.965303 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 236.617175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018065 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.025286 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12960 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12960 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 44 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 44 # number of WritebackClean hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1105 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1105 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 84 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 295 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1400 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1105 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 295 # number of overall misses -system.cpu.l2cache.overall_misses::total 1400 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16615500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16615500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 92835500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 92835500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8021000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8021000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92835500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24636500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 117472000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92835500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24636500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 117472000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 44 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 44 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1105 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1105 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 85 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 85 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1105 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1401 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1105 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1401 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.988235 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.988235 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.996622 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.999286 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.996622 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.999286 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78746.445498 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78746.445498 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84014.027149 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84014.027149 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95488.095238 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 95488.095238 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83908.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83908.571429 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1105 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1105 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 84 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 295 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1400 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 295 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1400 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14505500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14505500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81785500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81785500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7181000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7181000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81785500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21686500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 103472000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81785500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21686500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 103472000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.988235 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.988235 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.999286 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.999286 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68746.445498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68746.445498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74014.027149 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74014.027149 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 85488.095238 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85488.095238 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1445 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2254 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2846 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 92480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1401 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000714 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.026717 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1400 99.93% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1401 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 766500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1657500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1400 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1189 # Transaction distribution -system.membus.trans_dist::ReadExReq 211 # Transaction distribution -system.membus.trans_dist::ReadExResp 211 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2800 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 89600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 89600 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1400 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1400 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1400 # Request fanout histogram -system.membus.reqLayer0.occupancy 1611500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 7433000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |