diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing')
5 files changed, 3256 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.ini new file mode 100644 index 000000000..f5e07ebcd --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.ini @@ -0,0 +1,876 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=cout +pgid=100 +pid=100 +ppid=0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.json new file mode 100644 index 000000000..66b2caf2e --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.json @@ -0,0 +1,1155 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + 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+ "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "wait_for_remote_gdb": false, + "cacheStorePorts": 200, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simerr new file mode 100755 index 000000000..3d532185a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simerr @@ -0,0 +1,6 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Sockets disabled, not accepting gdb connections +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simout new file mode 100755 index 000000000..004fa3a6c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simout @@ -0,0 +1,169 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:25:07 +gem5 executing on boldrock, pid 6002 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/o3-timing + +Global frequency set at 1000000000000 ticks per second +lui: PASS +lui, negative: PASS +auipc: 0x184D6 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2430 + st_ino = 73671954 + st_mode = 33188 + st_nlink = 1 + st_uid = 1001 + st_gid = 1001 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +fstat: + st_dev = 2430 + st_ino = 73671954 + st_mode = 33188 + st_nlink = 1 + st_uid = 1001 + st_gid = 1001 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: [1;31mFAIL[0m (expected 1; found 0) +timeval: + tv_sec = 1000000000 + tv_usec = 194 +gettimeofday: PASS +Cycles: 397395 +rdcycle: PASS +Time: 1499981167 +rdtime: PASS +Instructions Retired: 214447 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 243602000 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/stats.txt new file mode 100644 index 000000000..4796aaa68 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/stats.txt @@ -0,0 +1,1050 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000244 +sim_ticks 243602000 +final_tick 243602000 +sim_freq 1000000000000 +host_inst_rate 3536 +host_op_rate 3546 +host_tick_rate 3225943 +host_mem_usage 272312 +host_seconds 75.51 +sim_insts 266983 +sim_ops 267753 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 243602000 +system.physmem.bytes_read::cpu.inst 72896 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79329.268293 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77854.383814 +system.cpu.toL2Bus.snoop_filter.tot_requests 1739 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 92 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 243602000 +system.cpu.toL2Bus.trans_dist::ReadResp 1429 +system.cpu.toL2Bus.trans_dist::WritebackClean 92 +system.cpu.toL2Bus.trans_dist::ReadExReq 218 +system.cpu.toL2Bus.trans_dist::ReadExResp 218 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1154 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 275 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2400 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 986 +system.cpu.toL2Bus.pkt_count::total 3386 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 79744 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31552 +system.cpu.toL2Bus.pkt_size::total 111296 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1647 +system.cpu.toL2Bus.snoop_fanout::mean 0 +system.cpu.toL2Bus.snoop_fanout::stdev 0 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1647 100.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 0 +system.cpu.toL2Bus.snoop_fanout::total 1647 +system.cpu.toL2Bus.reqLayer0.occupancy 961500 +system.cpu.toL2Bus.reqLayer0.utilization 0.4 +system.cpu.toL2Bus.respLayer0.occupancy 1731000 +system.cpu.toL2Bus.respLayer0.utilization 0.7 +system.cpu.toL2Bus.respLayer1.occupancy 739500 +system.cpu.toL2Bus.respLayer1.utilization 0.3 +system.membus.snoop_filter.tot_requests 1631 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 243602000 +system.membus.trans_dist::ReadResp 1413 +system.membus.trans_dist::ReadExReq 218 +system.membus.trans_dist::ReadExResp 218 +system.membus.trans_dist::ReadSharedReq 1413 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3262 +system.membus.pkt_count::total 3262 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 104384 +system.membus.pkt_size::total 104384 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1631 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1631 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1631 +system.membus.reqLayer0.occupancy 2012500 +system.membus.reqLayer0.utilization 0.8 +system.membus.respLayer1.occupancy 8687000 +system.membus.respLayer1.utilization 3.6 + +---------- End Simulation Statistics ---------- |