1 files changed, 51 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout
new file mode 100755
index 000000000..81d54f27f
--- /dev/null
+++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout
@@ -0,0 +1,51 @@
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simerr
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Nov 30 2016 14:33:35
+gem5 started Nov 30 2016 16:18:53
+gem5 executing on zizzer, pid 34103
+command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby
+
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+mul: PASS
+mul, overflow: PASS
+mulh: PASS
+mulh, negative: PASS
+mulh, all bits set: PASS
+mulhsu, all bits set: PASS
+mulhsu: PASS
+mulhu: PASS
+mulhu, all bits set: PASS
+div: PASS
+div/0: PASS
+div, overflow: PASS
+divu: PASS
+divu/0: PASS
+divu, "overflow": PASS
+rem: PASS
+rem/0: PASS
+rem, overflow: PASS
+remu: PASS
+remu/0: PASS
+remu, "overflow": PASS
+mulw, truncate: PASS
+mulw, overflow: PASS
+divw, truncate: PASS
+divw/0: PASS
+divw, overflow: PASS
+divuw, truncate: PASS
+divuw/0: PASS
+divuw, "overflow": PASS
+divuw, sign extend: PASS
+remw, truncate: PASS
+remw/0: PASS
+remw, overflow: PASS
+remuw, truncate: PASS
+remuw/0: PASS
+remuw, "overflow": PASS
+remuw, sign extend: PASS
+Exiting @ tick 1841805 because target called exit()