diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64m')
25 files changed, 3343 insertions, 3143 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini index 778748b0c..3221bbcbb 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini @@ -116,9 +116,11 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -745,7 +747,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -754,14 +756,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json index c05fef680..38329ca00 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json @@ -297,6 +297,7 @@ "max_loads_all_threads": 0, "executeMemoryIssueLimit": 1, "decodeCycleInput": true, + "syscallRetryLatency": 10000, "max_loads_any_thread": 0, "executeLSQTransfersQueueSize": 2, "p_state_clk_gate_max": 1000000000000, @@ -1058,21 +1059,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1084,6 +1086,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr index 85a6a33ad..4d11ac6e9 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr @@ -1,4 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout index eb07824f2..ef33d6498 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:44 -gem5 executing on zizzer, pid 34094 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:12:00 +gem5 executing on boldrock, pid 2002 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. mul: PASS mul, overflow: PASS mulh: PASS @@ -48,4 +46,4 @@ remuw, truncate: PASS remuw/0: PASS remuw, "overflow": PASS remuw, sign extend: PASS -Exiting @ tick 165091500 because target called exit() +Exiting @ tick 177558500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt index d63bf170c..a35673e04 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt @@ -1,761 +1,789 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000165 # Number of seconds simulated -sim_ticks 165091500 # Number of ticks simulated -final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 261359 # Simulator instruction rate (inst/s) -host_op_rate 261351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380682439 # Simulator tick rate (ticks/s) -host_mem_usage 261856 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host -sim_insts 113337 # Number of instructions simulated -sim_ops 113337 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 49984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory -system.physmem.bytes_read::total 66752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 781 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 262 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1043 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 302765436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 101567918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 404333355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302765436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302765436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302765436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 101567918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 404333355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1043 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1043 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 66752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 66752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 93 # Per bank write bursts -system.physmem.perBankRdBursts::1 5 # Per bank write bursts -system.physmem.perBankRdBursts::2 17 # Per bank write bursts -system.physmem.perBankRdBursts::3 108 # Per bank write bursts -system.physmem.perBankRdBursts::4 59 # Per bank write bursts -system.physmem.perBankRdBursts::5 95 # Per bank write bursts -system.physmem.perBankRdBursts::6 66 # Per bank write bursts -system.physmem.perBankRdBursts::7 26 # Per bank write bursts -system.physmem.perBankRdBursts::8 58 # Per bank write bursts -system.physmem.perBankRdBursts::9 78 # Per bank write bursts -system.physmem.perBankRdBursts::10 82 # Per bank write bursts -system.physmem.perBankRdBursts::11 51 # Per bank write bursts -system.physmem.perBankRdBursts::12 133 # Per bank write bursts -system.physmem.perBankRdBursts::13 67 # Per bank write bursts -system.physmem.perBankRdBursts::14 98 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 164764000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1043 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.956938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.620752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 291.549711 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 58 27.75% 27.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 50 23.92% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39 18.66% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19 9.09% 79.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9 4.31% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 3.83% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation -system.physmem.totQLat 16727250 # Total ticks spent queuing -system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 829 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 157971.24 # Average gap between requests -system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 778260 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 409860 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3348660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ) -system.physmem_0.averagePower 555.750261 # Core power per rank (mW) -system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states -system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states -system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ) -system.physmem_1.averagePower 547.351788 # Core power per rank (mW) -system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states -system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 31695 # Number of BP lookups -system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15330 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 45 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 165091500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 330183 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 113337 # Number of instructions committed -system.cpu.committedOps 113337 # Number of ops (including micro ops) committed -system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.913285 # CPI: cycles per instruction -system.cpu.ipc 0.343255 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction -system.cpu.op_class_0::IntAlu 69651 61.45% 61.49% # Class of committed instruction -system.cpu.op_class_0::IntMult 122 0.11% 61.60% # Class of committed instruction -system.cpu.op_class_0::IntDiv 26 0.02% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.63% # Class of committed instruction -system.cpu.op_class_0::MemRead 23780 20.98% 82.61% # Class of committed instruction -system.cpu.op_class_0::MemWrite 19713 17.39% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 113337 # Class of committed instruction -system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked -system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits -system.cpu.dcache.overall_hits::total 43871 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 453 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses -system.cpu.dcache.overall_misses::total 453 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 186 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 186 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 190 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 198 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 198 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 263 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14 # number of replacements -system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101683 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits -system.cpu.icache.overall_hits::total 49670 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses -system.cpu.icache.overall_misses::total 781 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14 # number of writebacks -system.cpu.icache.writebacks::total 14 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1043 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 556 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 437 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031830 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 9507 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 9507 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 14 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14 # number of WritebackClean hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 198 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 198 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 781 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 781 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 781 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 262 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1043 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 781 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 262 # number of overall misses -system.cpu.l2cache.overall_misses::total 1043 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 781 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 781 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 781 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 263 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1044 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 781 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 263 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1044 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.984615 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.984615 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.996198 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.999042 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 198 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 198 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 781 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 781 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 262 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1043 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 262 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.984615 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.984615 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.999042 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 526 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 67712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1044 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030949 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1044 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 543000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1171500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 394500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1043 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 845 # Transaction distribution -system.membus.trans_dist::ReadExReq 198 # Transaction distribution -system.membus.trans_dist::ReadExResp 198 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 845 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2086 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 66752 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1043 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1043 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1043 # Request fanout histogram -system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +sim_seconds 0.000178 +sim_ticks 177558500 +final_tick 177558500 +sim_freq 1000000000000 +host_inst_rate 5771 +host_op_rate 5782 +host_tick_rate 9526846 +host_mem_usage 272764 +host_seconds 18.64 +sim_insts 107550 +sim_ops 107762 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 177558500 +system.physmem.bytes_read::cpu.inst 60544 +system.physmem.bytes_read::cpu.data 29504 +system.physmem.bytes_read::total 90048 +system.physmem.bytes_inst_read::cpu.inst 60544 +system.physmem.bytes_inst_read::total 60544 +system.physmem.num_reads::cpu.inst 946 +system.physmem.num_reads::cpu.data 461 +system.physmem.num_reads::total 1407 +system.physmem.bw_read::cpu.inst 340980578 +system.physmem.bw_read::cpu.data 166164954 +system.physmem.bw_read::total 507145532 +system.physmem.bw_inst_read::cpu.inst 340980578 +system.physmem.bw_inst_read::total 340980578 +system.physmem.bw_total::cpu.inst 340980578 +system.physmem.bw_total::cpu.data 166164954 +system.physmem.bw_total::total 507145532 +system.physmem.readReqs 1407 +system.physmem.writeReqs 0 +system.physmem.readBursts 1407 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 90048 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 90048 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 165 +system.physmem.perBankRdBursts::1 82 +system.physmem.perBankRdBursts::2 125 +system.physmem.perBankRdBursts::3 86 +system.physmem.perBankRdBursts::4 28 +system.physmem.perBankRdBursts::5 90 +system.physmem.perBankRdBursts::6 29 +system.physmem.perBankRdBursts::7 35 +system.physmem.perBankRdBursts::8 84 +system.physmem.perBankRdBursts::9 137 +system.physmem.perBankRdBursts::10 194 +system.physmem.perBankRdBursts::11 146 +system.physmem.perBankRdBursts::12 52 +system.physmem.perBankRdBursts::13 53 +system.physmem.perBankRdBursts::14 55 +system.physmem.perBankRdBursts::15 46 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 177461500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 1407 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 1197 +system.physmem.rdQLenPdf::1 197 +system.physmem.rdQLenPdf::2 13 +system.physmem.rdQLenPdf::3 0 +system.physmem.rdQLenPdf::4 0 +system.physmem.rdQLenPdf::5 0 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 273 +system.physmem.bytesPerActivate::mean 322.578755 +system.physmem.bytesPerActivate::gmean 213.541597 +system.physmem.bytesPerActivate::stdev 289.786791 +system.physmem.bytesPerActivate::0-127 76 27.84% 27.84% +system.physmem.bytesPerActivate::128-255 60 21.98% 49.82% +system.physmem.bytesPerActivate::256-383 48 17.58% 67.40% +system.physmem.bytesPerActivate::384-511 26 9.52% 76.92% +system.physmem.bytesPerActivate::512-639 16 5.86% 82.78% +system.physmem.bytesPerActivate::640-767 15 5.49% 88.28% +system.physmem.bytesPerActivate::768-895 7 2.56% 90.84% +system.physmem.bytesPerActivate::896-1023 7 2.56% 93.41% +system.physmem.bytesPerActivate::1024-1151 18 6.59% 100.00% +system.physmem.bytesPerActivate::total 273 +system.physmem.totQLat 18087250 +system.physmem.totMemAccLat 44468500 +system.physmem.totBusLat 7035000 +system.physmem.avgQLat 12855.19 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 31605.19 +system.physmem.avgRdBW 507.15 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 507.15 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 3.96 +system.physmem.busUtilRead 3.96 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.13 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 1122 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 79.74 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 126127.58 +system.physmem.pageHitRate 79.74 +system.physmem_0.actEnergy 821100 +system.physmem_0.preEnergy 413655 +system.physmem_0.readEnergy 4569600 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 13522080.000000 +system.physmem_0.actBackEnergy 11049450 +system.physmem_0.preBackEnergy 315840 +system.physmem_0.actPowerDownEnergy 64094790 +system.physmem_0.prePowerDownEnergy 4587360 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 99373875 +system.physmem_0.averagePower 559.667575 +system.physmem_0.totalIdleTime 152474000 +system.physmem_0.memoryStateTime::IDLE 144000 +system.physmem_0.memoryStateTime::REF 5720000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 11945000 +system.physmem_0.memoryStateTime::ACT 19174000 +system.physmem_0.memoryStateTime::ACT_PDN 140575500 +system.physmem_1.actEnergy 1213800 +system.physmem_1.preEnergy 622380 +system.physmem_1.readEnergy 5476380 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 13522080.000000 +system.physmem_1.actBackEnergy 12400350 +system.physmem_1.preBackEnergy 386400 +system.physmem_1.actPowerDownEnergy 59656770 +system.physmem_1.prePowerDownEnergy 7116480 +system.physmem_1.selfRefreshEnergy 0 +system.physmem_1.totalEnergy 100394640 +system.physmem_1.averagePower 565.416461 +system.physmem_1.totalIdleTime 149184750 +system.physmem_1.memoryStateTime::IDLE 398000 +system.physmem_1.memoryStateTime::REF 5720000 +system.physmem_1.memoryStateTime::SREF 0 +system.physmem_1.memoryStateTime::PRE_PDN 18527500 +system.physmem_1.memoryStateTime::ACT 22078000 +system.physmem_1.memoryStateTime::ACT_PDN 130835000 +system.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.branchPred.lookups 32035 +system.cpu.branchPred.condPredicted 21823 +system.cpu.branchPred.condIncorrect 2767 +system.cpu.branchPred.BTBLookups 24464 +system.cpu.branchPred.BTBHits 11324 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 46.288424 +system.cpu.branchPred.usedRAS 0 +system.cpu.branchPred.RASInCorrect 0 +system.cpu.branchPred.indirectLookups 6634 +system.cpu.branchPred.indirectHits 3359 +system.cpu.branchPred.indirectMisses 3275 +system.cpu.branchPredindirectMispredicted 1300 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 45 +system.cpu.pwrStateResidencyTicks::ON 177558500 +system.cpu.numCycles 355117 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 107550 +system.cpu.committedOps 107762 +system.cpu.discardedOps 7803 +system.cpu.numFetchSuspends 0 +system.cpu.cpi 3.301878 +system.cpu.ipc 0.302858 +system.cpu.op_class_0::No_OpClass 49 0.05% 0.05% +system.cpu.op_class_0::IntAlu 65954 61.20% 61.25% +system.cpu.op_class_0::IntMult 124 0.12% 61.36% +system.cpu.op_class_0::IntDiv 30 0.03% 61.39% +system.cpu.op_class_0::FloatAdd 0 0.00% 61.39% +system.cpu.op_class_0::FloatCmp 0 0.00% 61.39% +system.cpu.op_class_0::FloatCvt 0 0.00% 61.39% +system.cpu.op_class_0::FloatMult 0 0.00% 61.39% +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.39% +system.cpu.op_class_0::FloatDiv 0 0.00% 61.39% +system.cpu.op_class_0::FloatMisc 0 0.00% 61.39% +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.39% +system.cpu.op_class_0::SimdAdd 0 0.00% 61.39% +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.39% +system.cpu.op_class_0::SimdAlu 0 0.00% 61.39% +system.cpu.op_class_0::SimdCmp 0 0.00% 61.39% +system.cpu.op_class_0::SimdCvt 0 0.00% 61.39% +system.cpu.op_class_0::SimdMisc 0 0.00% 61.39% +system.cpu.op_class_0::SimdMult 0 0.00% 61.39% +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.39% +system.cpu.op_class_0::SimdShift 0 0.00% 61.39% +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.39% +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.39% +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.39% +system.cpu.op_class_0::MemRead 25266 23.45% 84.84% +system.cpu.op_class_0::MemWrite 16327 15.15% 99.99% +system.cpu.op_class_0::FloatMemRead 0 0.00% 99.99% +system.cpu.op_class_0::FloatMemWrite 12 0.01% 100.00% +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class_0::total 107762 +system.cpu.tickCycles 166468 +system.cpu.idleCycles 188649 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.dcache.tags.replacements 0 +system.cpu.dcache.tags.tagsinuse 305.890276 +system.cpu.dcache.tags.total_refs 42081 +system.cpu.dcache.tags.sampled_refs 462 +system.cpu.dcache.tags.avg_refs 91.084416 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 305.890276 +system.cpu.dcache.tags.occ_percent::cpu.data 0.074680 +system.cpu.dcache.tags.occ_percent::total 0.074680 +system.cpu.dcache.tags.occ_task_id_blocks::1024 462 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 295 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.112793 +system.cpu.dcache.tags.tag_accesses 85888 +system.cpu.dcache.tags.data_accesses 85888 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.dcache.ReadReq_hits::cpu.data 25896 +system.cpu.dcache.ReadReq_hits::total 25896 +system.cpu.dcache.WriteReq_hits::cpu.data 15713 +system.cpu.dcache.WriteReq_hits::total 15713 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 235 +system.cpu.dcache.LoadLockedReq_hits::total 235 +system.cpu.dcache.StoreCondReq_hits::cpu.data 237 +system.cpu.dcache.StoreCondReq_hits::total 237 +system.cpu.dcache.demand_hits::cpu.data 41609 +system.cpu.dcache.demand_hits::total 41609 +system.cpu.dcache.overall_hits::cpu.data 41609 +system.cpu.dcache.overall_hits::total 41609 +system.cpu.dcache.ReadReq_misses::cpu.data 241 +system.cpu.dcache.ReadReq_misses::total 241 +system.cpu.dcache.WriteReq_misses::cpu.data 389 +system.cpu.dcache.WriteReq_misses::total 389 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_misses::total 2 +system.cpu.dcache.demand_misses::cpu.data 630 +system.cpu.dcache.demand_misses::total 630 +system.cpu.dcache.overall_misses::cpu.data 630 +system.cpu.dcache.overall_misses::total 630 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20806000 +system.cpu.dcache.ReadReq_miss_latency::total 20806000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31175000 +system.cpu.dcache.WriteReq_miss_latency::total 31175000 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 239500 +system.cpu.dcache.LoadLockedReq_miss_latency::total 239500 +system.cpu.dcache.demand_miss_latency::cpu.data 51981000 +system.cpu.dcache.demand_miss_latency::total 51981000 +system.cpu.dcache.overall_miss_latency::cpu.data 51981000 +system.cpu.dcache.overall_miss_latency::total 51981000 +system.cpu.dcache.ReadReq_accesses::cpu.data 26137 +system.cpu.dcache.ReadReq_accesses::total 26137 +system.cpu.dcache.WriteReq_accesses::cpu.data 16102 +system.cpu.dcache.WriteReq_accesses::total 16102 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 +system.cpu.dcache.LoadLockedReq_accesses::total 237 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 237 +system.cpu.dcache.StoreCondReq_accesses::total 237 +system.cpu.dcache.demand_accesses::cpu.data 42239 +system.cpu.dcache.demand_accesses::total 42239 +system.cpu.dcache.overall_accesses::cpu.data 42239 +system.cpu.dcache.overall_accesses::total 42239 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009221 +system.cpu.dcache.ReadReq_miss_rate::total 0.009221 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024158 +system.cpu.dcache.WriteReq_miss_rate::total 0.024158 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.008439 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.008439 +system.cpu.dcache.demand_miss_rate::cpu.data 0.014915 +system.cpu.dcache.demand_miss_rate::total 0.014915 +system.cpu.dcache.overall_miss_rate::cpu.data 0.014915 +system.cpu.dcache.overall_miss_rate::total 0.014915 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86331.950207 +system.cpu.dcache.ReadReq_avg_miss_latency::total 86331.950207 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80141.388175 +system.cpu.dcache.WriteReq_avg_miss_latency::total 80141.388175 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 119750 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 119750 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 82509.523810 +system.cpu.dcache.demand_avg_miss_latency::total 82509.523810 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 82509.523810 +system.cpu.dcache.overall_avg_miss_latency::total 82509.523810 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3 +system.cpu.dcache.ReadReq_mshr_hits::total 3 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 167 +system.cpu.dcache.WriteReq_mshr_hits::total 167 +system.cpu.dcache.demand_mshr_hits::cpu.data 170 +system.cpu.dcache.demand_mshr_hits::total 170 +system.cpu.dcache.overall_mshr_hits::cpu.data 170 +system.cpu.dcache.overall_mshr_hits::total 170 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 238 +system.cpu.dcache.ReadReq_mshr_misses::total 238 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222 +system.cpu.dcache.WriteReq_mshr_misses::total 222 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 +system.cpu.dcache.demand_mshr_misses::cpu.data 460 +system.cpu.dcache.demand_mshr_misses::total 460 +system.cpu.dcache.overall_mshr_misses::cpu.data 460 +system.cpu.dcache.overall_mshr_misses::total 460 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20320500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20320500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18425000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18425000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 237500 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 237500 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38745500 +system.cpu.dcache.demand_mshr_miss_latency::total 38745500 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38745500 +system.cpu.dcache.overall_mshr_miss_latency::total 38745500 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.009106 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.009106 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013787 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013787 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.008439 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.008439 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010890 +system.cpu.dcache.demand_mshr_miss_rate::total 0.010890 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.010890 +system.cpu.dcache.overall_mshr_miss_rate::total 0.010890 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85380.252101 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85380.252101 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82995.495495 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82995.495495 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 118750 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 118750 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84229.347826 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84229.347826 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84229.347826 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84229.347826 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.icache.tags.replacements 73 +system.cpu.icache.tags.tagsinuse 512.091780 +system.cpu.icache.tags.total_refs 44422 +system.cpu.icache.tags.sampled_refs 951 +system.cpu.icache.tags.avg_refs 46.710831 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 512.091780 +system.cpu.icache.tags.occ_percent::cpu.inst 0.250045 +system.cpu.icache.tags.occ_percent::total 0.250045 +system.cpu.icache.tags.occ_task_id_blocks::1024 878 +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 +system.cpu.icache.tags.age_task_id_blocks_1024::1 434 +system.cpu.icache.tags.age_task_id_blocks_1024::2 392 +system.cpu.icache.tags.occ_task_id_percent::1024 0.428711 +system.cpu.icache.tags.tag_accesses 91699 +system.cpu.icache.tags.data_accesses 91699 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.icache.ReadReq_hits::cpu.inst 44422 +system.cpu.icache.ReadReq_hits::total 44422 +system.cpu.icache.demand_hits::cpu.inst 44422 +system.cpu.icache.demand_hits::total 44422 +system.cpu.icache.overall_hits::cpu.inst 44422 +system.cpu.icache.overall_hits::total 44422 +system.cpu.icache.ReadReq_misses::cpu.inst 952 +system.cpu.icache.ReadReq_misses::total 952 +system.cpu.icache.demand_misses::cpu.inst 952 +system.cpu.icache.demand_misses::total 952 +system.cpu.icache.overall_misses::cpu.inst 952 +system.cpu.icache.overall_misses::total 952 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 80402500 +system.cpu.icache.ReadReq_miss_latency::total 80402500 +system.cpu.icache.demand_miss_latency::cpu.inst 80402500 +system.cpu.icache.demand_miss_latency::total 80402500 +system.cpu.icache.overall_miss_latency::cpu.inst 80402500 +system.cpu.icache.overall_miss_latency::total 80402500 +system.cpu.icache.ReadReq_accesses::cpu.inst 45374 +system.cpu.icache.ReadReq_accesses::total 45374 +system.cpu.icache.demand_accesses::cpu.inst 45374 +system.cpu.icache.demand_accesses::total 45374 +system.cpu.icache.overall_accesses::cpu.inst 45374 +system.cpu.icache.overall_accesses::total 45374 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.020981 +system.cpu.icache.ReadReq_miss_rate::total 0.020981 +system.cpu.icache.demand_miss_rate::cpu.inst 0.020981 +system.cpu.icache.demand_miss_rate::total 0.020981 +system.cpu.icache.overall_miss_rate::cpu.inst 0.020981 +system.cpu.icache.overall_miss_rate::total 0.020981 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84456.407563 +system.cpu.icache.ReadReq_avg_miss_latency::total 84456.407563 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 84456.407563 +system.cpu.icache.demand_avg_miss_latency::total 84456.407563 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 84456.407563 +system.cpu.icache.overall_avg_miss_latency::total 84456.407563 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 73 +system.cpu.icache.writebacks::total 73 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 952 +system.cpu.icache.ReadReq_mshr_misses::total 952 +system.cpu.icache.demand_mshr_misses::cpu.inst 952 +system.cpu.icache.demand_mshr_misses::total 952 +system.cpu.icache.overall_mshr_misses::cpu.inst 952 +system.cpu.icache.overall_mshr_misses::total 952 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79451500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 79451500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79451500 +system.cpu.icache.demand_mshr_miss_latency::total 79451500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79451500 +system.cpu.icache.overall_mshr_miss_latency::total 79451500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.020981 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.020981 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.020981 +system.cpu.icache.demand_mshr_miss_rate::total 0.020981 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.020981 +system.cpu.icache.overall_mshr_miss_rate::total 0.020981 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83457.457983 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83457.457983 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83457.457983 +system.cpu.icache.demand_avg_mshr_miss_latency::total 83457.457983 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83457.457983 +system.cpu.icache.overall_avg_mshr_miss_latency::total 83457.457983 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 846.547099 +system.cpu.l2cache.tags.total_refs 79 +system.cpu.l2cache.tags.sampled_refs 1407 +system.cpu.l2cache.tags.avg_refs 0.056148 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 540.914017 +system.cpu.l2cache.tags.occ_blocks::cpu.data 305.633082 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016507 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009327 +system.cpu.l2cache.tags.occ_percent::total 0.025835 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1407 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 587 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 755 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.042938 +system.cpu.l2cache.tags.tag_accesses 13303 +system.cpu.l2cache.tags.data_accesses 13303 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.l2cache.WritebackClean_hits::writebacks 73 +system.cpu.l2cache.WritebackClean_hits::total 73 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 +system.cpu.l2cache.ReadCleanReq_hits::total 5 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_hits::total 1 +system.cpu.l2cache.demand_hits::cpu.inst 5 +system.cpu.l2cache.demand_hits::cpu.data 1 +system.cpu.l2cache.demand_hits::total 6 +system.cpu.l2cache.overall_hits::cpu.inst 5 +system.cpu.l2cache.overall_hits::cpu.data 1 +system.cpu.l2cache.overall_hits::total 6 +system.cpu.l2cache.ReadExReq_misses::cpu.data 222 +system.cpu.l2cache.ReadExReq_misses::total 222 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 947 +system.cpu.l2cache.ReadCleanReq_misses::total 947 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 239 +system.cpu.l2cache.ReadSharedReq_misses::total 239 +system.cpu.l2cache.demand_misses::cpu.inst 947 +system.cpu.l2cache.demand_misses::cpu.data 461 +system.cpu.l2cache.demand_misses::total 1408 +system.cpu.l2cache.overall_misses::cpu.inst 947 +system.cpu.l2cache.overall_misses::cpu.data 461 +system.cpu.l2cache.overall_misses::total 1408 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18090000 +system.cpu.l2cache.ReadExReq_miss_latency::total 18090000 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 77972500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 77972500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 20183500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 20183500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 77972500 +system.cpu.l2cache.demand_miss_latency::cpu.data 38273500 +system.cpu.l2cache.demand_miss_latency::total 116246000 +system.cpu.l2cache.overall_miss_latency::cpu.inst 77972500 +system.cpu.l2cache.overall_miss_latency::cpu.data 38273500 +system.cpu.l2cache.overall_miss_latency::total 116246000 +system.cpu.l2cache.WritebackClean_accesses::writebacks 73 +system.cpu.l2cache.WritebackClean_accesses::total 73 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 222 +system.cpu.l2cache.ReadExReq_accesses::total 222 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 952 +system.cpu.l2cache.ReadCleanReq_accesses::total 952 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 240 +system.cpu.l2cache.ReadSharedReq_accesses::total 240 +system.cpu.l2cache.demand_accesses::cpu.inst 952 +system.cpu.l2cache.demand_accesses::cpu.data 462 +system.cpu.l2cache.demand_accesses::total 1414 +system.cpu.l2cache.overall_accesses::cpu.inst 952 +system.cpu.l2cache.overall_accesses::cpu.data 462 +system.cpu.l2cache.overall_accesses::total 1414 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994748 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994748 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.995833 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.995833 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994748 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.997835 +system.cpu.l2cache.demand_miss_rate::total 0.995757 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994748 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.997835 +system.cpu.l2cache.overall_miss_rate::total 0.995757 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81486.486486 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81486.486486 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82336.325238 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82336.325238 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84449.790795 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84449.790795 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82336.325238 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83022.776573 +system.cpu.l2cache.demand_avg_miss_latency::total 82561.079545 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82336.325238 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83022.776573 +system.cpu.l2cache.overall_avg_miss_latency::total 82561.079545 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 222 +system.cpu.l2cache.ReadExReq_mshr_misses::total 222 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 947 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 947 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 239 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 239 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 947 +system.cpu.l2cache.demand_mshr_misses::cpu.data 461 +system.cpu.l2cache.demand_mshr_misses::total 1408 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 947 +system.cpu.l2cache.overall_mshr_misses::cpu.data 461 +system.cpu.l2cache.overall_mshr_misses::total 1408 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15870000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15870000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68512500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68512500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17793500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17793500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68512500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 33663500 +system.cpu.l2cache.demand_mshr_miss_latency::total 102176000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68512500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 33663500 +system.cpu.l2cache.overall_mshr_miss_latency::total 102176000 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994748 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994748 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.995833 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.995833 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994748 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.997835 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995757 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994748 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.997835 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995757 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71486.486486 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71486.486486 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72346.884900 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72346.884900 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74449.790795 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74449.790795 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72346.884900 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73022.776573 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72568.181818 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72346.884900 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73022.776573 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72568.181818 +system.cpu.toL2Bus.snoop_filter.tot_requests 1487 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 177558500 +system.cpu.toL2Bus.trans_dist::ReadResp 1191 +system.cpu.toL2Bus.trans_dist::WritebackClean 73 +system.cpu.toL2Bus.trans_dist::ReadExReq 222 +system.cpu.toL2Bus.trans_dist::ReadExResp 222 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 952 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 240 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1976 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 924 +system.cpu.toL2Bus.pkt_count::total 2900 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65536 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29568 +system.cpu.toL2Bus.pkt_size::total 95104 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1414 +system.cpu.toL2Bus.snoop_fanout::mean 0.000707 +system.cpu.toL2Bus.snoop_fanout::stdev 0.026593 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1413 99.93% 99.93% +system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 1414 +system.cpu.toL2Bus.reqLayer0.occupancy 816500 +system.cpu.toL2Bus.reqLayer0.utilization 0.5 +system.cpu.toL2Bus.respLayer0.occupancy 1426500 +system.cpu.toL2Bus.respLayer0.utilization 0.8 +system.cpu.toL2Bus.respLayer1.occupancy 693000 +system.cpu.toL2Bus.respLayer1.utilization 0.4 +system.membus.snoop_filter.tot_requests 1407 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 177558500 +system.membus.trans_dist::ReadResp 1185 +system.membus.trans_dist::ReadExReq 222 +system.membus.trans_dist::ReadExResp 222 +system.membus.trans_dist::ReadSharedReq 1185 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2814 +system.membus.pkt_count::total 2814 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 90048 +system.membus.pkt_size::total 90048 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1407 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1407 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1407 +system.membus.reqLayer0.occupancy 1632000 +system.membus.reqLayer0.utilization 0.9 +system.membus.respLayer1.occupancy 7488500 +system.membus.respLayer1.utilization 4.2 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini index aba900b27..c417f6ef8 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -111,6 +111,7 @@ numIQEntries=64 numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 +numPhysVecRegs=256 numROBEntries=192 numRobs=1 numThreads=1 @@ -139,9 +140,11 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 +wait_for_remote_gdb=false wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -715,7 +718,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -724,14 +727,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json index c507a1468..4f3fa66f9 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json @@ -311,21 +311,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -350,6 +351,7 @@ "decodeToFetchDelay": 1, "renameWidth": 8, "numThreads": 1, + "syscallRetryLatency": 10000, "squashWidth": 8, "function_trace": false, "backComSize": 5, @@ -968,6 +970,8 @@ "switched_out": false, "smtLSQPolicy": "Partitioned", "fetchBufferSize": 64, + "wait_for_remote_gdb": false, + "cacheStorePorts": 200, "simpoint_start_insts": [], "max_insts_any_thread": 0, "smtROBThreshold": 100, @@ -1077,7 +1081,6 @@ "issueWidth": 8, "LSQCheckLoads": true, "commitToRenameDelay": 1, - "cachePorts": 200, "system": "system", "checker": null, "numPhysFloatRegs": 256, @@ -1085,6 +1088,7 @@ "default_p_state": "UNDEFINED", "type": "DerivO3CPU", "wbWidth": 8, + "numPhysVecRegs": 256, "interrupts": [ { "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr index 85a6a33ad..4d11ac6e9 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr @@ -1,4 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout index 0c05eb2fe..5cd6bd9ea 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:44 -gem5 executing on zizzer, pid 34095 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:11:34 +gem5 executing on boldrock, pid 1866 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. mul: PASS mul, overflow: PASS mulh: PASS @@ -48,4 +46,4 @@ remuw, truncate: PASS remuw/0: PASS remuw, "overflow": PASS remuw, sign extend: PASS -Exiting @ tick 66726000 because target called exit() +Exiting @ tick 124491500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt index eefd14017..f69b5eb21 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt @@ -1,1006 +1,1048 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000067 # Number of seconds simulated -sim_ticks 66743000 # Number of ticks simulated -final_tick 66743000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234636 # Simulator instruction rate (inst/s) -host_op_rate 234630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138224430 # Simulator tick rate (ticks/s) -host_mem_usage 263644 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host -sim_insts 113291 # Number of instructions simulated -sim_ops 113291 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 49408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory -system.physmem.bytes_read::total 66368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 772 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1037 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 740272388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 254109045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 994381433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 740272388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 740272388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 740272388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 254109045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 994381433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1038 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1038 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 66432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 66432 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 89 # Per bank write bursts -system.physmem.perBankRdBursts::1 8 # Per bank write bursts -system.physmem.perBankRdBursts::2 16 # Per bank write bursts -system.physmem.perBankRdBursts::3 108 # Per bank write bursts -system.physmem.perBankRdBursts::4 63 # Per bank write bursts -system.physmem.perBankRdBursts::5 91 # Per bank write bursts -system.physmem.perBankRdBursts::6 61 # Per bank write bursts -system.physmem.perBankRdBursts::7 30 # Per bank write bursts -system.physmem.perBankRdBursts::8 56 # Per bank write bursts -system.physmem.perBankRdBursts::9 76 # Per bank write bursts -system.physmem.perBankRdBursts::10 79 # Per bank write bursts -system.physmem.perBankRdBursts::11 53 # Per bank write bursts -system.physmem.perBankRdBursts::12 133 # Per bank write bursts -system.physmem.perBankRdBursts::13 64 # Per bank write bursts -system.physmem.perBankRdBursts::14 104 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 66724000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1038 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.407960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.437814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 320.986499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 66 32.84% 32.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 49 24.38% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 13.93% 71.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 5.47% 76.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 11 5.47% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 2.99% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.49% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 2.49% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22 10.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 201 # Bytes accessed per row activation -system.physmem.totQLat 13663500 # Total ticks spent queuing -system.physmem.totMemAccLat 33126000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5190000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13163.29 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31913.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 995.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 995.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.78 # Data bus utilization in percentage -system.physmem.busUtilRead 7.78 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 824 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 64281.31 # Average gap between requests -system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 821100 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 406065 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3327240 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6538470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 110400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 22321770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1215840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 39658005 # Total energy per rank (pJ) -system.physmem_0.averagePower 594.183051 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51789750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 53500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2080000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3164000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 12517250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 48928250 # Time in different power states -system.physmem_1.actEnergy 706860 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 356730 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4084080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6307620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 140640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 21247890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 2284320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 40045260 # Total energy per rank (pJ) -system.physmem_1.averagePower 599.985167 # Core power per rank (mW) -system.physmem_1.totalIdleTime 52550750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 144500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2080000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 5948000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 11967750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 46602750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40127 # Number of BP lookups -system.cpu.branchPred.condPredicted 25071 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2677 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 34324 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19560 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 56.986365 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7732 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3910 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3822 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1192 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 45 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 66743000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 133487 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 32821 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 168943 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40127 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23470 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 44129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5494 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22264 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1272 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.102406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.833567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 43897 54.63% 54.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3425 4.26% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6099 7.59% 66.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5421 6.75% 73.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2445 3.04% 76.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6593 8.20% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1925 2.40% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1654 2.06% 88.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8898 11.07% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.300606 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.265614 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33044 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11875 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 32363 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 936 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2139 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 19097 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 639 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 154927 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1938 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2139 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34647 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3538 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31612 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7015 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 148450 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 267 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6512 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 101534 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 195335 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 195335 # Number of integer rename lookups -system.cpu.rename.CommittedMaps 76188 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 25346 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 57 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 57 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3248 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29003 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22614 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 628 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 137191 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 60 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 131006 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 401 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13441 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80357 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.630300 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.012996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 38076 47.38% 47.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10267 12.78% 60.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8067 10.04% 70.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8077 10.05% 80.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5915 7.36% 87.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4760 5.92% 93.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3768 4.69% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1110 1.38% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 317 0.39% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80357 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 179 6.20% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1370 47.45% 53.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1338 46.35% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 45 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 81559 62.26% 62.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27992 21.37% 83.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21251 16.22% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 131006 # Type of FU issued -system.cpu.iq.rate 0.981414 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2887 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022037 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 345657 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 161246 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 125018 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133848 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2541 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5223 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2902 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 101 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2139 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2305 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 218 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 137249 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 965 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29003 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22614 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 58 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 224 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1896 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2394 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 126750 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 27173 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4256 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 47912 # number of memory reference insts executed -system.cpu.iew.exec_branches 29064 # Number of branches executed -system.cpu.iew.exec_stores 20739 # Number of stores executed -system.cpu.iew.exec_rate 0.949531 # Inst execution rate -system.cpu.iew.wb_sent 125653 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 125018 # cumulative count of insts written-back -system.cpu.iew.wb_producers 49237 # num instructions producing a value -system.cpu.iew.wb_consumers 72853 # num instructions consuming a value -system.cpu.iew.wb_rate 0.936556 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675840 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 23968 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 45 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2069 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 75913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.492379 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.297345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42174 55.56% 55.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10790 14.21% 69.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5413 7.13% 76.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4064 5.35% 82.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3292 4.34% 86.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3056 4.03% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2525 3.33% 93.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 907 1.19% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3692 4.86% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 75913 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113291 # Number of instructions committed -system.cpu.commit.committedOps 113291 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 43492 # Number of memory references committed -system.cpu.commit.loads 23780 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 25920 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 113291 # Number of committed integer instructions. -system.cpu.commit.function_calls 8529 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 69651 61.48% 61.48% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 122 0.11% 61.59% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 26 0.02% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 23780 20.99% 82.60% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 19712 17.40% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 113291 # Class of committed instruction -system.cpu.commit.bw_lim_events 3692 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 208895 # The number of ROB reads -system.cpu.rob.rob_writes 279024 # The number of ROB writes -system.cpu.timesIdled 415 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53130 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 113291 # Number of Instructions Simulated -system.cpu.committedOps 113291 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178267 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178267 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848704 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848704 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 166268 # number of integer regfile reads -system.cpu.int_regfile_writes 85929 # number of integer regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 217.985310 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42417 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 265 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 160.064151 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 217.985310 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.053219 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.053219 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.064697 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88517 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88517 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24171 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24171 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18246 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18246 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 42417 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42417 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42417 # number of overall hits -system.cpu.dcache.overall_hits::total 42417 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 243 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 243 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1466 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1466 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1709 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1709 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1709 # number of overall misses -system.cpu.dcache.overall_misses::total 1709 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20232000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20232000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95961940 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95961940 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 116193940 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 116193940 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 116193940 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 116193940 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44126 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44126 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44126 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44126 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009953 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009953 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.074371 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.074371 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038730 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038730 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83259.259259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 83259.259259 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65458.349250 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65458.349250 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67989.432417 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67989.432417 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 63 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.714286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 173 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1269 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1269 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1442 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1442 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1442 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1442 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 197 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22100500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22100500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22100500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22100500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002867 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002867 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009994 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009994 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006051 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006051 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91307.142857 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91307.142857 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79741.116751 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79741.116751 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82773.408240 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82773.408240 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82773.408240 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82773.408240 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16 # number of replacements -system.cpu.icache.tags.tagsinuse 390.093191 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21217 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 773 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27.447607 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 390.093191 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.190475 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.190475 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 757 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.369629 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45285 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45285 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 21217 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21217 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21217 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21217 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21217 # number of overall hits -system.cpu.icache.overall_hits::total 21217 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses -system.cpu.icache.overall_misses::total 1039 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81350998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81350998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81350998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81350998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81350998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81350998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22256 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22256 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22256 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22256 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22256 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22256 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046684 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.046684 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.046684 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.046684 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.046684 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.046684 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78297.399423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78297.399423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78297.399423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78297.399423 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 37 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.783784 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16 # number of writebacks -system.cpu.icache.writebacks::total 16 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 266 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 266 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 266 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 266 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 773 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 773 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 773 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65540000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65540000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.034732 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.034732 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.034732 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84786.545925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84786.545925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84786.545925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84786.545925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84786.545925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84786.545925 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 612.540827 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1037 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.015429 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 394.513827 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 218.027000 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012040 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006654 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.018693 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1037 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 9477 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 9477 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 197 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 197 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 70 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 70 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1039 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses -system.cpu.l2cache.overall_misses::total 1039 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15413500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15413500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 64376500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 64376500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6288000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6288000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 64376500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21701500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 86078000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64376500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21701500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 86078000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 70 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 70 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 772 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 267 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1039 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 772 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 267 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1039 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78241.116751 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78241.116751 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83389.248705 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83389.248705 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89828.571429 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89828.571429 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82846.968239 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82846.968239 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 772 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 772 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 70 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 70 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1039 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1039 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13443500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13443500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 56656500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 56656500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5608000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5608000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56656500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19051500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 75708000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56656500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19051500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 75708000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68241.116751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68241.116751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73389.248705 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73389.248705 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80114.285714 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80114.285714 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1056 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 70 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1561 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2093 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 67392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1040 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000962 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031009 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1039 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1040 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 544000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1159500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 397500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1038 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 840 # Transaction distribution -system.membus.trans_dist::ReadExReq 197 # Transaction distribution -system.membus.trans_dist::ReadExResp 197 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 841 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2075 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2075 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 66368 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1038 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1038 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1038 # Request fanout histogram -system.membus.reqLayer0.occupancy 1251500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 5471250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.2 # Layer utilization (%) +sim_seconds 0.000124 +sim_ticks 124491500 +final_tick 124491500 +sim_freq 1000000000000 +host_inst_rate 5956 +host_op_rate 5968 +host_tick_rate 6896930 +host_mem_usage 272248 +host_seconds 18.05 +sim_insts 107505 +sim_ops 107717 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 124491500 +system.physmem.bytes_read::cpu.inst 55232 +system.physmem.bytes_read::cpu.data 29568 +system.physmem.bytes_read::total 84800 +system.physmem.bytes_inst_read::cpu.inst 55232 +system.physmem.bytes_inst_read::total 55232 +system.physmem.num_reads::cpu.inst 863 +system.physmem.num_reads::cpu.data 462 +system.physmem.num_reads::total 1325 +system.physmem.bw_read::cpu.inst 443660812 +system.physmem.bw_read::cpu.data 237510191 +system.physmem.bw_read::total 681171004 +system.physmem.bw_inst_read::cpu.inst 443660812 +system.physmem.bw_inst_read::total 443660812 +system.physmem.bw_total::cpu.inst 443660812 +system.physmem.bw_total::cpu.data 237510191 +system.physmem.bw_total::total 681171004 +system.physmem.readReqs 1325 +system.physmem.writeReqs 0 +system.physmem.readBursts 1325 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 84800 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 84800 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 160 +system.physmem.perBankRdBursts::1 75 +system.physmem.perBankRdBursts::2 130 +system.physmem.perBankRdBursts::3 69 +system.physmem.perBankRdBursts::4 28 +system.physmem.perBankRdBursts::5 73 +system.physmem.perBankRdBursts::6 30 +system.physmem.perBankRdBursts::7 36 +system.physmem.perBankRdBursts::8 80 +system.physmem.perBankRdBursts::9 128 +system.physmem.perBankRdBursts::10 170 +system.physmem.perBankRdBursts::11 139 +system.physmem.perBankRdBursts::12 54 +system.physmem.perBankRdBursts::13 52 +system.physmem.perBankRdBursts::14 50 +system.physmem.perBankRdBursts::15 51 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 124370500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 1325 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 795 +system.physmem.rdQLenPdf::1 342 +system.physmem.rdQLenPdf::2 133 +system.physmem.rdQLenPdf::3 44 +system.physmem.rdQLenPdf::4 10 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 293 +system.physmem.bytesPerActivate::mean 282.866894 +system.physmem.bytesPerActivate::gmean 183.394708 +system.physmem.bytesPerActivate::stdev 273.006748 +system.physmem.bytesPerActivate::0-127 100 34.13% 34.13% +system.physmem.bytesPerActivate::128-255 66 22.53% 56.66% +system.physmem.bytesPerActivate::256-383 47 16.04% 72.70% +system.physmem.bytesPerActivate::384-511 26 8.87% 81.57% +system.physmem.bytesPerActivate::512-639 11 3.75% 85.32% +system.physmem.bytesPerActivate::640-767 15 5.12% 90.44% +system.physmem.bytesPerActivate::768-895 9 3.07% 93.52% +system.physmem.bytesPerActivate::896-1023 4 1.37% 94.88% +system.physmem.bytesPerActivate::1024-1151 15 5.12% 100.00% +system.physmem.bytesPerActivate::total 293 +system.physmem.totQLat 20133000 +system.physmem.totMemAccLat 44976750 +system.physmem.totBusLat 6625000 +system.physmem.avgQLat 15194.72 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 33944.72 +system.physmem.avgRdBW 681.17 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 681.17 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 5.32 +system.physmem.busUtilRead 5.32 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.54 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 1019 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 76.91 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 93864.53 +system.physmem.pageHitRate 76.91 +system.physmem_0.actEnergy 956760 +system.physmem_0.preEnergy 481965 +system.physmem_0.readEnergy 4291140 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 9219600.000000 +system.physmem_0.actBackEnergy 9317790 +system.physmem_0.preBackEnergy 204960 +system.physmem_0.actPowerDownEnergy 46016100 +system.physmem_0.prePowerDownEnergy 1003200 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 71491515 +system.physmem_0.averagePower 574.263630 +system.physmem_0.totalIdleTime 101911500 +system.physmem_0.memoryStateTime::IDLE 89500 +system.physmem_0.memoryStateTime::REF 3900000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 2612500 +system.physmem_0.memoryStateTime::ACT 16963750 +system.physmem_0.memoryStateTime::ACT_PDN 100925750 +system.physmem_1.actEnergy 1228080 +system.physmem_1.preEnergy 629970 +system.physmem_1.readEnergy 5169360 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 9219600.000000 +system.physmem_1.actBackEnergy 9878670 +system.physmem_1.preBackEnergy 257760 +system.physmem_1.actPowerDownEnergy 41086740 +system.physmem_1.prePowerDownEnergy 4629120 +system.physmem_1.selfRefreshEnergy 0 +system.physmem_1.totalEnergy 72099300 +system.physmem_1.averagePower 579.145732 +system.physmem_1.totalIdleTime 102065000 +system.physmem_1.memoryStateTime::IDLE 260500 +system.physmem_1.memoryStateTime::REF 3900000 +system.physmem_1.memoryStateTime::SREF 0 +system.physmem_1.memoryStateTime::PRE_PDN 12050750 +system.physmem_1.memoryStateTime::ACT 18181250 +system.physmem_1.memoryStateTime::ACT_PDN 90099000 +system.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.branchPred.lookups 34816 +system.cpu.branchPred.condPredicted 24305 +system.cpu.branchPred.condIncorrect 7878 +system.cpu.branchPred.BTBLookups 27691 +system.cpu.branchPred.BTBHits 13759 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 49.687624 +system.cpu.branchPred.usedRAS 0 +system.cpu.branchPred.RASInCorrect 0 +system.cpu.branchPred.indirectLookups 7171 +system.cpu.branchPred.indirectHits 3706 +system.cpu.branchPred.indirectMisses 3465 +system.cpu.branchPredindirectMispredicted 1414 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 45 +system.cpu.pwrStateResidencyTicks::ON 124491500 +system.cpu.numCycles 248984 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 46747 +system.cpu.fetch.Insts 152710 +system.cpu.fetch.Branches 34816 +system.cpu.fetch.predictedBranches 17465 +system.cpu.fetch.Cycles 114549 +system.cpu.fetch.SquashCycles 15876 +system.cpu.fetch.MiscStallCycles 7 +system.cpu.fetch.IcacheWaitRetryStallCycles 92 +system.cpu.fetch.CacheLines 27073 +system.cpu.fetch.IcacheSquashes 1404 +system.cpu.fetch.rateDist::samples 169333 +system.cpu.fetch.rateDist::mean 0.903238 +system.cpu.fetch.rateDist::stdev 0.994367 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 63074 37.25% 37.25% +system.cpu.fetch.rateDist::1 77291 45.64% 82.89% +system.cpu.fetch.rateDist::2 18218 10.76% 93.65% +system.cpu.fetch.rateDist::3 6642 3.92% 97.57% +system.cpu.fetch.rateDist::4 2533 1.50% 99.07% +system.cpu.fetch.rateDist::5 841 0.50% 99.57% +system.cpu.fetch.rateDist::6 409 0.24% 99.81% +system.cpu.fetch.rateDist::7 96 0.06% 99.86% +system.cpu.fetch.rateDist::8 229 0.14% 100.00% +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 8 +system.cpu.fetch.rateDist::total 169333 +system.cpu.fetch.branchRate 0.139832 +system.cpu.fetch.rate 0.613333 +system.cpu.decode.IdleCycles 53035 +system.cpu.decode.BlockedCycles 15088 +system.cpu.decode.RunCycles 95872 +system.cpu.decode.UnblockCycles 411 +system.cpu.decode.SquashCycles 4927 +system.cpu.decode.BranchResolved 13489 +system.cpu.decode.BranchMispred 3125 +system.cpu.decode.DecodedInsts 138749 +system.cpu.decode.SquashedInsts 4432 +system.cpu.rename.SquashCycles 4927 +system.cpu.rename.IdleCycles 59325 +system.cpu.rename.BlockCycles 2075 +system.cpu.rename.serializeStallCycles 7298 +system.cpu.rename.RunCycles 89979 +system.cpu.rename.UnblockCycles 5729 +system.cpu.rename.RenamedInsts 132331 +system.cpu.rename.ROBFullEvents 3 +system.cpu.rename.IQFullEvents 12 +system.cpu.rename.LQFullEvents 2887 +system.cpu.rename.SQFullEvents 2573 +system.cpu.rename.RenamedOperands 88185 +system.cpu.rename.RenameLookups 161560 +system.cpu.rename.int_rename_lookups 161362 +system.cpu.rename.fp_rename_lookups 198 +system.cpu.rename.CommittedMaps 70918 +system.cpu.rename.UndoneMaps 17267 +system.cpu.rename.serializingInsts 307 +system.cpu.rename.tempSerializingInsts 307 +system.cpu.rename.skidInsts 859 +system.cpu.memDep0.insertedLoads 28420 +system.cpu.memDep0.insertedStores 17484 +system.cpu.memDep0.conflictingLoads 175 +system.cpu.memDep0.conflictingStores 17 +system.cpu.iq.iqInstsAdded 121763 +system.cpu.iq.iqNonSpecInstsAdded 551 +system.cpu.iq.iqInstsIssued 119946 +system.cpu.iq.iqSquashedInstsIssued 110 +system.cpu.iq.iqSquashedInstsExamined 14590 +system.cpu.iq.iqSquashedOperandsExamined 6084 +system.cpu.iq.iqSquashedNonSpecRemoved 47 +system.cpu.iq.issued_per_cycle::samples 169333 +system.cpu.iq.issued_per_cycle::mean 0.708344 +system.cpu.iq.issued_per_cycle::stdev 0.867381 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 82784 48.89% 48.89% +system.cpu.iq.issued_per_cycle::1 62057 36.65% 85.54% +system.cpu.iq.issued_per_cycle::2 18132 10.71% 96.24% +system.cpu.iq.issued_per_cycle::3 4720 2.79% 99.03% +system.cpu.iq.issued_per_cycle::4 1062 0.63% 99.66% +system.cpu.iq.issued_per_cycle::5 352 0.21% 99.87% +system.cpu.iq.issued_per_cycle::6 152 0.09% 99.96% +system.cpu.iq.issued_per_cycle::7 47 0.03% 99.98% +system.cpu.iq.issued_per_cycle::8 27 0.02% 100.00% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 8 +system.cpu.iq.issued_per_cycle::total 169333 +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 19 10.33% 10.33% +system.cpu.iq.fu_full::IntMult 0 0.00% 10.33% +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.33% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.33% +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.33% +system.cpu.iq.fu_full::MemRead 60 32.61% 42.93% +system.cpu.iq.fu_full::MemWrite 102 55.43% 98.37% +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.37% +system.cpu.iq.fu_full::FloatMemWrite 3 1.63% 100.00% +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::No_OpClass 49 0.04% 0.04% +system.cpu.iq.FU_type_0::IntAlu 74493 62.11% 62.15% +system.cpu.iq.FU_type_0::IntMult 126 0.11% 62.25% +system.cpu.iq.FU_type_0::IntDiv 31 0.03% 62.28% +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.28% +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.28% +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.28% +system.cpu.iq.FU_type_0::FloatMult 29 0.02% 62.30% +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.30% +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.30% +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.30% +system.cpu.iq.FU_type_0::MemRead 28137 23.46% 85.76% +system.cpu.iq.FU_type_0::MemWrite 17069 14.23% 99.99% +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.99% +system.cpu.iq.FU_type_0::FloatMemWrite 12 0.01% 100.00% +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::total 119946 +system.cpu.iq.rate 0.481742 +system.cpu.iq.fu_busy_cnt 184 +system.cpu.iq.fu_busy_rate 0.001534 +system.cpu.iq.int_inst_queue_reads 409434 +system.cpu.iq.int_inst_queue_writes 136852 +system.cpu.iq.int_inst_queue_wakeup_accesses 114740 +system.cpu.iq.fp_inst_queue_reads 85 +system.cpu.iq.fp_inst_queue_writes 70 +system.cpu.iq.fp_inst_queue_wakeup_accesses 12 +system.cpu.iq.int_alu_accesses 120037 +system.cpu.iq.fp_alu_accesses 44 +system.cpu.iew.lsq.thread0.forwLoads 229 +system.cpu.iew.lsq.thread0.invAddrLoads 0 +system.cpu.iew.lsq.thread0.squashedLoads 3154 +system.cpu.iew.lsq.thread0.ignoredResponses 16 +system.cpu.iew.lsq.thread0.memOrderViolation 16 +system.cpu.iew.lsq.thread0.squashedStores 1145 +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 +system.cpu.iew.lsq.thread0.blockedLoads 0 +system.cpu.iew.lsq.thread0.rescheduledLoads 0 +system.cpu.iew.lsq.thread0.cacheBlocked 151 +system.cpu.iew.iewIdleCycles 0 +system.cpu.iew.iewSquashCycles 4927 +system.cpu.iew.iewBlockCycles 1165 +system.cpu.iew.iewUnblockCycles 735 +system.cpu.iew.iewDispatchedInsts 122308 +system.cpu.iew.iewDispSquashedInsts 5105 +system.cpu.iew.iewDispLoadInsts 28420 +system.cpu.iew.iewDispStoreInsts 17484 +system.cpu.iew.iewDispNonSpecInsts 545 +system.cpu.iew.iewIQFullEvents 4 +system.cpu.iew.iewLSQFullEvents 726 +system.cpu.iew.memOrderViolationEvents 16 +system.cpu.iew.predictedTakenIncorrect 2807 +system.cpu.iew.predictedNotTakenIncorrect 2546 +system.cpu.iew.branchMispredicts 5353 +system.cpu.iew.iewExecutedInsts 115997 +system.cpu.iew.iewExecLoadInsts 27252 +system.cpu.iew.iewExecSquashedInsts 3949 +system.cpu.iew.exec_swp 0 +system.cpu.iew.exec_nop 0 +system.cpu.iew.exec_refs 44098 +system.cpu.iew.exec_branches 25988 +system.cpu.iew.exec_stores 16846 +system.cpu.iew.exec_rate 0.465881 +system.cpu.iew.wb_sent 115060 +system.cpu.iew.wb_count 114752 +system.cpu.iew.wb_producers 37473 +system.cpu.iew.wb_consumers 42148 +system.cpu.iew.wb_rate 0.460881 +system.cpu.iew.wb_fanout 0.889081 +system.cpu.commit.commitSquashedInsts 14590 +system.cpu.commit.commitNonSpecStalls 498 +system.cpu.commit.branchMispredicts 4867 +system.cpu.commit.committed_per_cycle::samples 163751 +system.cpu.commit.committed_per_cycle::mean 0.657810 +system.cpu.commit.committed_per_cycle::stdev 1.217274 +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% +system.cpu.commit.committed_per_cycle::0 104340 63.72% 63.72% +system.cpu.commit.committed_per_cycle::1 37348 22.81% 86.53% +system.cpu.commit.committed_per_cycle::2 8922 5.45% 91.98% +system.cpu.commit.committed_per_cycle::3 7132 4.36% 96.33% +system.cpu.commit.committed_per_cycle::4 3349 2.05% 98.38% +system.cpu.commit.committed_per_cycle::5 785 0.48% 98.85% +system.cpu.commit.committed_per_cycle::6 471 0.29% 99.14% +system.cpu.commit.committed_per_cycle::7 250 0.15% 99.30% +system.cpu.commit.committed_per_cycle::8 1154 0.70% 100.00% +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% +system.cpu.commit.committed_per_cycle::min_value 0 +system.cpu.commit.committed_per_cycle::max_value 8 +system.cpu.commit.committed_per_cycle::total 163751 +system.cpu.commit.committedInsts 107505 +system.cpu.commit.committedOps 107717 +system.cpu.commit.swp_count 0 +system.cpu.commit.refs 41605 +system.cpu.commit.loads 25266 +system.cpu.commit.membars 4 +system.cpu.commit.branches 23849 +system.cpu.commit.vec_insts 0 +system.cpu.commit.fp_insts 12 +system.cpu.commit.int_insts 107132 +system.cpu.commit.function_calls 6215 +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% +system.cpu.commit.op_class_0::IntAlu 65954 61.23% 61.23% +system.cpu.commit.op_class_0::IntMult 124 0.12% 61.35% +system.cpu.commit.op_class_0::IntDiv 30 0.03% 61.38% +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.38% +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.38% +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.38% +system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.38% +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.38% +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.38% +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.38% +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.38% +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.38% +system.cpu.commit.op_class_0::MemRead 25266 23.46% 84.83% +system.cpu.commit.op_class_0::MemWrite 16327 15.16% 99.99% +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.99% +system.cpu.commit.op_class_0::FloatMemWrite 12 0.01% 100.00% +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% +system.cpu.commit.op_class_0::total 107717 +system.cpu.commit.bw_lim_events 1154 +system.cpu.rob.rob_reads 284332 +system.cpu.rob.rob_writes 250205 +system.cpu.timesIdled 635 +system.cpu.idleCycles 79651 +system.cpu.committedInsts 107505 +system.cpu.committedOps 107717 +system.cpu.cpi 2.316023 +system.cpu.cpi_total 2.316023 +system.cpu.ipc 0.431775 +system.cpu.ipc_total 0.431775 +system.cpu.int_regfile_reads 142885 +system.cpu.int_regfile_writes 75846 +system.cpu.fp_regfile_reads 12 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.dcache.tags.replacements 0 +system.cpu.dcache.tags.tagsinuse 323.490826 +system.cpu.dcache.tags.total_refs 41387 +system.cpu.dcache.tags.sampled_refs 464 +system.cpu.dcache.tags.avg_refs 89.196121 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 323.490826 +system.cpu.dcache.tags.occ_percent::cpu.data 0.078977 +system.cpu.dcache.tags.occ_percent::total 0.078977 +system.cpu.dcache.tags.occ_task_id_blocks::1024 464 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 229 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.113281 +system.cpu.dcache.tags.tag_accesses 86644 +system.cpu.dcache.tags.data_accesses 86644 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.dcache.ReadReq_hits::cpu.data 26019 +system.cpu.dcache.ReadReq_hits::total 26019 +system.cpu.dcache.WriteReq_hits::cpu.data 14893 +system.cpu.dcache.WriteReq_hits::total 14893 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 238 +system.cpu.dcache.LoadLockedReq_hits::total 238 +system.cpu.dcache.StoreCondReq_hits::cpu.data 237 +system.cpu.dcache.StoreCondReq_hits::total 237 +system.cpu.dcache.demand_hits::cpu.data 40912 +system.cpu.dcache.demand_hits::total 40912 +system.cpu.dcache.overall_hits::cpu.data 40912 +system.cpu.dcache.overall_hits::total 40912 +system.cpu.dcache.ReadReq_misses::cpu.data 491 +system.cpu.dcache.ReadReq_misses::total 491 +system.cpu.dcache.WriteReq_misses::cpu.data 1209 +system.cpu.dcache.WriteReq_misses::total 1209 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 +system.cpu.dcache.LoadLockedReq_misses::total 3 +system.cpu.dcache.demand_misses::cpu.data 1700 +system.cpu.dcache.demand_misses::total 1700 +system.cpu.dcache.overall_misses::cpu.data 1700 +system.cpu.dcache.overall_misses::total 1700 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37658000 +system.cpu.dcache.ReadReq_miss_latency::total 37658000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 84443464 +system.cpu.dcache.WriteReq_miss_latency::total 84443464 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 273000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 273000 +system.cpu.dcache.demand_miss_latency::cpu.data 122101464 +system.cpu.dcache.demand_miss_latency::total 122101464 +system.cpu.dcache.overall_miss_latency::cpu.data 122101464 +system.cpu.dcache.overall_miss_latency::total 122101464 +system.cpu.dcache.ReadReq_accesses::cpu.data 26510 +system.cpu.dcache.ReadReq_accesses::total 26510 +system.cpu.dcache.WriteReq_accesses::cpu.data 16102 +system.cpu.dcache.WriteReq_accesses::total 16102 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 241 +system.cpu.dcache.LoadLockedReq_accesses::total 241 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 237 +system.cpu.dcache.StoreCondReq_accesses::total 237 +system.cpu.dcache.demand_accesses::cpu.data 42612 +system.cpu.dcache.demand_accesses::total 42612 +system.cpu.dcache.overall_accesses::cpu.data 42612 +system.cpu.dcache.overall_accesses::total 42612 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018521 +system.cpu.dcache.ReadReq_miss_rate::total 0.018521 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.075084 +system.cpu.dcache.WriteReq_miss_rate::total 0.075084 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012448 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012448 +system.cpu.dcache.demand_miss_rate::cpu.data 0.039895 +system.cpu.dcache.demand_miss_rate::total 0.039895 +system.cpu.dcache.overall_miss_rate::cpu.data 0.039895 +system.cpu.dcache.overall_miss_rate::total 0.039895 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76696.537678 +system.cpu.dcache.ReadReq_avg_miss_latency::total 76696.537678 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69845.710505 +system.cpu.dcache.WriteReq_avg_miss_latency::total 69845.710505 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 91000 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 91000 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71824.390588 +system.cpu.dcache.demand_avg_miss_latency::total 71824.390588 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71824.390588 +system.cpu.dcache.overall_avg_miss_latency::total 71824.390588 +system.cpu.dcache.blocked_cycles::no_mshrs 3851 +system.cpu.dcache.blocked_cycles::no_targets 159 +system.cpu.dcache.blocked::no_mshrs 61 +system.cpu.dcache.blocked::no_targets 2 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.131148 +system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 244 +system.cpu.dcache.ReadReq_mshr_hits::total 244 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 994 +system.cpu.dcache.WriteReq_mshr_hits::total 994 +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 +system.cpu.dcache.demand_mshr_hits::cpu.data 1238 +system.cpu.dcache.demand_mshr_hits::total 1238 +system.cpu.dcache.overall_mshr_hits::cpu.data 1238 +system.cpu.dcache.overall_mshr_hits::total 1238 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 247 +system.cpu.dcache.ReadReq_mshr_misses::total 247 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 215 +system.cpu.dcache.WriteReq_mshr_misses::total 215 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 +system.cpu.dcache.demand_mshr_misses::cpu.data 462 +system.cpu.dcache.demand_mshr_misses::total 462 +system.cpu.dcache.overall_mshr_misses::cpu.data 462 +system.cpu.dcache.overall_mshr_misses::total 462 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22176000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22176000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18901498 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18901498 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41077498 +system.cpu.dcache.demand_mshr_miss_latency::total 41077498 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41077498 +system.cpu.dcache.overall_mshr_miss_latency::total 41077498 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.009317 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.009317 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013352 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013352 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.008299 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.008299 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010842 +system.cpu.dcache.demand_mshr_miss_rate::total 0.010842 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.010842 +system.cpu.dcache.overall_mshr_miss_rate::total 0.010842 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89781.376518 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89781.376518 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87913.944186 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87913.944186 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 97000 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 97000 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88912.333333 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88912.333333 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88912.333333 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88912.333333 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.icache.tags.replacements 65 +system.cpu.icache.tags.tagsinuse 494.293412 +system.cpu.icache.tags.total_refs 26025 +system.cpu.icache.tags.sampled_refs 876 +system.cpu.icache.tags.avg_refs 29.708904 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 494.293412 +system.cpu.icache.tags.occ_percent::cpu.inst 0.241354 +system.cpu.icache.tags.occ_percent::total 0.241354 +system.cpu.icache.tags.occ_task_id_blocks::1024 811 +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 +system.cpu.icache.tags.age_task_id_blocks_1024::1 497 +system.cpu.icache.tags.age_task_id_blocks_1024::2 257 +system.cpu.icache.tags.occ_task_id_percent::1024 0.395996 +system.cpu.icache.tags.tag_accesses 55022 +system.cpu.icache.tags.data_accesses 55022 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.icache.ReadReq_hits::cpu.inst 26025 +system.cpu.icache.ReadReq_hits::total 26025 +system.cpu.icache.demand_hits::cpu.inst 26025 +system.cpu.icache.demand_hits::total 26025 +system.cpu.icache.overall_hits::cpu.inst 26025 +system.cpu.icache.overall_hits::total 26025 +system.cpu.icache.ReadReq_misses::cpu.inst 1048 +system.cpu.icache.ReadReq_misses::total 1048 +system.cpu.icache.demand_misses::cpu.inst 1048 +system.cpu.icache.demand_misses::total 1048 +system.cpu.icache.overall_misses::cpu.inst 1048 +system.cpu.icache.overall_misses::total 1048 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84617996 +system.cpu.icache.ReadReq_miss_latency::total 84617996 +system.cpu.icache.demand_miss_latency::cpu.inst 84617996 +system.cpu.icache.demand_miss_latency::total 84617996 +system.cpu.icache.overall_miss_latency::cpu.inst 84617996 +system.cpu.icache.overall_miss_latency::total 84617996 +system.cpu.icache.ReadReq_accesses::cpu.inst 27073 +system.cpu.icache.ReadReq_accesses::total 27073 +system.cpu.icache.demand_accesses::cpu.inst 27073 +system.cpu.icache.demand_accesses::total 27073 +system.cpu.icache.overall_accesses::cpu.inst 27073 +system.cpu.icache.overall_accesses::total 27073 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038710 +system.cpu.icache.ReadReq_miss_rate::total 0.038710 +system.cpu.icache.demand_miss_rate::cpu.inst 0.038710 +system.cpu.icache.demand_miss_rate::total 0.038710 +system.cpu.icache.overall_miss_rate::cpu.inst 0.038710 +system.cpu.icache.overall_miss_rate::total 0.038710 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80742.362595 +system.cpu.icache.ReadReq_avg_miss_latency::total 80742.362595 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80742.362595 +system.cpu.icache.demand_avg_miss_latency::total 80742.362595 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80742.362595 +system.cpu.icache.overall_avg_miss_latency::total 80742.362595 +system.cpu.icache.blocked_cycles::no_mshrs 884 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 14 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.142857 +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 65 +system.cpu.icache.writebacks::total 65 +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 172 +system.cpu.icache.ReadReq_mshr_hits::total 172 +system.cpu.icache.demand_mshr_hits::cpu.inst 172 +system.cpu.icache.demand_mshr_hits::total 172 +system.cpu.icache.overall_mshr_hits::cpu.inst 172 +system.cpu.icache.overall_mshr_hits::total 172 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 876 +system.cpu.icache.ReadReq_mshr_misses::total 876 +system.cpu.icache.demand_mshr_misses::cpu.inst 876 +system.cpu.icache.demand_mshr_misses::total 876 +system.cpu.icache.overall_mshr_misses::cpu.inst 876 +system.cpu.icache.overall_mshr_misses::total 876 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73689997 +system.cpu.icache.ReadReq_mshr_miss_latency::total 73689997 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73689997 +system.cpu.icache.demand_mshr_miss_latency::total 73689997 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73689997 +system.cpu.icache.overall_mshr_miss_latency::total 73689997 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032357 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032357 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032357 +system.cpu.icache.demand_mshr_miss_rate::total 0.032357 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032357 +system.cpu.icache.overall_mshr_miss_rate::total 0.032357 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84121.001142 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84121.001142 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84121.001142 +system.cpu.icache.demand_avg_mshr_miss_latency::total 84121.001142 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84121.001142 +system.cpu.icache.overall_avg_mshr_miss_latency::total 84121.001142 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 840.364635 +system.cpu.l2cache.tags.total_refs 80 +system.cpu.l2cache.tags.sampled_refs 1325 +system.cpu.l2cache.tags.avg_refs 0.060377 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 517.394471 +system.cpu.l2cache.tags.occ_blocks::cpu.data 322.970164 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015790 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009856 +system.cpu.l2cache.tags.occ_percent::total 0.025646 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1325 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 734 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 525 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040436 +system.cpu.l2cache.tags.tag_accesses 12565 +system.cpu.l2cache.tags.data_accesses 12565 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.l2cache.WritebackClean_hits::writebacks 65 +system.cpu.l2cache.WritebackClean_hits::total 65 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13 +system.cpu.l2cache.ReadCleanReq_hits::total 13 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 +system.cpu.l2cache.ReadSharedReq_hits::total 2 +system.cpu.l2cache.demand_hits::cpu.inst 13 +system.cpu.l2cache.demand_hits::cpu.data 2 +system.cpu.l2cache.demand_hits::total 15 +system.cpu.l2cache.overall_hits::cpu.inst 13 +system.cpu.l2cache.overall_hits::cpu.data 2 +system.cpu.l2cache.overall_hits::total 15 +system.cpu.l2cache.ReadExReq_misses::cpu.data 215 +system.cpu.l2cache.ReadExReq_misses::total 215 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 863 +system.cpu.l2cache.ReadCleanReq_misses::total 863 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 247 +system.cpu.l2cache.ReadSharedReq_misses::total 247 +system.cpu.l2cache.demand_misses::cpu.inst 863 +system.cpu.l2cache.demand_misses::cpu.data 462 +system.cpu.l2cache.demand_misses::total 1325 +system.cpu.l2cache.overall_misses::cpu.inst 863 +system.cpu.l2cache.overall_misses::cpu.data 462 +system.cpu.l2cache.overall_misses::total 1325 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18572500 +system.cpu.l2cache.ReadExReq_miss_latency::total 18572500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72229500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 72229500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21968500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21968500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 72229500 +system.cpu.l2cache.demand_miss_latency::cpu.data 40541000 +system.cpu.l2cache.demand_miss_latency::total 112770500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 72229500 +system.cpu.l2cache.overall_miss_latency::cpu.data 40541000 +system.cpu.l2cache.overall_miss_latency::total 112770500 +system.cpu.l2cache.WritebackClean_accesses::writebacks 65 +system.cpu.l2cache.WritebackClean_accesses::total 65 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 215 +system.cpu.l2cache.ReadExReq_accesses::total 215 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 876 +system.cpu.l2cache.ReadCleanReq_accesses::total 876 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 249 +system.cpu.l2cache.ReadSharedReq_accesses::total 249 +system.cpu.l2cache.demand_accesses::cpu.inst 876 +system.cpu.l2cache.demand_accesses::cpu.data 464 +system.cpu.l2cache.demand_accesses::total 1340 +system.cpu.l2cache.overall_accesses::cpu.inst 876 +system.cpu.l2cache.overall_accesses::cpu.data 464 +system.cpu.l2cache.overall_accesses::total 1340 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.985160 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.985160 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.991968 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.991968 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985160 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.995690 +system.cpu.l2cache.demand_miss_rate::total 0.988806 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985160 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.995690 +system.cpu.l2cache.overall_miss_rate::total 0.988806 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86383.720930 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86383.720930 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83695.828505 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83695.828505 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88941.295547 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88941.295547 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83695.828505 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87751.082251 +system.cpu.l2cache.demand_avg_miss_latency::total 85109.811321 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83695.828505 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87751.082251 +system.cpu.l2cache.overall_avg_miss_latency::total 85109.811321 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 215 +system.cpu.l2cache.ReadExReq_mshr_misses::total 215 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 863 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 863 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 247 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 247 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 863 +system.cpu.l2cache.demand_mshr_misses::cpu.data 462 +system.cpu.l2cache.demand_mshr_misses::total 1325 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 863 +system.cpu.l2cache.overall_mshr_misses::cpu.data 462 +system.cpu.l2cache.overall_mshr_misses::total 1325 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16422500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16422500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 63599500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 63599500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19498500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19498500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 63599500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 35921000 +system.cpu.l2cache.demand_mshr_miss_latency::total 99520500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 63599500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 35921000 +system.cpu.l2cache.overall_mshr_miss_latency::total 99520500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.985160 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.985160 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.991968 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.991968 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985160 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.995690 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.988806 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985160 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.995690 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.988806 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76383.720930 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76383.720930 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73695.828505 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73695.828505 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78941.295547 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78941.295547 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73695.828505 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77751.082251 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75109.811321 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73695.828505 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77751.082251 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75109.811321 +system.cpu.toL2Bus.snoop_filter.tot_requests 1405 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124491500 +system.cpu.toL2Bus.trans_dist::ReadResp 1125 +system.cpu.toL2Bus.trans_dist::WritebackClean 65 +system.cpu.toL2Bus.trans_dist::ReadExReq 215 +system.cpu.toL2Bus.trans_dist::ReadExResp 215 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 876 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 249 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1817 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 928 +system.cpu.toL2Bus.pkt_count::total 2745 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60224 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29696 +system.cpu.toL2Bus.pkt_size::total 89920 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1340 +system.cpu.toL2Bus.snoop_fanout::mean 0.003731 +system.cpu.toL2Bus.snoop_fanout::stdev 0.060993 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1335 99.63% 99.63% +system.cpu.toL2Bus.snoop_fanout::1 5 0.37% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 1340 +system.cpu.toL2Bus.reqLayer0.occupancy 767500 +system.cpu.toL2Bus.reqLayer0.utilization 0.6 +system.cpu.toL2Bus.respLayer0.occupancy 1314000 +system.cpu.toL2Bus.respLayer0.utilization 1.1 +system.cpu.toL2Bus.respLayer1.occupancy 696000 +system.cpu.toL2Bus.respLayer1.utilization 0.6 +system.membus.snoop_filter.tot_requests 1325 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 124491500 +system.membus.trans_dist::ReadResp 1110 +system.membus.trans_dist::ReadExReq 215 +system.membus.trans_dist::ReadExResp 215 +system.membus.trans_dist::ReadSharedReq 1110 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2650 +system.membus.pkt_count::total 2650 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 84800 +system.membus.pkt_size::total 84800 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1325 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1325 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1325 +system.membus.reqLayer0.occupancy 1620500 +system.membus.reqLayer0.utilization 1.3 +system.membus.respLayer1.occupancy 7036000 +system.membus.respLayer1.utilization 5.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini index 9b465ed9b..df52aac68 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini @@ -88,8 +88,10 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false width=1 workload=system.cpu.workload dcache_port=system.membus.slave[2] @@ -118,7 +120,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -127,14 +129,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json index 56400a045..7ec8d72f4 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json @@ -192,6 +192,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -216,21 +217,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -242,6 +244,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr index fd133b12b..a01f2057a 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout index 100328c9d..0ed1a6e51 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:49 -gem5 executing on zizzer, pid 34098 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:10:51 +gem5 executing on boldrock, pid 1656 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. mul: PASS mul, overflow: PASS mulh: PASS @@ -48,4 +46,4 @@ remuw, truncate: PASS remuw/0: PASS remuw, "overflow": PASS remuw, sign extend: PASS -Exiting @ tick 56668000 because target called exit() +Exiting @ tick 67349000 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt index a11ee5e48..2e57ed034 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt @@ -1,153 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000057 # Number of seconds simulated -sim_ticks 56668000 # Number of ticks simulated -final_tick 56668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42634 # Simulator instruction rate (inst/s) -host_op_rate 42633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21324951 # Simulator tick rate (ticks/s) -host_mem_usage 233724 # Number of bytes of host memory used -host_seconds 2.66 # Real time elapsed on the host -sim_insts 113291 # Number of instructions simulated -sim_ops 113291 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 453348 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156046 # Number of bytes read from this memory -system.physmem.bytes_read::total 609394 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 453348 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 453348 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 110317 # Number of bytes written to this memory -system.physmem.bytes_written::total 110317 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 113337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 23780 # Number of read requests responded to by this memory -system.physmem.num_reads::total 137117 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 19712 # Number of write requests responded to by this memory -system.physmem.num_writes::total 19712 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8000070587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2753688149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10753758735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8000070587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8000070587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1946724783 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1946724783 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8000070587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4700412931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12700483518 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 45 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 56668000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 113337 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 113291 # Number of instructions committed -system.cpu.committedOps 113291 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 8529 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls -system.cpu.num_int_insts 113292 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 151096 # number of times the integer registers were read -system.cpu.num_int_register_writes 76188 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 43493 # number of memory refs -system.cpu.num_load_insts 23780 # Number of load instructions -system.cpu.num_store_insts 19713 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 113337 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 25920 # Number of branches fetched -system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction -system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction -system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction -system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 113337 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 137117 # Transaction distribution -system.membus.trans_dist::ReadResp 137117 # Transaction distribution -system.membus.trans_dist::WriteReq 19712 # Transaction distribution -system.membus.trans_dist::WriteResp 19712 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 226674 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 86984 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 313658 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 453348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 266363 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 719711 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 156829 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 156829 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 156829 # Request fanout histogram +sim_seconds 0.000067 +sim_ticks 67349000 +final_tick 67349000 +sim_freq 1000000000000 +host_inst_rate 5719 +host_op_rate 5730 +host_tick_rate 3582584 +host_mem_usage 259188 +host_seconds 18.80 +sim_insts 107505 +sim_ops 107717 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 67349000 +system.physmem.bytes_read::cpu.inst 537948 +system.physmem.bytes_read::cpu.data 170929 +system.physmem.bytes_read::total 708877 +system.physmem.bytes_inst_read::cpu.inst 537948 +system.physmem.bytes_inst_read::total 537948 +system.physmem.bytes_written::cpu.data 109969 +system.physmem.bytes_written::total 109969 +system.physmem.num_reads::cpu.inst 134487 +system.physmem.num_reads::cpu.data 25266 +system.physmem.num_reads::total 159753 +system.physmem.num_writes::cpu.data 16339 +system.physmem.num_writes::total 16339 +system.physmem.bw_read::cpu.inst 7987468262 +system.physmem.bw_read::cpu.data 2537958990 +system.physmem.bw_read::total 10525427252 +system.physmem.bw_inst_read::cpu.inst 7987468262 +system.physmem.bw_inst_read::total 7987468262 +system.physmem.bw_write::cpu.data 1632823056 +system.physmem.bw_write::total 1632823056 +system.physmem.bw_total::cpu.inst 7987468262 +system.physmem.bw_total::cpu.data 4170782046 +system.physmem.bw_total::total 12158250308 +system.pwrStateResidencyTicks::UNDEFINED 67349000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 45 +system.cpu.pwrStateResidencyTicks::ON 67349000 +system.cpu.numCycles 134699 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 107505 +system.cpu.committedOps 107717 +system.cpu.num_int_alu_accesses 107132 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 6215 +system.cpu.num_conditional_control_insts 17634 +system.cpu.num_int_insts 107132 +system.cpu.num_fp_insts 12 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 134283 +system.cpu.num_int_register_writes 70918 +system.cpu.num_fp_register_reads 12 +system.cpu.num_fp_register_writes 0 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 41605 +system.cpu.num_load_insts 25266 +system.cpu.num_store_insts 16339 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 134699 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 23849 +system.cpu.op_class::No_OpClass 49 0.05% 0.05% +system.cpu.op_class::IntAlu 65954 61.20% 61.25% +system.cpu.op_class::IntMult 124 0.12% 61.36% +system.cpu.op_class::IntDiv 30 0.03% 61.39% +system.cpu.op_class::FloatAdd 0 0.00% 61.39% +system.cpu.op_class::FloatCmp 0 0.00% 61.39% +system.cpu.op_class::FloatCvt 0 0.00% 61.39% +system.cpu.op_class::FloatMult 0 0.00% 61.39% +system.cpu.op_class::FloatMultAcc 0 0.00% 61.39% +system.cpu.op_class::FloatDiv 0 0.00% 61.39% +system.cpu.op_class::FloatMisc 0 0.00% 61.39% +system.cpu.op_class::FloatSqrt 0 0.00% 61.39% +system.cpu.op_class::SimdAdd 0 0.00% 61.39% +system.cpu.op_class::SimdAddAcc 0 0.00% 61.39% +system.cpu.op_class::SimdAlu 0 0.00% 61.39% +system.cpu.op_class::SimdCmp 0 0.00% 61.39% +system.cpu.op_class::SimdCvt 0 0.00% 61.39% +system.cpu.op_class::SimdMisc 0 0.00% 61.39% +system.cpu.op_class::SimdMult 0 0.00% 61.39% +system.cpu.op_class::SimdMultAcc 0 0.00% 61.39% +system.cpu.op_class::SimdShift 0 0.00% 61.39% +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.39% +system.cpu.op_class::SimdSqrt 0 0.00% 61.39% +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.39% +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.39% +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.39% +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.39% +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.39% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.39% +system.cpu.op_class::MemRead 25266 23.45% 84.84% +system.cpu.op_class::MemWrite 16327 15.15% 99.99% +system.cpu.op_class::FloatMemRead 0 0.00% 99.99% +system.cpu.op_class::FloatMemWrite 12 0.01% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 107762 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 67349000 +system.membus.trans_dist::ReadReq 159516 +system.membus.trans_dist::ReadResp 159753 +system.membus.trans_dist::WriteReq 16102 +system.membus.trans_dist::WriteResp 16102 +system.membus.trans_dist::LoadLockedReq 237 +system.membus.trans_dist::StoreCondReq 237 +system.membus.trans_dist::StoreCondResp 237 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 268974 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 83210 +system.membus.pkt_count::total 352184 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 537948 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 280898 +system.membus.pkt_size::total 818846 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 176092 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 176092 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 176092 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini index 2d0e2ebad..7da82d9bc 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -122,7 +124,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -131,14 +133,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -266,6 +269,7 @@ voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] type=Directory_Controller children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +addr_ranges=0:268435455:5:0:0:0 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 @@ -288,16 +292,14 @@ responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory ruby_system=system.ruby system=system to_memory_controller_latency=1 -transitions_per_cycle=4 +transitions_per_cycle=32 version=0 memory=system.mem_ctrls.port [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +addr_ranges=0:268435455:5:0:0:0 eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] type=MessageBuffer @@ -349,6 +351,7 @@ randomization=false [system.ruby.l1_cntrl0] type=L1Cache_Controller children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +addr_ranges=0:18446744073709551615:0:0:0:0 buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json index 491401e32..d5b17fa87 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json @@ -115,7 +115,6 @@ "path": "system.ruby.l1_cntrl0.requestFromCache", "type": "MessageBuffer" }, - "cxx_class": "L1Cache_Controller", "forwardToCache": { "ordered": true, "name": "forwardToCache", @@ -168,8 +167,9 @@ "support_data_reqs": true, "is_cpu_sequencer": true }, - "type": "L1Cache_Controller", + "cxx_class": "L1Cache_Controller", "issue_latency": 2, + "type": "L1Cache_Controller", "recycle_latency": 10, "clk_domain": "system.cpu.clk_domain", "version": 0, @@ -241,6 +241,9 @@ }, "ruby_system": "system.ruby", "name": "l1_cntrl0", + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], "p_state_clk_gate_bins": 20, "mandatoryQueue": { "ordered": false, @@ -1447,12 +1450,15 @@ "path": "system.ruby.dir_cntrl0.responseFromDir", "type": "MessageBuffer" }, - "transitions_per_cycle": 4, + "transitions_per_cycle": 32, "memory": { "peer": "system.mem_ctrls.port", "role": "MASTER" }, "power_model": null, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "buffer_size": 0, "ruby_system": "system.ruby", "requestToDir": { @@ -1487,13 +1493,13 @@ "p_state_clk_gate_bins": 20, "directory": { "name": "directory", - "version": 0, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "eventq_index": 0, "cxx_class": "DirectoryMemory", "path": "system.ruby.dir_cntrl0.directory", - "type": "RubyDirectoryMemory", - "numa_high_bit": 5, - "size": 268435456 + "type": "RubyDirectoryMemory" }, "path": "system.ruby.dir_cntrl0" } @@ -1548,6 +1554,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -1572,21 +1579,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1598,6 +1606,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr index 63b14556f..015dd4d22 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr @@ -4,8 +4,12 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout index 81d54f27f..4a16a862f 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:53 -gem5 executing on zizzer, pid 34103 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:09:50 +gem5 executing on boldrock, pid 1343 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. mul: PASS mul, overflow: PASS mulh: PASS @@ -48,4 +46,4 @@ remuw, truncate: PASS remuw/0: PASS remuw, "overflow": PASS remuw, sign extend: PASS -Exiting @ tick 1841805 because target called exit() +Exiting @ tick 1858825 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt index a9142c5dc..62882b0a2 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt @@ -1,617 +1,658 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.001842 # Number of seconds simulated -sim_ticks 1841805 # Number of ticks simulated -final_tick 1841805 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 106701 # Simulator instruction rate (inst/s) -host_op_rate 106700 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1734637 # Simulator tick rate (ticks/s) -host_mem_usage 428500 # Number of bytes of host memory used -host_seconds 1.06 # Real time elapsed on the host -sim_insts 113291 # Number of instructions simulated -sim_ops 113291 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 1901888 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 1901888 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 1901632 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 1901632 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 29717 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 29717 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 29713 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 29713 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032621803 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1032621803 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032482809 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1032482809 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2065104612 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2065104612 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 29717 # Number of read requests accepted -system.mem_ctrls.writeReqs 29713 # Number of write requests accepted -system.mem_ctrls.readBursts 29717 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 29713 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 810816 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 1091072 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 842496 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 1901888 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 1901632 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 17048 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 16517 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 1366 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 241 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 400 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 244 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 371 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 334 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 67 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 341 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 2380 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 1301 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 1236 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 1592 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 483 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 2223 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 87 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 1405 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 241 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 412 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 257 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 383 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 346 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 69 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 351 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 2448 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 1316 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 1275 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 1634 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 505 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 2424 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 95 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 1841733 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 29717 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 29713 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 12669 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 104 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 124 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 715 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 812 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 810 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 826 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 868 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 857 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 811 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 807 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 805 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 4235 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 390.135537 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 255.090286 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 338.320461 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 828 19.55% 19.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 1136 26.82% 46.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 580 13.70% 60.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 361 8.52% 68.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 278 6.56% 75.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 169 3.99% 79.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 146 3.45% 82.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 150 3.54% 86.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 587 13.86% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 4235 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 805 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.719255 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.645655 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 1.595450 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 50 6.21% 6.21% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 309 38.39% 44.60% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 373 46.34% 90.93% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 65 8.07% 99.01% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 7 0.87% 99.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 0.12% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 805 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 805 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.352795 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.329834 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.903150 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 691 85.84% 85.84% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 4 0.50% 86.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 56 6.96% 93.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 48 5.96% 99.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 6 0.75% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 805 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 239535 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 480246 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 63345 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 18.91 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 37.91 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 440.23 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 457.43 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1032.62 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1032.48 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.01 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.44 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.57 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 9468 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 12124 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 74.73 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.88 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 30.99 # Average gap between requests -system.mem_ctrls.pageHitRate 83.48 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 10074540 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 5448240 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 34569024 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 26024832 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 127230480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 197709288 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3259392 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 446690304 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 61497984 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 65163360 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 977667444 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 530.820279 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 1399707 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 2653 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 53850 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 260009 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 160151 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 385558 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 979584 # Time in different power states -system.mem_ctrls_1.actEnergy 20206200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 10915800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 110161632 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 83920896 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 145055040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 217978032 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3880704 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 529686864 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 51989376 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 18024480 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 1191819024 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 647.092946 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 1353468 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 3236 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 61408 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 56694 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 135389 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 423484 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 1161594 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 45 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1841805 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1841805 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 113291 # Number of instructions committed -system.cpu.committedOps 113291 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 8529 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls -system.cpu.num_int_insts 113292 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 151096 # number of times the integer registers were read -system.cpu.num_int_register_writes 76188 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 43493 # number of memory refs -system.cpu.num_load_insts 23780 # Number of load instructions -system.cpu.num_store_insts 19713 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1841805 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 25920 # Number of branches fetched -system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction -system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction -system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction -system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 113337 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 59430 # delay histogram for all message -system.ruby.delayHist | 59430 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 59430 # delay histogram for all message +sim_seconds 0.001859 +sim_ticks 1858825 +final_tick 1858825 +sim_freq 1000000000 +host_inst_rate 3630 +host_op_rate 3637 +host_tick_rate 62766 +host_mem_usage 438644 +host_seconds 29.62 +sim_insts 107505 +sim_ops 107717 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1858825 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 1845568 +system.mem_ctrls.bytes_read::total 1845568 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 1845312 +system.mem_ctrls.bytes_written::total 1845312 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 28837 +system.mem_ctrls.num_reads::total 28837 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 28833 +system.mem_ctrls.num_writes::total 28833 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 992868075 +system.mem_ctrls.bw_read::total 992868075 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 992730354 +system.mem_ctrls.bw_write::total 992730354 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1985598429 +system.mem_ctrls.bw_total::total 1985598429 +system.mem_ctrls.readReqs 28837 +system.mem_ctrls.writeReqs 28833 +system.mem_ctrls.readBursts 28837 +system.mem_ctrls.writeBursts 28833 +system.mem_ctrls.bytesReadDRAM 808512 +system.mem_ctrls.bytesReadWrQ 1037056 +system.mem_ctrls.bytesWritten 850432 +system.mem_ctrls.bytesReadSys 1845568 +system.mem_ctrls.bytesWrittenSys 1845312 +system.mem_ctrls.servicedByWrQ 16204 +system.mem_ctrls.mergedWrBursts 15513 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 791 +system.mem_ctrls.perBankRdBursts::1 377 +system.mem_ctrls.perBankRdBursts::2 801 +system.mem_ctrls.perBankRdBursts::3 1138 +system.mem_ctrls.perBankRdBursts::4 39 +system.mem_ctrls.perBankRdBursts::5 156 +system.mem_ctrls.perBankRdBursts::6 208 +system.mem_ctrls.perBankRdBursts::7 294 +system.mem_ctrls.perBankRdBursts::8 412 +system.mem_ctrls.perBankRdBursts::9 1571 +system.mem_ctrls.perBankRdBursts::10 1498 +system.mem_ctrls.perBankRdBursts::11 1206 +system.mem_ctrls.perBankRdBursts::12 1065 +system.mem_ctrls.perBankRdBursts::13 1722 +system.mem_ctrls.perBankRdBursts::14 1209 +system.mem_ctrls.perBankRdBursts::15 146 +system.mem_ctrls.perBankWrBursts::0 801 +system.mem_ctrls.perBankWrBursts::1 405 +system.mem_ctrls.perBankWrBursts::2 818 +system.mem_ctrls.perBankWrBursts::3 1199 +system.mem_ctrls.perBankWrBursts::4 42 +system.mem_ctrls.perBankWrBursts::5 164 +system.mem_ctrls.perBankWrBursts::6 209 +system.mem_ctrls.perBankWrBursts::7 297 +system.mem_ctrls.perBankWrBursts::8 429 +system.mem_ctrls.perBankWrBursts::9 1685 +system.mem_ctrls.perBankWrBursts::10 1512 +system.mem_ctrls.perBankWrBursts::11 1252 +system.mem_ctrls.perBankWrBursts::12 1123 +system.mem_ctrls.perBankWrBursts::13 1957 +system.mem_ctrls.perBankWrBursts::14 1253 +system.mem_ctrls.perBankWrBursts::15 142 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 1858745 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 28837 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 28833 +system.mem_ctrls.rdQLenPdf::0 12633 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 114 +system.mem_ctrls.wrQLenPdf::16 139 +system.mem_ctrls.wrQLenPdf::17 689 +system.mem_ctrls.wrQLenPdf::18 826 +system.mem_ctrls.wrQLenPdf::19 837 +system.mem_ctrls.wrQLenPdf::20 860 +system.mem_ctrls.wrQLenPdf::21 876 +system.mem_ctrls.wrQLenPdf::22 854 +system.mem_ctrls.wrQLenPdf::23 811 +system.mem_ctrls.wrQLenPdf::24 811 +system.mem_ctrls.wrQLenPdf::25 812 +system.mem_ctrls.wrQLenPdf::26 811 +system.mem_ctrls.wrQLenPdf::27 811 +system.mem_ctrls.wrQLenPdf::28 811 +system.mem_ctrls.wrQLenPdf::29 811 +system.mem_ctrls.wrQLenPdf::30 811 +system.mem_ctrls.wrQLenPdf::31 811 +system.mem_ctrls.wrQLenPdf::32 810 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 5236 +system.mem_ctrls.bytesPerActivate::mean 316.516425 +system.mem_ctrls.bytesPerActivate::gmean 214.527854 +system.mem_ctrls.bytesPerActivate::stdev 285.194511 +system.mem_ctrls.bytesPerActivate::0-127 1174 22.42% 22.42% +system.mem_ctrls.bytesPerActivate::128-255 1531 29.24% 51.66% +system.mem_ctrls.bytesPerActivate::256-383 903 17.25% 68.91% +system.mem_ctrls.bytesPerActivate::384-511 514 9.82% 78.72% +system.mem_ctrls.bytesPerActivate::512-639 271 5.18% 83.90% +system.mem_ctrls.bytesPerActivate::640-767 207 3.95% 87.85% +system.mem_ctrls.bytesPerActivate::768-895 152 2.90% 90.76% +system.mem_ctrls.bytesPerActivate::896-1023 138 2.64% 93.39% +system.mem_ctrls.bytesPerActivate::1024-1151 346 6.61% 100.00% +system.mem_ctrls.bytesPerActivate::total 5236 +system.mem_ctrls.rdPerTurnAround::samples 810 +system.mem_ctrls.rdPerTurnAround::mean 15.576543 +system.mem_ctrls.rdPerTurnAround::gmean 15.495477 +system.mem_ctrls.rdPerTurnAround::stdev 1.646720 +system.mem_ctrls.rdPerTurnAround::12-13 65 8.02% 8.02% +system.mem_ctrls.rdPerTurnAround::14-15 342 42.22% 50.25% +system.mem_ctrls.rdPerTurnAround::16-17 321 39.63% 89.88% +system.mem_ctrls.rdPerTurnAround::18-19 78 9.63% 99.51% +system.mem_ctrls.rdPerTurnAround::20-21 3 0.37% 99.88% +system.mem_ctrls.rdPerTurnAround::34-35 1 0.12% 100.00% +system.mem_ctrls.rdPerTurnAround::total 810 +system.mem_ctrls.wrPerTurnAround::samples 810 +system.mem_ctrls.wrPerTurnAround::mean 16.404938 +system.mem_ctrls.wrPerTurnAround::gmean 16.379881 +system.mem_ctrls.wrPerTurnAround::stdev 0.941542 +system.mem_ctrls.wrPerTurnAround::16 674 83.21% 83.21% +system.mem_ctrls.wrPerTurnAround::17 11 1.36% 84.57% +system.mem_ctrls.wrPerTurnAround::18 60 7.41% 91.98% +system.mem_ctrls.wrPerTurnAround::19 63 7.78% 99.75% +system.mem_ctrls.wrPerTurnAround::20 2 0.25% 100.00% +system.mem_ctrls.wrPerTurnAround::total 810 +system.mem_ctrls.totQLat 246353 +system.mem_ctrls.totMemAccLat 486380 +system.mem_ctrls.totBusLat 63165 +system.mem_ctrls.avgQLat 19.50 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 38.50 +system.mem_ctrls.avgRdBW 434.96 +system.mem_ctrls.avgWrBW 457.51 +system.mem_ctrls.avgRdBWSys 992.87 +system.mem_ctrls.avgWrBWSys 992.73 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 6.97 +system.mem_ctrls.busUtilRead 3.40 +system.mem_ctrls.busUtilWrite 3.57 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 26.25 +system.mem_ctrls.readRowHits 8783 +system.mem_ctrls.writeRowHits 11891 +system.mem_ctrls.readRowHitRate 69.52 +system.mem_ctrls.writeRowHitRate 89.27 +system.mem_ctrls.avgGap 32.23 +system.mem_ctrls.pageHitRate 79.66 +system.mem_ctrls_0.actEnergy 9660420 +system.mem_ctrls_0.preEnergy 5204808 +system.mem_ctrls_0.readEnergy 43456896 +system.mem_ctrls_0.writeEnergy 32865120 +system.mem_ctrls_0.refreshEnergy 143825760.000000 +system.mem_ctrls_0.actBackEnergy 210861240 +system.mem_ctrls_0.preBackEnergy 3899904 +system.mem_ctrls_0.actPowerDownEnergy 517171488 +system.mem_ctrls_0.prePowerDownEnergy 60469632 +system.mem_ctrls_0.selfRefreshEnergy 27711816 +system.mem_ctrls_0.totalEnergy 1055147052 +system.mem_ctrls_0.averagePower 567.641952 +system.mem_ctrls_0.totalIdleTime 1386171 +system.mem_ctrls_0.memoryStateTime::IDLE 3568 +system.mem_ctrls_0.memoryStateTime::REF 60894 +system.mem_ctrls_0.memoryStateTime::SREF 94587 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 157473 +system.mem_ctrls_0.memoryStateTime::ACT 408155 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 1134148 +system.mem_ctrls_1.actEnergy 27803160 +system.mem_ctrls_1.preEnergy 15027096 +system.mem_ctrls_1.readEnergy 100862496 +system.mem_ctrls_1.writeEnergy 78116256 +system.mem_ctrls_1.refreshEnergy 147513600.000000 +system.mem_ctrls_1.actBackEnergy 209065056 +system.mem_ctrls_1.preBackEnergy 3613824 +system.mem_ctrls_1.actPowerDownEnergy 587665896 +system.mem_ctrls_1.prePowerDownEnergy 32830080 +system.mem_ctrls_1.selfRefreshEnergy 6217440 +system.mem_ctrls_1.totalEnergy 1208714904 +system.mem_ctrls_1.averagePower 650.257504 +system.mem_ctrls_1.totalIdleTime 1390821 +system.mem_ctrls_1.memoryStateTime::IDLE 2339 +system.mem_ctrls_1.memoryStateTime::REF 62430 +system.mem_ctrls_1.memoryStateTime::SREF 16702 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 85495 +system.mem_ctrls_1.memoryStateTime::ACT 403118 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 1288741 +system.pwrStateResidencyTicks::UNDEFINED 1858825 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 45 +system.cpu.pwrStateResidencyTicks::ON 1858825 +system.cpu.numCycles 1858825 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 107505 +system.cpu.committedOps 107717 +system.cpu.num_int_alu_accesses 107132 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 6215 +system.cpu.num_conditional_control_insts 17634 +system.cpu.num_int_insts 107132 +system.cpu.num_fp_insts 12 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 134283 +system.cpu.num_int_register_writes 70918 +system.cpu.num_fp_register_reads 12 +system.cpu.num_fp_register_writes 0 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 41605 +system.cpu.num_load_insts 25266 +system.cpu.num_store_insts 16339 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 1858825 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 23849 +system.cpu.op_class::No_OpClass 49 0.05% 0.05% +system.cpu.op_class::IntAlu 65954 61.20% 61.25% +system.cpu.op_class::IntMult 124 0.12% 61.36% +system.cpu.op_class::IntDiv 30 0.03% 61.39% +system.cpu.op_class::FloatAdd 0 0.00% 61.39% +system.cpu.op_class::FloatCmp 0 0.00% 61.39% +system.cpu.op_class::FloatCvt 0 0.00% 61.39% +system.cpu.op_class::FloatMult 0 0.00% 61.39% +system.cpu.op_class::FloatMultAcc 0 0.00% 61.39% +system.cpu.op_class::FloatDiv 0 0.00% 61.39% +system.cpu.op_class::FloatMisc 0 0.00% 61.39% +system.cpu.op_class::FloatSqrt 0 0.00% 61.39% +system.cpu.op_class::SimdAdd 0 0.00% 61.39% +system.cpu.op_class::SimdAddAcc 0 0.00% 61.39% +system.cpu.op_class::SimdAlu 0 0.00% 61.39% +system.cpu.op_class::SimdCmp 0 0.00% 61.39% +system.cpu.op_class::SimdCvt 0 0.00% 61.39% +system.cpu.op_class::SimdMisc 0 0.00% 61.39% +system.cpu.op_class::SimdMult 0 0.00% 61.39% +system.cpu.op_class::SimdMultAcc 0 0.00% 61.39% +system.cpu.op_class::SimdShift 0 0.00% 61.39% +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.39% +system.cpu.op_class::SimdSqrt 0 0.00% 61.39% +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.39% +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.39% +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.39% +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.39% +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.39% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.39% +system.cpu.op_class::MemRead 25266 23.45% 84.84% +system.cpu.op_class::MemWrite 16327 15.15% 99.99% +system.cpu.op_class::FloatMemRead 0 0.00% 99.99% +system.cpu.op_class::FloatMemWrite 12 0.01% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 107762 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 57670 +system.ruby.delayHist | 57670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 57670 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 156830 +system.ruby.outstanding_req_hist_seqr::samples 176093 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 156830 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 156830 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 176093 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 176093 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 156829 -system.ruby.latency_hist_seqr::mean 10.744033 -system.ruby.latency_hist_seqr::gmean 2.067079 -system.ruby.latency_hist_seqr::stdev 25.213617 -system.ruby.latency_hist_seqr | 144536 92.16% 92.16% | 11426 7.29% 99.45% | 606 0.39% 99.83% | 87 0.06% 99.89% | 95 0.06% 99.95% | 65 0.04% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 0 0.00% 99.99% | 10 0.01% 100.00% -system.ruby.latency_hist_seqr::total 156829 +system.ruby.latency_hist_seqr::samples 176092 +system.ruby.latency_hist_seqr::mean 9.555988 +system.ruby.latency_hist_seqr::gmean 1.877495 +system.ruby.latency_hist_seqr::stdev 23.909492 +system.ruby.latency_hist_seqr | 163928 93.09% 93.09% | 11377 6.46% 99.55% | 529 0.30% 99.85% | 95 0.05% 99.91% | 91 0.05% 99.96% | 54 0.03% 99.99% | 8 0.00% 99.99% | 3 0.00% 100.00% | 0 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.latency_hist_seqr::total 176092 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 127112 +system.ruby.hit_latency_hist_seqr::samples 147255 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 127112 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 127112 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 147255 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 147255 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 29717 -system.ruby.miss_latency_hist_seqr::mean 52.423327 -system.ruby.miss_latency_hist_seqr::gmean 46.160524 -system.ruby.miss_latency_hist_seqr::stdev 34.809845 -system.ruby.miss_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% -system.ruby.miss_latency_hist_seqr::total 29717 -system.ruby.Directory.incomplete_times_seqr 29716 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.016133 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999752 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.032267 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.740878 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.016135 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.032267 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 127112 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 29717 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 156829 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.016133 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.998244 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.085150 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.064534 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.016135 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999715 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.998498 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999759 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.096797 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.740922 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 8.066815 -system.ruby.network.routers0.msg_count.Control::2 29717 -system.ruby.network.routers0.msg_count.Data::2 29713 -system.ruby.network.routers0.msg_count.Response_Data::4 29717 -system.ruby.network.routers0.msg_count.Writeback_Control::3 29713 -system.ruby.network.routers0.msg_bytes.Control::2 237736 -system.ruby.network.routers0.msg_bytes.Data::2 2139336 -system.ruby.network.routers0.msg_bytes.Response_Data::4 2139624 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 237704 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.740889 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.016133 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999504 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.016135 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999924 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 8.066815 -system.ruby.network.routers1.msg_count.Control::2 29717 -system.ruby.network.routers1.msg_count.Data::2 29713 -system.ruby.network.routers1.msg_count.Response_Data::4 29717 -system.ruby.network.routers1.msg_count.Writeback_Control::3 29713 -system.ruby.network.routers1.msg_bytes.Control::2 237736 -system.ruby.network.routers1.msg_bytes.Data::2 2139336 -system.ruby.network.routers1.msg_bytes.Response_Data::4 2139624 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 237704 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.740915 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.016133 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.999254 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.016135 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.999884 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.016133 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.998751 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.016135 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.999802 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.032267 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.740899 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999003 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999844 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.032267 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.740908 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 8.066815 -system.ruby.network.routers2.msg_count.Control::2 29717 -system.ruby.network.routers2.msg_count.Data::2 29713 -system.ruby.network.routers2.msg_count.Response_Data::4 29717 -system.ruby.network.routers2.msg_count.Writeback_Control::3 29713 -system.ruby.network.routers2.msg_bytes.Control::2 237736 -system.ruby.network.routers2.msg_bytes.Data::2 2139336 -system.ruby.network.routers2.msg_bytes.Response_Data::4 2139624 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 237704 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 89151 -system.ruby.network.msg_count.Data 89139 -system.ruby.network.msg_count.Response_Data 89151 -system.ruby.network.msg_count.Writeback_Control 89139 -system.ruby.network.msg_byte.Control 713208 -system.ruby.network.msg_byte.Data 6418008 -system.ruby.network.msg_byte.Response_Data 6418872 -system.ruby.network.msg_byte.Writeback_Control 713112 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 8.067249 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 29717 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 29713 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2139624 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 237704 -system.ruby.network.routers0.throttle1.link_utilization 8.066381 -system.ruby.network.routers0.throttle1.msg_count.Control::2 29717 -system.ruby.network.routers0.throttle1.msg_count.Data::2 29713 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 237736 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2139336 -system.ruby.network.routers1.throttle0.link_utilization 8.066381 -system.ruby.network.routers1.throttle0.msg_count.Control::2 29717 -system.ruby.network.routers1.throttle0.msg_count.Data::2 29713 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 237736 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2139336 -system.ruby.network.routers1.throttle1.link_utilization 8.067249 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 29717 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 29713 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2139624 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 237704 -system.ruby.network.routers2.throttle0.link_utilization 8.067249 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 29717 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 29713 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2139624 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 237704 -system.ruby.network.routers2.throttle1.link_utilization 8.066381 -system.ruby.network.routers2.throttle1.msg_count.Control::2 29717 -system.ruby.network.routers2.throttle1.msg_count.Data::2 29713 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 237736 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2139336 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 29717 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 29717 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 29717 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 29713 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 29713 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 29713 # delay histogram for vnet_2 +system.ruby.miss_latency_hist_seqr::samples 28837 +system.ruby.miss_latency_hist_seqr::mean 53.246801 +system.ruby.miss_latency_hist_seqr::gmean 46.837910 +system.ruby.miss_latency_hist_seqr::stdev 34.758587 +system.ruby.miss_latency_hist_seqr | 16673 57.82% 57.82% | 11377 39.45% 97.27% | 529 1.83% 99.11% | 95 0.33% 99.43% | 91 0.32% 99.75% | 54 0.19% 99.94% | 8 0.03% 99.97% | 3 0.01% 99.98% | 0 0.00% 99.98% | 7 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 28837 +system.ruby.Directory.incomplete_times_seqr 28836 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015511 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999804 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.031025 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.751023 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015514 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999963 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.031025 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999963 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 147255 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 28837 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 176092 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015511 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.998607 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.094733 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.062050 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015514 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999718 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015511 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.998809 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015514 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999761 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.093071 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.751067 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.network.routers0.percent_links_utilized 7.756244 +system.ruby.network.routers0.msg_count.Control::2 28837 +system.ruby.network.routers0.msg_count.Data::2 28833 +system.ruby.network.routers0.msg_count.Response_Data::4 28837 +system.ruby.network.routers0.msg_count.Writeback_Control::3 28833 +system.ruby.network.routers0.msg_bytes.Control::2 230696 +system.ruby.network.routers0.msg_bytes.Data::2 2075976 +system.ruby.network.routers0.msg_bytes.Response_Data::4 2076264 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 230664 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.031025 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.751034 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015511 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999607 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015514 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999925 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.network.routers1.percent_links_utilized 7.756244 +system.ruby.network.routers1.msg_count.Control::2 28837 +system.ruby.network.routers1.msg_count.Data::2 28833 +system.ruby.network.routers1.msg_count.Response_Data::4 28837 +system.ruby.network.routers1.msg_count.Writeback_Control::3 28833 +system.ruby.network.routers1.msg_bytes.Control::2 230696 +system.ruby.network.routers1.msg_bytes.Data::2 2075976 +system.ruby.network.routers1.msg_bytes.Response_Data::4 2076264 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 230664 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031025 +system.ruby.network.int_link_buffers02.avg_stall_time 7.751060 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015511 +system.ruby.network.int_link_buffers08.avg_stall_time 2.999409 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015514 +system.ruby.network.int_link_buffers09.avg_stall_time 2.999885 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015511 +system.ruby.network.int_link_buffers13.avg_stall_time 4.999010 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015514 +system.ruby.network.int_link_buffers14.avg_stall_time 4.999804 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.031025 +system.ruby.network.int_link_buffers17.avg_stall_time 9.751044 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015511 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999210 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015514 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999845 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.031025 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.751053 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.network.routers2.percent_links_utilized 7.756244 +system.ruby.network.routers2.msg_count.Control::2 28837 +system.ruby.network.routers2.msg_count.Data::2 28833 +system.ruby.network.routers2.msg_count.Response_Data::4 28837 +system.ruby.network.routers2.msg_count.Writeback_Control::3 28833 +system.ruby.network.routers2.msg_bytes.Control::2 230696 +system.ruby.network.routers2.msg_bytes.Data::2 2075976 +system.ruby.network.routers2.msg_bytes.Response_Data::4 2076264 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 230664 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.network.msg_count.Control 86511 +system.ruby.network.msg_count.Data 86499 +system.ruby.network.msg_count.Response_Data 86511 +system.ruby.network.msg_count.Writeback_Control 86499 +system.ruby.network.msg_byte.Control 692088 +system.ruby.network.msg_byte.Data 6227928 +system.ruby.network.msg_byte.Response_Data 6228792 +system.ruby.network.msg_byte.Writeback_Control 691992 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 1858825 +system.ruby.network.routers0.throttle0.link_utilization 7.756674 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 28837 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 28833 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2076264 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 230664 +system.ruby.network.routers0.throttle1.link_utilization 7.755813 +system.ruby.network.routers0.throttle1.msg_count.Control::2 28837 +system.ruby.network.routers0.throttle1.msg_count.Data::2 28833 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 230696 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2075976 +system.ruby.network.routers1.throttle0.link_utilization 7.755813 +system.ruby.network.routers1.throttle0.msg_count.Control::2 28837 +system.ruby.network.routers1.throttle0.msg_count.Data::2 28833 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 230696 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2075976 +system.ruby.network.routers1.throttle1.link_utilization 7.756674 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 28837 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 28833 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2076264 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 230664 +system.ruby.network.routers2.throttle0.link_utilization 7.756674 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 28837 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 28833 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2076264 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 230664 +system.ruby.network.routers2.throttle1.link_utilization 7.755813 +system.ruby.network.routers2.throttle1.msg_count.Control::2 28837 +system.ruby.network.routers2.throttle1.msg_count.Data::2 28833 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 230696 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2075976 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 28837 +system.ruby.delayVCHist.vnet_1 | 28837 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 28837 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 28833 +system.ruby.delayVCHist.vnet_2 | 28833 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 28833 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 23780 -system.ruby.LD.latency_hist_seqr::mean 23.543860 -system.ruby.LD.latency_hist_seqr::gmean 5.728326 -system.ruby.LD.latency_hist_seqr::stdev 33.566569 -system.ruby.LD.latency_hist_seqr | 19950 83.89% 83.89% | 3533 14.86% 98.75% | 205 0.86% 99.61% | 27 0.11% 99.73% | 36 0.15% 99.88% | 25 0.11% 99.98% | 0 0.00% 99.98% | 2 0.01% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% -system.ruby.LD.latency_hist_seqr::total 23780 +system.ruby.LD.latency_hist_seqr::samples 25029 +system.ruby.LD.latency_hist_seqr::mean 27.003356 +system.ruby.LD.latency_hist_seqr::gmean 6.909676 +system.ruby.LD.latency_hist_seqr::stdev 35.388693 +system.ruby.LD.latency_hist_seqr | 19926 79.61% 79.61% | 4779 19.09% 98.71% | 221 0.88% 99.59% | 36 0.14% 99.73% | 38 0.15% 99.88% | 23 0.09% 99.98% | 4 0.02% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 25029 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 12809 +system.ruby.LD.hit_latency_hist_seqr::samples 12406 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 12809 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 12809 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 12406 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 12406 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 10971 -system.ruby.LD.miss_latency_hist_seqr::mean 49.864552 -system.ruby.LD.miss_latency_hist_seqr::gmean 43.959200 -system.ruby.LD.miss_latency_hist_seqr::stdev 34.000652 -system.ruby.LD.miss_latency_hist_seqr | 7141 65.09% 65.09% | 3533 32.20% 97.29% | 205 1.87% 99.16% | 27 0.25% 99.41% | 36 0.33% 99.74% | 25 0.23% 99.96% | 0 0.00% 99.96% | 2 0.02% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 10971 +system.ruby.LD.miss_latency_hist_seqr::samples 12623 +system.ruby.LD.miss_latency_hist_seqr::mean 52.559693 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.183238 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.139513 +system.ruby.LD.miss_latency_hist_seqr | 7520 59.57% 59.57% | 4779 37.86% 97.43% | 221 1.75% 99.18% | 36 0.29% 99.47% | 38 0.30% 99.77% | 23 0.18% 99.95% | 4 0.03% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 12623 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 -system.ruby.ST.latency_hist_seqr::samples 19712 -system.ruby.ST.latency_hist_seqr::mean 12.481128 -system.ruby.ST.latency_hist_seqr::gmean 2.637325 -system.ruby.ST.latency_hist_seqr::stdev 25.900228 -system.ruby.ST.latency_hist_seqr | 18468 93.69% 93.69% | 1151 5.84% 99.53% | 59 0.30% 99.83% | 14 0.07% 99.90% | 7 0.04% 99.93% | 6 0.03% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 7 0.04% 100.00% -system.ruby.ST.latency_hist_seqr::total 19712 +system.ruby.ST.latency_hist_seqr::samples 16102 +system.ruby.ST.latency_hist_seqr::mean 15.175196 +system.ruby.ST.latency_hist_seqr::gmean 3.407774 +system.ruby.ST.latency_hist_seqr::stdev 26.847749 +system.ruby.ST.latency_hist_seqr | 14941 92.79% 92.79% | 1070 6.65% 99.43% | 62 0.39% 99.82% | 8 0.05% 99.87% | 10 0.06% 99.93% | 6 0.04% 99.97% | 0 0.00% 99.97% | 1 0.01% 99.98% | 0 0.00% 99.98% | 4 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 16102 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 14522 +system.ruby.ST.hit_latency_hist_seqr::samples 10712 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 14522 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 14522 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 10712 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 10712 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 -system.ruby.ST.miss_latency_hist_seqr::samples 5190 -system.ruby.ST.miss_latency_hist_seqr::mean 44.606166 -system.ruby.ST.miss_latency_hist_seqr::gmean 39.775024 -system.ruby.ST.miss_latency_hist_seqr::stdev 33.868458 -system.ruby.ST.miss_latency_hist_seqr | 3946 76.03% 76.03% | 1151 22.18% 98.21% | 59 1.14% 99.34% | 14 0.27% 99.61% | 7 0.13% 99.75% | 6 0.12% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 7 0.13% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 5190 +system.ruby.ST.miss_latency_hist_seqr::samples 5390 +system.ruby.ST.miss_latency_hist_seqr::mean 43.346753 +system.ruby.ST.miss_latency_hist_seqr::gmean 38.966782 +system.ruby.ST.miss_latency_hist_seqr::stdev 30.990026 +system.ruby.ST.miss_latency_hist_seqr | 4229 78.46% 78.46% | 1070 19.85% 98.31% | 62 1.15% 99.46% | 8 0.15% 99.61% | 10 0.19% 99.80% | 6 0.11% 99.91% | 0 0.00% 99.91% | 1 0.02% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 5390 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 113337 -system.ruby.IFETCH.latency_hist_seqr::mean 7.756293 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.599835 -system.ruby.IFETCH.latency_hist_seqr::stdev 21.972545 -system.ruby.IFETCH.latency_hist_seqr | 106118 93.63% 93.63% | 6742 5.95% 99.58% | 342 0.30% 99.88% | 46 0.04% 99.92% | 52 0.05% 99.97% | 34 0.03% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 113337 +system.ruby.IFETCH.latency_hist_seqr::samples 134487 +system.ruby.IFETCH.latency_hist_seqr::mean 5.587313 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.367123 +system.ruby.IFETCH.latency_hist_seqr::stdev 18.655199 +system.ruby.IFETCH.latency_hist_seqr | 128690 95.69% 95.69% | 5432 4.04% 99.73% | 243 0.18% 99.91% | 48 0.04% 99.94% | 42 0.03% 99.98% | 25 0.02% 99.99% | 4 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 134487 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 99781 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 123855 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 99781 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 99781 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 123855 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 123855 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 13556 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 57.487017 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.839427 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.033938 -system.ruby.IFETCH.miss_latency_hist_seqr | 6337 46.75% 46.75% | 6742 49.73% 96.48% | 342 2.52% 99.00% | 46 0.34% 99.34% | 52 0.38% 99.73% | 34 0.25% 99.98% | 1 0.01% 99.99% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 13556 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 10632 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.026147 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.223378 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.074822 +system.ruby.IFETCH.miss_latency_hist_seqr | 4835 45.48% 45.48% | 5432 51.09% 96.57% | 243 2.29% 98.85% | 48 0.45% 99.30% | 42 0.40% 99.70% | 25 0.24% 99.93% | 4 0.04% 99.97% | 1 0.01% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 10632 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 32 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 319 +system.ruby.Load_Linked.latency_hist_seqr::samples 237 +system.ruby.Load_Linked.latency_hist_seqr::mean 45.810127 +system.ruby.Load_Linked.latency_hist_seqr::gmean 23.754096 +system.ruby.Load_Linked.latency_hist_seqr::stdev 37.801581 +system.ruby.Load_Linked.latency_hist_seqr | 45 18.99% 18.99% | 89 37.55% 56.54% | 95 40.08% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 2 0.84% 98.31% | 3 1.27% 99.58% | 0 0.00% 99.58% | 0 0.00% 99.58% | 1 0.42% 100.00% +system.ruby.Load_Linked.latency_hist_seqr::total 237 +system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 45 +system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 45 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 45 +system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 32 +system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 319 +system.ruby.Load_Linked.miss_latency_hist_seqr::samples 192 +system.ruby.Load_Linked.miss_latency_hist_seqr::mean 56.312500 +system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 49.908811 +system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 34.375449 +system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 89 46.35% 46.35% | 95 49.48% 95.83% | 1 0.52% 96.35% | 1 0.52% 96.88% | 2 1.04% 97.92% | 3 1.56% 99.48% | 0 0.00% 99.48% | 0 0.00% 99.48% | 1 0.52% 100.00% +system.ruby.Load_Linked.miss_latency_hist_seqr::total 192 +system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.latency_hist_seqr::samples 237 +system.ruby.Store_Conditional.latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 237 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.latency_hist_seqr::total 237 +system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 237 +system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 237 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.hit_latency_hist_seqr::total 237 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 29717 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.423327 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.160524 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.809845 -system.ruby.Directory.miss_mach_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 29717 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 28837 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.246801 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.837910 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.758587 +system.ruby.Directory.miss_mach_latency_hist_seqr | 16673 57.82% 57.82% | 11377 39.45% 97.27% | 529 1.83% 99.11% | 95 0.33% 99.43% | 91 0.32% 99.75% | 54 0.19% 99.94% | 8 0.03% 99.97% | 3 0.01% 99.98% | 0 0.00% 99.98% | 7 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 28837 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -640,51 +681,59 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 10971 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 49.864552 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 43.959200 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.000652 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7141 65.09% 65.09% | 3533 32.20% 97.29% | 205 1.87% 99.16% | 27 0.25% 99.41% | 36 0.33% 99.74% | 25 0.23% 99.96% | 0 0.00% 99.96% | 2 0.02% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 10971 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 12623 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.559693 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.183238 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.139513 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7520 59.57% 59.57% | 4779 37.86% 97.43% | 221 1.75% 99.18% | 36 0.29% 99.47% | 38 0.30% 99.77% | 23 0.18% 99.95% | 4 0.03% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 12623 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5190 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.606166 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.775024 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.868458 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 3946 76.03% 76.03% | 1151 22.18% 98.21% | 59 1.14% 99.34% | 14 0.27% 99.61% | 7 0.13% 99.75% | 6 0.12% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 7 0.13% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5190 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5390 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.346753 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.966782 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.990026 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 4229 78.46% 78.46% | 1070 19.85% 98.31% | 62 1.15% 99.46% | 8 0.15% 99.61% | 10 0.19% 99.80% | 6 0.11% 99.91% | 0 0.00% 99.91% | 1 0.02% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5390 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 13556 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 57.487017 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.839427 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.033938 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 6337 46.75% 46.75% | 6742 49.73% 96.48% | 342 2.52% 99.00% | 46 0.34% 99.34% | 52 0.38% 99.73% | 34 0.25% 99.98% | 1 0.01% 99.99% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 13556 -system.ruby.Directory_Controller.GETX 29717 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 29713 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 29717 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 29713 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 29717 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 29713 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 29717 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 29713 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 23780 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 113337 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 19712 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 29717 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 29713 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 29713 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 10971 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 13556 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 5190 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 12809 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 99781 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 14522 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 29713 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 29713 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 24527 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 5190 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 10632 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.026147 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.223378 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.074822 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4835 45.48% 45.48% | 5432 51.09% 96.57% | 243 2.29% 98.85% | 48 0.45% 99.30% | 42 0.40% 99.70% | 25 0.24% 99.93% | 4 0.04% 99.97% | 1 0.01% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 10632 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 192 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 56.312500 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 49.908811 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 34.375449 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 89 46.35% 46.35% | 95 49.48% 95.83% | 1 0.52% 96.35% | 1 0.52% 96.88% | 2 1.04% 97.92% | 3 1.56% 99.48% | 0 0.00% 99.48% | 0 0.00% 99.48% | 1 0.52% 100.00% +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 192 +system.ruby.Directory_Controller.GETX 28837 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 28833 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 28837 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 28833 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 28837 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 28833 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 28837 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 28833 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 25029 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 134487 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 16576 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 28837 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 28833 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 28833 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 12623 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 10632 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 5582 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 12406 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 123855 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 10994 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 28833 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 28833 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 23255 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 5582 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini index 4d0cc1f98..e9823fe0e 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -287,7 +289,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -296,14 +298,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json index 70b4bf86d..8ea1a4257 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json @@ -292,6 +292,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -376,21 +377,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -402,6 +404,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr index fd133b12b..a01f2057a 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout index 7cb72814c..852fd2516 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:50 -gem5 executing on zizzer, pid 34099 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:12:17 +gem5 executing on boldrock, pid 2077 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. mul: PASS mul, overflow: PASS mulh: PASS @@ -48,4 +46,4 @@ remuw, truncate: PASS remuw/0: PASS remuw, "overflow": PASS remuw, sign extend: PASS -Exiting @ tick 209715500 because target called exit() +Exiting @ tick 246972500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt index 336f36a46..165d9b176 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt @@ -1,515 +1,549 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000210 # Number of seconds simulated -sim_ticks 209715500 # Number of ticks simulated -final_tick 209715500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42175 # Simulator instruction rate (inst/s) -host_op_rate 42174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78069260 # Simulator tick rate (ticks/s) -host_mem_usage 242960 # Number of bytes of host memory used -host_seconds 2.69 # Real time elapsed on the host -sim_insts 113291 # Number of instructions simulated -sim_ops 113291 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 37952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 16640 # Number of bytes read from this memory -system.physmem.bytes_read::total 54592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 37952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 37952 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 260 # Number of read requests responded to by this memory -system.physmem.num_reads::total 853 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 180968979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 79345590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 260314569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 180968979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 180968979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 180968979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 79345590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 260314569 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 45 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 209715500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 419431 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 113291 # Number of instructions committed -system.cpu.committedOps 113291 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 8529 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls -system.cpu.num_int_insts 113292 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 151096 # number of times the integer registers were read -system.cpu.num_int_register_writes 76188 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 43493 # number of memory refs -system.cpu.num_load_insts 23780 # Number of load instructions -system.cpu.num_store_insts 19713 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 419431 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 25920 # Number of branches fetched -system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction -system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction -system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction -system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction -system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 113337 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.473039 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43232 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 260 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.276923 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.473039 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052606 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052606 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 260 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.063477 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87244 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87244 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23719 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23719 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19513 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19513 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 43232 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 43232 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 43232 # number of overall hits -system.cpu.dcache.overall_hits::total 43232 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 199 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 199 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 260 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 260 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 260 # number of overall misses -system.cpu.dcache.overall_misses::total 260 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12537000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12537000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16380000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16380000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16380000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16380000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43492 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43492 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43492 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43492 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002565 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002565 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010095 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005978 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005978 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005978 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005978 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 260 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3782000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12338000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12338000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16120000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16120000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16120000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16120000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002565 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002565 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010095 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010095 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005978 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005978 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6 # number of replacements -system.cpu.icache.tags.tagsinuse 302.746737 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 112745 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 593 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 190.126476 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 302.746737 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.147826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.147826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 587 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.286621 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 227269 # Number of tag accesses -system.cpu.icache.tags.data_accesses 227269 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 112745 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 112745 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 112745 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 112745 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 112745 # number of overall hits -system.cpu.icache.overall_hits::total 112745 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 593 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 593 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 593 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 593 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 593 # number of overall misses -system.cpu.icache.overall_misses::total 593 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37359500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37359500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37359500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37359500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37359500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37359500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 113338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 113338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 113338 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 113338 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 113338 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 113338 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005232 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005232 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005232 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005232 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005232 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005232 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63000.843170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63000.843170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63000.843170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63000.843170 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6 # number of writebacks -system.cpu.icache.writebacks::total 6 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 593 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 593 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 593 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 593 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 593 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 593 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36766500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36766500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36766500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36766500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36766500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36766500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005232 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005232 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005232 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.843170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.843170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 520.331439 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 6 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 853 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007034 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 304.845382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.486056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009303 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.015879 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 853 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.026031 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7725 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7725 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 6 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 593 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 593 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 593 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 260 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 853 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 593 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 260 # number of overall misses -system.cpu.l2cache.overall_misses::total 853 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12039500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12039500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35877000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 35877000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3690500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3690500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35877000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15730000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 51607000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35877000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15730000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 51607000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 6 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 593 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 593 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 593 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 260 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 853 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 593 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 260 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 853 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.843170 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.843170 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.843170 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.586166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.843170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.586166 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 593 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 593 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 593 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 853 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 593 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 260 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 853 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10049500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10049500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29947000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29947000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3080500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3080500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29947000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13130000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 43077000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29947000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13130000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 43077000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.843170 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.843170 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 859 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1712 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 853 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 853 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 435500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 889500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 390000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 853 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 654 # Transaction distribution -system.membus.trans_dist::ReadExReq 199 # Transaction distribution -system.membus.trans_dist::ReadExResp 199 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 654 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1706 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 54592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 853 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 853 # Request fanout histogram -system.membus.reqLayer0.occupancy 853500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4265000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.0 # Layer utilization (%) +sim_seconds 0.000247 +sim_ticks 246972500 +final_tick 246972500 +sim_freq 1000000000000 +host_inst_rate 6087 +host_op_rate 6099 +host_tick_rate 13984193 +host_mem_usage 268924 +host_seconds 17.66 +sim_insts 107505 +sim_ops 107717 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 246972500 +system.physmem.bytes_read::cpu.inst 43968 +system.physmem.bytes_read::cpu.data 29184 +system.physmem.bytes_read::total 73152 +system.physmem.bytes_inst_read::cpu.inst 43968 +system.physmem.bytes_inst_read::total 43968 +system.physmem.num_reads::cpu.inst 687 +system.physmem.num_reads::cpu.data 456 +system.physmem.num_reads::total 1143 +system.physmem.bw_read::cpu.inst 178027918 +system.physmem.bw_read::cpu.data 118167002 +system.physmem.bw_read::total 296194920 +system.physmem.bw_inst_read::cpu.inst 178027918 +system.physmem.bw_inst_read::total 178027918 +system.physmem.bw_total::cpu.inst 178027918 +system.physmem.bw_total::cpu.data 118167002 +system.physmem.bw_total::total 296194920 +system.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 45 +system.cpu.pwrStateResidencyTicks::ON 246972500 +system.cpu.numCycles 493945 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 107505 +system.cpu.committedOps 107717 +system.cpu.num_int_alu_accesses 107132 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 6215 +system.cpu.num_conditional_control_insts 17634 +system.cpu.num_int_insts 107132 +system.cpu.num_fp_insts 12 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 134283 +system.cpu.num_int_register_writes 70918 +system.cpu.num_fp_register_reads 12 +system.cpu.num_fp_register_writes 0 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 41605 +system.cpu.num_load_insts 25266 +system.cpu.num_store_insts 16339 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 493945 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 23849 +system.cpu.op_class::No_OpClass 49 0.05% 0.05% +system.cpu.op_class::IntAlu 65954 61.20% 61.25% +system.cpu.op_class::IntMult 124 0.12% 61.36% +system.cpu.op_class::IntDiv 30 0.03% 61.39% +system.cpu.op_class::FloatAdd 0 0.00% 61.39% +system.cpu.op_class::FloatCmp 0 0.00% 61.39% +system.cpu.op_class::FloatCvt 0 0.00% 61.39% +system.cpu.op_class::FloatMult 0 0.00% 61.39% +system.cpu.op_class::FloatMultAcc 0 0.00% 61.39% +system.cpu.op_class::FloatDiv 0 0.00% 61.39% +system.cpu.op_class::FloatMisc 0 0.00% 61.39% +system.cpu.op_class::FloatSqrt 0 0.00% 61.39% +system.cpu.op_class::SimdAdd 0 0.00% 61.39% +system.cpu.op_class::SimdAddAcc 0 0.00% 61.39% +system.cpu.op_class::SimdAlu 0 0.00% 61.39% +system.cpu.op_class::SimdCmp 0 0.00% 61.39% +system.cpu.op_class::SimdCvt 0 0.00% 61.39% +system.cpu.op_class::SimdMisc 0 0.00% 61.39% +system.cpu.op_class::SimdMult 0 0.00% 61.39% +system.cpu.op_class::SimdMultAcc 0 0.00% 61.39% +system.cpu.op_class::SimdShift 0 0.00% 61.39% +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.39% +system.cpu.op_class::SimdSqrt 0 0.00% 61.39% +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.39% +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.39% +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.39% +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.39% +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.39% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.39% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.39% +system.cpu.op_class::MemRead 25266 23.45% 84.84% +system.cpu.op_class::MemWrite 16327 15.15% 99.99% +system.cpu.op_class::FloatMemRead 0 0.00% 99.99% +system.cpu.op_class::FloatMemWrite 12 0.01% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 107762 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu.dcache.tags.replacements 0 +system.cpu.dcache.tags.tagsinuse 327.838970 +system.cpu.dcache.tags.total_refs 41149 +system.cpu.dcache.tags.sampled_refs 456 +system.cpu.dcache.tags.avg_refs 90.239035 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 327.838970 +system.cpu.dcache.tags.occ_percent::cpu.data 0.080039 +system.cpu.dcache.tags.occ_percent::total 0.080039 +system.cpu.dcache.tags.occ_task_id_blocks::1024 456 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 11 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 432 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.111328 +system.cpu.dcache.tags.tag_accesses 83666 +system.cpu.dcache.tags.data_accesses 83666 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu.dcache.ReadReq_hits::cpu.data 24798 +system.cpu.dcache.ReadReq_hits::total 24798 +system.cpu.dcache.WriteReq_hits::cpu.data 15879 +system.cpu.dcache.WriteReq_hits::total 15879 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 235 +system.cpu.dcache.LoadLockedReq_hits::total 235 +system.cpu.dcache.StoreCondReq_hits::cpu.data 237 +system.cpu.dcache.StoreCondReq_hits::total 237 +system.cpu.dcache.demand_hits::cpu.data 40677 +system.cpu.dcache.demand_hits::total 40677 +system.cpu.dcache.overall_hits::cpu.data 40677 +system.cpu.dcache.overall_hits::total 40677 +system.cpu.dcache.ReadReq_misses::cpu.data 231 +system.cpu.dcache.ReadReq_misses::total 231 +system.cpu.dcache.WriteReq_misses::cpu.data 223 +system.cpu.dcache.WriteReq_misses::total 223 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_misses::total 2 +system.cpu.dcache.demand_misses::cpu.data 454 +system.cpu.dcache.demand_misses::total 454 +system.cpu.dcache.overall_misses::cpu.data 454 +system.cpu.dcache.overall_misses::total 454 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14553000 +system.cpu.dcache.ReadReq_miss_latency::total 14553000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14049000 +system.cpu.dcache.WriteReq_miss_latency::total 14049000 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 +system.cpu.dcache.demand_miss_latency::cpu.data 28602000 +system.cpu.dcache.demand_miss_latency::total 28602000 +system.cpu.dcache.overall_miss_latency::cpu.data 28602000 +system.cpu.dcache.overall_miss_latency::total 28602000 +system.cpu.dcache.ReadReq_accesses::cpu.data 25029 +system.cpu.dcache.ReadReq_accesses::total 25029 +system.cpu.dcache.WriteReq_accesses::cpu.data 16102 +system.cpu.dcache.WriteReq_accesses::total 16102 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 +system.cpu.dcache.LoadLockedReq_accesses::total 237 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 237 +system.cpu.dcache.StoreCondReq_accesses::total 237 +system.cpu.dcache.demand_accesses::cpu.data 41131 +system.cpu.dcache.demand_accesses::total 41131 +system.cpu.dcache.overall_accesses::cpu.data 41131 +system.cpu.dcache.overall_accesses::total 41131 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009229 +system.cpu.dcache.ReadReq_miss_rate::total 0.009229 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013849 +system.cpu.dcache.WriteReq_miss_rate::total 0.013849 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.008439 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.008439 +system.cpu.dcache.demand_miss_rate::cpu.data 0.011038 +system.cpu.dcache.demand_miss_rate::total 0.011038 +system.cpu.dcache.overall_miss_rate::cpu.data 0.011038 +system.cpu.dcache.overall_miss_rate::total 0.011038 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.demand_avg_miss_latency::total 63000 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.overall_avg_miss_latency::total 63000 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 231 +system.cpu.dcache.ReadReq_mshr_misses::total 231 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 223 +system.cpu.dcache.WriteReq_mshr_misses::total 223 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 +system.cpu.dcache.demand_mshr_misses::cpu.data 454 +system.cpu.dcache.demand_mshr_misses::total 454 +system.cpu.dcache.overall_mshr_misses::cpu.data 454 +system.cpu.dcache.overall_mshr_misses::total 454 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14322000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14322000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13826000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13826000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 124000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 124000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28148000 +system.cpu.dcache.demand_mshr_miss_latency::total 28148000 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28148000 +system.cpu.dcache.overall_mshr_miss_latency::total 28148000 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.009229 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.009229 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013849 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013849 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.008439 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.008439 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.011038 +system.cpu.dcache.demand_mshr_miss_rate::total 0.011038 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011038 +system.cpu.dcache.overall_mshr_miss_rate::total 0.011038 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu.icache.tags.replacements 34 +system.cpu.icache.tags.tagsinuse 404.619001 +system.cpu.icache.tags.total_refs 133800 +system.cpu.icache.tags.sampled_refs 688 +system.cpu.icache.tags.avg_refs 194.476744 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 404.619001 +system.cpu.icache.tags.occ_percent::cpu.inst 0.197568 +system.cpu.icache.tags.occ_percent::total 0.197568 +system.cpu.icache.tags.occ_task_id_blocks::1024 654 +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 +system.cpu.icache.tags.age_task_id_blocks_1024::1 111 +system.cpu.icache.tags.age_task_id_blocks_1024::2 501 +system.cpu.icache.tags.occ_task_id_percent::1024 0.319336 +system.cpu.icache.tags.tag_accesses 269664 +system.cpu.icache.tags.data_accesses 269664 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu.icache.ReadReq_hits::cpu.inst 133800 +system.cpu.icache.ReadReq_hits::total 133800 +system.cpu.icache.demand_hits::cpu.inst 133800 +system.cpu.icache.demand_hits::total 133800 +system.cpu.icache.overall_hits::cpu.inst 133800 +system.cpu.icache.overall_hits::total 133800 +system.cpu.icache.ReadReq_misses::cpu.inst 688 +system.cpu.icache.ReadReq_misses::total 688 +system.cpu.icache.demand_misses::cpu.inst 688 +system.cpu.icache.demand_misses::total 688 +system.cpu.icache.overall_misses::cpu.inst 688 +system.cpu.icache.overall_misses::total 688 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43296500 +system.cpu.icache.ReadReq_miss_latency::total 43296500 +system.cpu.icache.demand_miss_latency::cpu.inst 43296500 +system.cpu.icache.demand_miss_latency::total 43296500 +system.cpu.icache.overall_miss_latency::cpu.inst 43296500 +system.cpu.icache.overall_miss_latency::total 43296500 +system.cpu.icache.ReadReq_accesses::cpu.inst 134488 +system.cpu.icache.ReadReq_accesses::total 134488 +system.cpu.icache.demand_accesses::cpu.inst 134488 +system.cpu.icache.demand_accesses::total 134488 +system.cpu.icache.overall_accesses::cpu.inst 134488 +system.cpu.icache.overall_accesses::total 134488 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005116 +system.cpu.icache.ReadReq_miss_rate::total 0.005116 +system.cpu.icache.demand_miss_rate::cpu.inst 0.005116 +system.cpu.icache.demand_miss_rate::total 0.005116 +system.cpu.icache.overall_miss_rate::cpu.inst 0.005116 +system.cpu.icache.overall_miss_rate::total 0.005116 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62930.959302 +system.cpu.icache.ReadReq_avg_miss_latency::total 62930.959302 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62930.959302 +system.cpu.icache.demand_avg_miss_latency::total 62930.959302 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62930.959302 +system.cpu.icache.overall_avg_miss_latency::total 62930.959302 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 34 +system.cpu.icache.writebacks::total 34 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 688 +system.cpu.icache.ReadReq_mshr_misses::total 688 +system.cpu.icache.demand_mshr_misses::cpu.inst 688 +system.cpu.icache.demand_mshr_misses::total 688 +system.cpu.icache.overall_mshr_misses::cpu.inst 688 +system.cpu.icache.overall_mshr_misses::total 688 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42608500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 42608500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42608500 +system.cpu.icache.demand_mshr_miss_latency::total 42608500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42608500 +system.cpu.icache.overall_mshr_miss_latency::total 42608500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005116 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005116 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005116 +system.cpu.icache.demand_mshr_miss_rate::total 0.005116 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005116 +system.cpu.icache.overall_mshr_miss_rate::total 0.005116 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61930.959302 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61930.959302 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61930.959302 +system.cpu.icache.demand_avg_mshr_miss_latency::total 61930.959302 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61930.959302 +system.cpu.icache.overall_avg_mshr_miss_latency::total 61930.959302 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 748.536096 +system.cpu.l2cache.tags.total_refs 35 +system.cpu.l2cache.tags.sampled_refs 1143 +system.cpu.l2cache.tags.avg_refs 0.030621 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 420.677738 +system.cpu.l2cache.tags.occ_blocks::cpu.data 327.858357 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012838 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010005 +system.cpu.l2cache.tags.occ_percent::total 0.022844 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1143 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 966 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.034882 +system.cpu.l2cache.tags.tag_accesses 10567 +system.cpu.l2cache.tags.data_accesses 10567 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu.l2cache.WritebackClean_hits::writebacks 34 +system.cpu.l2cache.WritebackClean_hits::total 34 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 +system.cpu.l2cache.ReadCleanReq_hits::total 1 +system.cpu.l2cache.demand_hits::cpu.inst 1 +system.cpu.l2cache.demand_hits::total 1 +system.cpu.l2cache.overall_hits::cpu.inst 1 +system.cpu.l2cache.overall_hits::total 1 +system.cpu.l2cache.ReadExReq_misses::cpu.data 223 +system.cpu.l2cache.ReadExReq_misses::total 223 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 687 +system.cpu.l2cache.ReadCleanReq_misses::total 687 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 233 +system.cpu.l2cache.ReadSharedReq_misses::total 233 +system.cpu.l2cache.demand_misses::cpu.inst 687 +system.cpu.l2cache.demand_misses::cpu.data 456 +system.cpu.l2cache.demand_misses::total 1143 +system.cpu.l2cache.overall_misses::cpu.inst 687 +system.cpu.l2cache.overall_misses::cpu.data 456 +system.cpu.l2cache.overall_misses::total 1143 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13491500 +system.cpu.l2cache.ReadExReq_miss_latency::total 13491500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 41565000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 41565000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14096500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14096500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 41565000 +system.cpu.l2cache.demand_miss_latency::cpu.data 27588000 +system.cpu.l2cache.demand_miss_latency::total 69153000 +system.cpu.l2cache.overall_miss_latency::cpu.inst 41565000 +system.cpu.l2cache.overall_miss_latency::cpu.data 27588000 +system.cpu.l2cache.overall_miss_latency::total 69153000 +system.cpu.l2cache.WritebackClean_accesses::writebacks 34 +system.cpu.l2cache.WritebackClean_accesses::total 34 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 223 +system.cpu.l2cache.ReadExReq_accesses::total 223 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 688 +system.cpu.l2cache.ReadCleanReq_accesses::total 688 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 233 +system.cpu.l2cache.ReadSharedReq_accesses::total 233 +system.cpu.l2cache.demand_accesses::cpu.inst 688 +system.cpu.l2cache.demand_accesses::cpu.data 456 +system.cpu.l2cache.demand_accesses::total 1144 +system.cpu.l2cache.overall_accesses::cpu.inst 688 +system.cpu.l2cache.overall_accesses::cpu.data 456 +system.cpu.l2cache.overall_accesses::total 1144 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998547 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998547 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998547 +system.cpu.l2cache.demand_miss_rate::cpu.data 1 +system.cpu.l2cache.demand_miss_rate::total 0.999126 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998547 +system.cpu.l2cache.overall_miss_rate::cpu.data 1 +system.cpu.l2cache.overall_miss_rate::total 0.999126 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.183406 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.183406 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.183406 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.demand_avg_miss_latency::total 60501.312336 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.183406 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.overall_avg_miss_latency::total 60501.312336 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 223 +system.cpu.l2cache.ReadExReq_mshr_misses::total 223 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 687 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 687 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 233 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 233 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 687 +system.cpu.l2cache.demand_mshr_misses::cpu.data 456 +system.cpu.l2cache.demand_mshr_misses::total 1143 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 687 +system.cpu.l2cache.overall_mshr_misses::cpu.data 456 +system.cpu.l2cache.overall_mshr_misses::total 1143 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11261500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11261500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34695000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34695000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11766500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11766500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34695000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23028000 +system.cpu.l2cache.demand_mshr_miss_latency::total 57723000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34695000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23028000 +system.cpu.l2cache.overall_mshr_miss_latency::total 57723000 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998547 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998547 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998547 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999126 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998547 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999126 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.183406 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.183406 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.183406 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.312336 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.183406 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.312336 +system.cpu.toL2Bus.snoop_filter.tot_requests 1178 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 34 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 246972500 +system.cpu.toL2Bus.trans_dist::ReadResp 921 +system.cpu.toL2Bus.trans_dist::WritebackClean 34 +system.cpu.toL2Bus.trans_dist::ReadExReq 223 +system.cpu.toL2Bus.trans_dist::ReadExResp 223 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 688 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 233 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1410 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 912 +system.cpu.toL2Bus.pkt_count::total 2322 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46208 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29184 +system.cpu.toL2Bus.pkt_size::total 75392 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1144 +system.cpu.toL2Bus.snoop_fanout::mean 0 +system.cpu.toL2Bus.snoop_fanout::stdev 0 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1144 100.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 0 +system.cpu.toL2Bus.snoop_fanout::total 1144 +system.cpu.toL2Bus.reqLayer0.occupancy 623000 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 1032000 +system.cpu.toL2Bus.respLayer0.utilization 0.4 +system.cpu.toL2Bus.respLayer1.occupancy 684000 +system.cpu.toL2Bus.respLayer1.utilization 0.3 +system.membus.snoop_filter.tot_requests 1143 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 246972500 +system.membus.trans_dist::ReadResp 920 +system.membus.trans_dist::ReadExReq 223 +system.membus.trans_dist::ReadExResp 223 +system.membus.trans_dist::ReadSharedReq 920 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2286 +system.membus.pkt_count::total 2286 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73152 +system.membus.pkt_size::total 73152 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1143 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1143 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1143 +system.membus.reqLayer0.occupancy 1144500 +system.membus.reqLayer0.utilization 0.5 +system.membus.respLayer1.occupancy 5715000 +system.membus.respLayer1.utilization 2.3 ---------- End Simulation Statistics ---------- |