diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt | 521 |
1 files changed, 265 insertions, 256 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 0c812fe4f..9f174a09c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27282000 # Number of ticks simulated -final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27705000 # Number of ticks simulated +final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96636 # Simulator instruction rate (inst/s) -host_op_rate 96628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173854426 # Simulator tick rate (ticks/s) -host_mem_usage 231852 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 72386 # Simulator instruction rate (inst/s) +host_op_rate 72381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132251643 # Simulator tick rate (ticks/s) +host_mem_usage 260736 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27904 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27248500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 436 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 688395596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 318787223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1007182819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 688395596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 318787223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1007182819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 436 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97 # Per bank write bursts +system.physmem.perBankRdBursts::1 28 # Per bank write bursts +system.physmem.perBankRdBursts::2 38 # Per bank write bursts +system.physmem.perBankRdBursts::3 20 # Per bank write bursts +system.physmem.perBankRdBursts::4 16 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 29 # Per bank write bursts +system.physmem.perBankRdBursts::7 32 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 58 # Per bank write bursts +system.physmem.perBankRdBursts::15 33 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 27671500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 436 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation -system.physmem.totQLat 1525500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests -system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 6325000 # Total cycles spent in bank access -system.physmem.avgQLat 3498.85 # Average queueing delay per request -system.physmem.avgBankLat 14506.88 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23005.73 # Average memory access latency -system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.37 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 387 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.743118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 502.320204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 32.81% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 10 15.62% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 7.81% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 12.50% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 3.12% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 3.12% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.12% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.56% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.56% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.56% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.56% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.56% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 3.12% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 2 3.12% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.56% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.56% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 3.12% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 1 1.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation +system.physmem.totQLat 2393750 # Total ticks spent queuing +system.physmem.totMemAccLat 10830000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6256250 # Total ticks spent accessing banks +system.physmem.avgQLat 5490.25 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14349.20 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24839.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1007.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1007.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.87 # Data bus utilization in percentage +system.physmem.busUtilRead 7.87 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.39 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 372 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 62496.56 # Average gap between requests -system.membus.throughput 1020453046 # Throughput (bytes/s) +system.physmem.avgGap 63466.74 # Average gap between requests +system.physmem.pageHitRate 85.32 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.29 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1004872767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -204,8 +213,8 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.6 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -216,7 +225,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54565 # number of cpu cycles simulated +system.cpu.numCycles 55411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -238,12 +247,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21832 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 436 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37843 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 32.196463 # Percentage of cycles cpu is active +system.cpu.activity 31.704896 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -255,36 +264,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.654597 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads -system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.654597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.273628 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.273628 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41985 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.229846 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46058 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 16.879320 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46608 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 15.886737 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 52533 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.193915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46102 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 16.799913 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.234439 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -297,12 +306,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26803000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26803000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26803000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26803000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -315,12 +324,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70349.081365 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +350,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20772000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20772000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1009492871 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -375,21 +384,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 501000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 200.306060 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.564740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -407,17 +416,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20448500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24149750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9603750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30052250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20448500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9603750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30052250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -440,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,17 +479,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16729000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19771250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7902250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24631250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16729000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7902250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24631250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -492,27 +501,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.671839 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -531,14 +540,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4274250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4274250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25400750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25400750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29675000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29675000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -557,14 +566,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61822.916667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -589,14 +598,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9746250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9746250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -605,14 +614,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |