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-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt454
1 files changed, 227 insertions, 227 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 73324a4d5..c2589ee2d 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000025 # Number of seconds simulated
-sim_ticks 25007500 # Number of ticks simulated
-final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000026 # Number of seconds simulated
+sim_ticks 25615500 # Number of ticks simulated
+final_tick 25615500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 72389 # Simulator instruction rate (inst/s)
-host_op_rate 72383 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 119272701 # Simulator tick rate (ticks/s)
-host_mem_usage 221376 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 51797 # Simulator instruction rate (inst/s)
+host_op_rate 51795 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 87424707 # Simulator tick rate (ticks/s)
+host_mem_usage 219936 # Number of bytes of host memory used
+host_seconds 0.29 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
@@ -19,36 +19,36 @@ system.physmem.bytes_inst_read::total 19072 # Nu
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 762651205 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 353174048 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1115825252 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 762651205 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 762651205 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 762651205 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 353174048 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1115825252 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 744549199 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 344791240 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1089340438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 744549199 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 744549199 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 744549199 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 344791240 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1089340438 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 50016 # number of cpu cycles simulated
+system.cpu.numCycles 51232 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 5015 # Number of BP lookups
+system.cpu.branch_predictor.lookups 5014 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3353 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2379 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 3332 # Number of BTB lookups
+system.cpu.branch_predictor.BTBLookups 3331 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 2040 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 174 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 61.224490 # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHitPct 61.242870 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 2214 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 2801 # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedNotTaken 2800 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14401 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 25512 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 4993 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 3952 # Number of Address Generations
+system.cpu.regfile_manager.regForwards 4991 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 3950 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 1316 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1000 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 2316 # Number of Branches Incorrectly Predicted
@@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 11084 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 21887 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 22262 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 453 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 32683 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 17333 # Number of cycles cpu stages are processed.
-system.cpu.activity 34.654910 # Percentage of cycles cpu is active
+system.cpu.timesIdled 525 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 33883 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 17349 # Number of cycles cpu stages are processed.
+system.cpu.activity 33.863601 # Percentage of cycles cpu is active
system.cpu.comLoads 2226 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3359 # Number of Branches instructions committed
@@ -75,72 +75,72 @@ system.cpu.committedInsts 15175 # Nu
system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total)
-system.cpu.cpi 3.295947 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 3.376079 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 3.295947 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.303403 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 3.376079 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.296202 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.303403 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 36923 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.296202 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 38139 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13093 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 26.177623 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 40814 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 9202 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 18.398113 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 41191 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 8825 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 17.644354 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 47132 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 5.766155 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 40690 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 9326 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 18.646033 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.utilization 25.556293 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 42033 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 9199 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 17.955575 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 42406 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 8826 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 17.227514 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 48347 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 2885 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 5.631246 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 41905 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 9327 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 18.205418 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 165.557258 # Cycle average of tags in use
-system.cpu.icache.total_refs 2602 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 164.555255 # Cycle average of tags in use
+system.cpu.icache.total_refs 2600 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 8.702341 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 8.695652 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 165.557258 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.080839 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.080839 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 2602 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 2602 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 2602 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 2602 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 2602 # number of overall hits
-system.cpu.icache.overall_hits::total 2602 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
-system.cpu.icache.overall_misses::total 368 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 20203500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 20203500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 20203500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 20203500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 20203500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 20203500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2970 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2970 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2970 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2970 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.123906 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.123906 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.123906 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54900.815217 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54900.815217 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54900.815217 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 164.555255 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.080349 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.080349 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 2600 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 2600 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 2600 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 2600 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 2600 # number of overall hits
+system.cpu.icache.overall_hits::total 2600 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses
+system.cpu.icache.overall_misses::total 371 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 20687000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 20687000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 20687000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 20687000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 20687000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 20687000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2971 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2971 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2971 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2971 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2971 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2971 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124874 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.124874 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.124874 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.124874 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.124874 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.124874 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55760.107817 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55760.107817 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55760.107817 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55760.107817 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55760.107817 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55760.107817 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -149,72 +149,72 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15872000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 15872000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.101347 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.101347 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52730.897010 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16327000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 16327000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16327000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 16327000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16327000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 16327000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101313 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.101313 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.101313 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54242.524917 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54242.524917 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54242.524917 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54242.524917 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54242.524917 # average overall mshr miss latency
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system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@@ -227,36 +227,36 @@ system.cpu.dcache.overall_accesses::cpu.data 3668
system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
@@ -265,14 +265,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
@@ -281,26 +281,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623
system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
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@@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
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@@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
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@@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
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-system.cpu.l2cache.demand_mshr_miss_latency::total 17464500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12379500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2285000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14664500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3604000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3604000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12379500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5889000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18268500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12379500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5889000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18268500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
@@ -403,17 +403,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39910.511364 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40188.235294 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41403.010033 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43113.207547 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41660.511364 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42400 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42400 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------