summaryrefslogtreecommitdiff
path: root/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout')
-rwxr-xr-xtests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout9
1 files changed, 4 insertions, 5 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index f333d0ba2..81d821c63 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -1,12 +1,11 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:07:38
-gem5 started Jun 21 2014 11:08:19
+gem5 compiled Apr 22 2015 08:08:31
+gem5 started Apr 22 2015 08:14:03
gem5 executing on phenom
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
@@ -20,4 +19,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 26706500 because target called exit()
+Exiting @ tick 27482500 because target called exit()