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-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt968
1 files changed, 484 insertions, 484 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index a830552cf..39a395968 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 19778500 # Number of ticks simulated
-final_tick 19778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000023 # Number of seconds simulated
+sim_ticks 23428500 # Number of ticks simulated
+final_tick 23428500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 52882 # Simulator instruction rate (inst/s)
-host_op_rate 52877 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 72439157 # Simulator tick rate (ticks/s)
-host_mem_usage 223656 # Number of bytes of host memory used
+host_inst_rate 53742 # Simulator instruction rate (inst/s)
+host_op_rate 53738 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 87205048 # Simulator tick rate (ticks/s)
+host_mem_usage 223912 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 30848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1090477033 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 472432186 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1562909220 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1090477033 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1090477033 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1090477033 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 472432186 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1562909220 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 483 # Total number of read requests seen
+system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 917856457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 398830484 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1316686941 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 917856457 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 917856457 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 917856457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 398830484 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1316686941 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 482 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30912 # Total number of bytes read from memory
+system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30848 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
@@ -40,7 +40,7 @@ system.physmem.perBankRdReqs::0 70 # Tr
system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 19726000 # Total gap between requests
+system.physmem.totGap 23376000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 483 # Categorize read packet sizes
+system.physmem.readPktSize::6 482 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 271 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
@@ -164,262 +164,262 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3361480 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13231480 # Sum of mem lat for all requests
-system.physmem.totBusLat 1932000 # Total cycles spent in databus access
-system.physmem.totBankLat 7938000 # Total cycles spent in bank access
-system.physmem.avgQLat 6959.59 # Average queueing delay per request
-system.physmem.avgBankLat 16434.78 # Average bank access latency per request
+system.physmem.totQLat 2488982 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12396982 # Sum of mem lat for all requests
+system.physmem.totBusLat 1928000 # Total cycles spent in databus access
+system.physmem.totBankLat 7980000 # Total cycles spent in bank access
+system.physmem.avgQLat 5163.86 # Average queueing delay per request
+system.physmem.avgBankLat 16556.02 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27394.37 # Average memory access latency
-system.physmem.avgRdBW 1562.91 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25719.88 # Average memory access latency
+system.physmem.avgRdBW 1316.69 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1562.91 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1316.69 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 9.77 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.67 # Average read queue length over time
+system.physmem.busUtil 8.23 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.53 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 394 # Number of row buffer hits during reads
+system.physmem.readRowHits 393 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 40840.58 # Average gap between requests
+system.physmem.avgGap 48497.93 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 39558 # number of cpu cycles simulated
+system.cpu.numCycles 46858 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6961 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 4635 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 5126 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 2626 # Number of BTB hits
+system.cpu.BPredUnit.lookups 6941 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 4630 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 5115 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 2636 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 443 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 11957 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 32537 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6961 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 3069 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9617 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3192 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7429 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 12393 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 32407 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6941 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 3078 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9616 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3187 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8221 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 5561 # Number of cache lines fetched
+system.cpu.fetch.PendingTrapStallCycles 943 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 5564 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 31813 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.022758 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.197280 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 33142 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.977823 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.154937 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 22196 69.77% 69.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4753 14.94% 84.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 498 1.57% 86.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 475 1.49% 87.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 708 2.23% 89.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 718 2.26% 92.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 247 0.78% 93.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 285 0.90% 93.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1933 6.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 23526 70.99% 70.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4767 14.38% 85.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 497 1.50% 86.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 473 1.43% 88.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 713 2.15% 90.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 723 2.18% 92.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 250 0.75% 93.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 284 0.86% 94.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1909 5.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 31813 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.175969 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.822514 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12679 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8183 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 8793 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 186 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1972 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 30371 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1972 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13365 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 199 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7520 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 8338 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 419 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 27570 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 33142 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.148128 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.691600 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 13096 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9104 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 8780 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 30240 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13789 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 355 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 8257 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 8329 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 447 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 27456 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 24556 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 51144 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 51144 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 134 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 24477 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 50943 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 50943 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 10737 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 10658 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 696 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2824 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3648 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2459 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 2830 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3653 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 23227 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 659 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21740 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 23144 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 660 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21674 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8509 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 6060 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 184 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 31813 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.683368 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.298612 # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined 8424 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 6018 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 185 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 33142 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.653974 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.274325 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 22340 70.22% 70.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3583 11.26% 81.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2473 7.77% 89.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1697 5.33% 94.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 903 2.84% 97.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 492 1.55% 98.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 244 0.77% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23639 71.33% 71.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3658 11.04% 82.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2441 7.37% 89.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1702 5.14% 94.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 894 2.70% 97.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 488 1.47% 99.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 244 0.74% 99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 60 0.18% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 16 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 31813 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 33142 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 50 28.09% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 26 14.61% 42.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 102 57.30% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 49 28.16% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 26 14.94% 43.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 99 56.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 16052 73.84% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3424 15.75% 89.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2264 10.41% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 16000 73.82% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3426 15.81% 89.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2248 10.37% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21740 # Type of FU issued
-system.cpu.iq.rate 0.549573 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008188 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 75584 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 32421 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19938 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 21674 # Type of FU issued
+system.cpu.iq.rate 0.462546 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 174 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008028 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 76777 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 32254 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19887 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21918 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21848 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1423 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1011 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1972 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25068 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 512 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 3648 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2459 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 659 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 238 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 24981 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 536 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 3653 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 660 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 961 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1257 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20524 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3260 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1216 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 295 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20477 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3262 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1197 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1182 # number of nop insts executed
-system.cpu.iew.exec_refs 5396 # number of memory reference insts executed
-system.cpu.iew.exec_branches 4297 # Number of branches executed
-system.cpu.iew.exec_stores 2136 # Number of stores executed
-system.cpu.iew.exec_rate 0.518833 # Inst execution rate
-system.cpu.iew.wb_sent 20197 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 19938 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 9248 # num instructions producing a value
-system.cpu.iew.wb_consumers 11357 # num instructions consuming a value
+system.cpu.iew.exec_nop 1177 # number of nop insts executed
+system.cpu.iew.exec_refs 5386 # number of memory reference insts executed
+system.cpu.iew.exec_branches 4289 # Number of branches executed
+system.cpu.iew.exec_stores 2124 # Number of stores executed
+system.cpu.iew.exec_rate 0.437001 # Inst execution rate
+system.cpu.iew.wb_sent 20145 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19887 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 9217 # num instructions producing a value
+system.cpu.iew.wb_consumers 11299 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.504019 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.814300 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.424410 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.815736 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9816 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9729 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1124 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 29858 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.507804 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.195478 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 31194 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.486055 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.173479 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 22523 75.43% 75.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 3989 13.36% 88.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1473 4.93% 93.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 787 2.64% 96.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 343 1.15% 97.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 245 0.82% 98.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 323 1.08% 99.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 69 0.23% 99.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106 0.36% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23830 76.39% 76.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 4047 12.97% 89.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1444 4.63% 94.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 788 2.53% 96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 343 1.10% 97.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 244 0.78% 98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 322 1.03% 99.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 69 0.22% 99.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 107 0.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 29858 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 31194 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -430,68 +430,68 @@ system.cpu.commit.branches 3358 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 53907 # The number of ROB reads
-system.cpu.rob.rob_writes 51935 # The number of ROB writes
-system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7745 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11943516 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2975060 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14918576 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3394062 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3394062 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11943516 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6369122 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18312638 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11943516 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6369122 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18312638 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28218.139466 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43540.571429 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30631.422500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34006.578313 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34006.578313 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28218.139466 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38120.561644 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.418219 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28218.139466 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38120.561644 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.418219 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35546.178571 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47223.174603 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37389.914787 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40892.313253 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40892.313253 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------