diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 926 |
1 files changed, 463 insertions, 463 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index b851aeb29..fe03e9faf 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25944000 # Number of ticks simulated -final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27482500 # Number of ticks simulated +final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95549 # Simulator instruction rate (inst/s) -host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171686089 # Simulator tick rate (ticks/s) -host_mem_usage 292480 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 86365 # Simulator instruction rate (inst/s) +host_op_rate 86358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164391633 # Simulator tick rate (ticks/s) +host_mem_usage 291648 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22016 # Nu system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory system.physmem.num_reads::total 492 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25892500 # Total gap between requests +system.physmem.totGap 27431000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,307 +186,307 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation -system.physmem.totQLat 2786000 # Total ticks spent queuing -system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation +system.physmem.totQLat 3613750 # Total ticks spent queuing +system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.48 # Data bus utilization in percentage -system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.95 # Data bus utilization in percentage +system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 411 # Number of row buffer hits during reads +system.physmem.readRowHits 412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52627.03 # Average gap between requests -system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 55754.07 # Average gap between requests +system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) -system.physmem_0.averagePower 857.473194 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states +system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ) +system.physmem_0.averagePower 853.427679 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) -system.physmem_1.averagePower 812.585763 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states +system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ) +system.physmem_1.averagePower 816.177825 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 8578 # Number of BP lookups -system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3046 # Number of BTB hits +system.cpu.branchPred.lookups 8538 # Number of BP lookups +system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3053 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 51.087684 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51889 # number of cpu cycles simulated +system.cpu.numCycles 54966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed -system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 6844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 6847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 6918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups +system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 6898 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 768 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 767 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21921 # Type of FU issued -system.cpu.iq.rate 0.422459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 226 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21924 # Type of FU issued +system.cpu.iq.rate 0.398865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 225 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1127 # number of nop insts executed -system.cpu.iew.exec_refs 5373 # number of memory reference insts executed -system.cpu.iew.exec_branches 4425 # Number of branches executed +system.cpu.iew.exec_nop 1126 # number of nop insts executed +system.cpu.iew.exec_refs 5371 # number of memory reference insts executed +system.cpu.iew.exec_branches 4427 # Number of branches executed system.cpu.iew.exec_stores 2024 # Number of stores executed -system.cpu.iew.exec_rate 0.402956 # Inst execution rate -system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 20237 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9846 # num instructions producing a value -system.cpu.iew.wb_consumers 12767 # num instructions consuming a value +system.cpu.iew.exec_rate 0.380490 # Inst execution rate +system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 20244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9848 # num instructions producing a value +system.cpu.iew.wb_consumers 12670 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back +system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,105 +532,105 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54809 # The number of ROB reads -system.cpu.rob.rob_writes 52997 # The number of ROB writes -system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54715 # The number of ROB reads +system.cpu.rob.rob_writes 52974 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads -system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 33401 # number of integer regfile reads -system.cpu.int_regfile_writes 18599 # number of integer regfile writes -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads +system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 33408 # number of integer regfile reads +system.cpu.int_regfile_writes 18606 # number of integer regfile writes +system.cpu.misc_regfile_reads 7133 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits -system.cpu.dcache.overall_hits::total 4118 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4119 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits +system.cpu.dcache.overall_hits::total 4119 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses -system.cpu.dcache.overall_misses::total 548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses +system.cpu.dcache.overall_misses::total 546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -639,135 +639,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 190.975563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5904 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13252 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits -system.cpu.icache.overall_hits::total 5925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses -system.cpu.icache.overall_misses::total 528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 13222 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13222 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5904 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5904 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5904 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5904 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5904 # number of overall hits +system.cpu.icache.overall_hits::total 5904 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 534 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 534 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 534 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 534 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 534 # number of overall misses +system.cpu.icache.overall_misses::total 534 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37367000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37367000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37367000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37367000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37367000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37367000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6438 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6438 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6438 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6438 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082945 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082945 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082945 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082945 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082945 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082945 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69975.655431 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69975.655431 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69975.655431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69975.655431 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 188 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 188 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 188 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 188 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 188 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 188 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26526250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26526250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26526250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26526250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26526250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26526250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053743 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.053743 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.053743 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76665.462428 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76665.462428 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 224.896195 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 190.368376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.527819 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006863 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses @@ -788,17 +788,17 @@ system.cpu.l2cache.demand_misses::total 492 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 492 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26158750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5078750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31237500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6304750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6304750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26158750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11383500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37542250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26158750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11383500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37542250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) @@ -821,17 +821,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995951 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76042.877907 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78134.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76375.305623 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75960.843373 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75960.843373 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76305.386179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76305.386179 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -851,17 +851,17 @@ system.cpu.l2cache.demand_mshr_misses::total 492 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4272750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26134000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21861250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31412250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution @@ -908,10 +908,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.trans_dist::ReadReq 409 # Transaction distribution system.membus.trans_dist::ReadResp 408 # Transaction distribution @@ -932,9 +932,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |