diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 1177 |
1 files changed, 594 insertions, 583 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 698dda741..24ae64048 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,50 +1,50 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29089500 # Number of ticks simulated -final_tick 29089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29908500 # Number of ticks simulated +final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39190 # Simulator instruction rate (inst/s) -host_op_rate 39188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78964807 # Simulator tick rate (ticks/s) -host_mem_usage 252916 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host +host_inst_rate 58398 # Simulator instruction rate (inst/s) +host_op_rate 58392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120966219 # Simulator tick rate (ticks/s) +host_mem_usage 251080 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 32768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23360 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 365 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 798638684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 323415665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1122054350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 798638684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 798638684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 798638684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 323415665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1122054350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 511 # Number of read requests accepted +system.physmem.num_reads::total 512 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 781048866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 314559406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1095608272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 781048866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 781048866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 781048866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 314559406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1095608272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 513 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 513 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 32832 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side +system.physmem.bytesReadSys 32832 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 105 # Per bank write bursts system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 53 # Per bank write bursts +system.physmem.perBankRdBursts::2 55 # Per bank write bursts system.physmem.perBankRdBursts::3 27 # Per bank write bursts system.physmem.perBankRdBursts::4 23 # Per bank write bursts system.physmem.perBankRdBursts::5 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29058000 # Total gap between requests +system.physmem.totGap 29877000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 511 # Read request sizes (log2) +system.physmem.readPktSize::6 513 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,310 +187,321 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 411.306667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 274.853259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.874505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 25.33% 42.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 16.00% 58.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 8.00% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3266500 # Total ticks spent queuing -system.physmem.totMemAccLat 12847750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6392.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 253.933476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.475070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 24.36% 46.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 6721500 # Total ticks spent queuing +system.physmem.totMemAccLat 16340250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13102.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25142.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1124.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31852.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1124.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.78 # Data bus utilization in percentage -system.physmem.busUtilRead 8.78 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.58 # Data bus utilization in percentage +system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 427 # Number of row buffer hits during reads +system.physmem.readRowHits 424 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 56864.97 # Average gap between requests -system.physmem.pageHitRate 83.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2113800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 58239.77 # Average gap between requests +system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20264970 # Total energy per rank (pJ) -system.physmem_0.averagePower 858.003493 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states +system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3642300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 9900900 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) +system.physmem_0.averagePower 608.449701 # Core power per rank (mW) +system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states +system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15332715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 721500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19350015 # Total energy per rank (pJ) -system.physmem_1.averagePower 819.264991 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4570750 # Time in different power states +system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2522250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10426440 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) +system.physmem_1.averagePower 576.319973 # Core power per rank (mW) +system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21719750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 12614 # Number of BP lookups -system.cpu.branchPred.condPredicted 7656 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9453 # Number of BTB lookups +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1286000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4831250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22868250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 12304 # Number of BP lookups +system.cpu.branchPred.condPredicted 7429 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1435 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9156 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 730 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9453 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7609 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 9156 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1824 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7332 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 865 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29089500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58180 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 29908500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 59818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15554 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 59055 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12614 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17529 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1090 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 720 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 35776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.650688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.904189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15502 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 57440 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12304 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2554 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 17524 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3065 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1117 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 7446 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 730 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 35692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.609324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.874327 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23025 64.36% 64.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4506 12.60% 76.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 507 1.42% 78.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 451 1.26% 79.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.13% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 707 1.98% 83.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 297 0.83% 84.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 355 0.99% 85.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5167 14.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23194 64.98% 64.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4479 12.55% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 496 1.39% 78.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 441 1.24% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 761 2.13% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 680 1.91% 84.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 284 0.80% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 358 1.00% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4999 14.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.216810 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.015040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12463 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13012 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7932 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 797 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 42051 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13239 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1819 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7921 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1465 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 37034 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1048 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 31990 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 66442 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54845 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 35692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.205691 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.960246 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12333 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13299 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7732 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1532 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 41071 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1532 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13082 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2036 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9748 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7750 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1544 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 36233 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 31392 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 65112 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 53717 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2920 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11337 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.708911 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.503990 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 17573 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 793 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 25032 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10993 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.701334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.501806 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26518 74.12% 74.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3268 9.13% 83.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1619 4.53% 87.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1541 4.31% 92.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1236 3.45% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 752 2.10% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 465 1.30% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 277 0.77% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26613 74.56% 74.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3169 8.88% 83.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1586 4.44% 87.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197 3.35% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 154 52.56% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51 17.41% 69.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 30.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164 53.07% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18584 73.27% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4272 16.84% 90.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18346 73.29% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 25362 # Type of FU issued -system.cpu.iq.rate 0.435923 # Inst issue rate -system.cpu.iq.fu_busy_cnt 293 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011553 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86911 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 44761 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22611 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 25032 # Type of FU issued +system.cpu.iq.rate 0.418469 # Inst issue rate +system.cpu.iq.fu_busy_cnt 309 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 86197 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 22374 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25655 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 25341 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1472 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1852 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 31164 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2920 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1532 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2073 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 30726 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1624 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1835 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23718 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1644 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1575 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1782 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23436 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1596 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1579 # number of nop insts executed -system.cpu.iew.exec_refs 6245 # number of memory reference insts executed -system.cpu.iew.exec_branches 5021 # Number of branches executed -system.cpu.iew.exec_stores 2300 # Number of stores executed -system.cpu.iew.exec_rate 0.407666 # Inst execution rate -system.cpu.iew.wb_sent 23107 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22611 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10526 # num instructions producing a value -system.cpu.iew.wb_consumers 13786 # num instructions consuming a value -system.cpu.iew.wb_rate 0.388639 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.763528 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 15913 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1532 # number of nop insts executed +system.cpu.iew.exec_refs 6191 # number of memory reference insts executed +system.cpu.iew.exec_branches 4986 # Number of branches executed +system.cpu.iew.exec_stores 2309 # Number of stores executed +system.cpu.iew.exec_rate 0.391788 # Inst execution rate +system.cpu.iew.wb_sent 22845 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22374 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10411 # num instructions producing a value +system.cpu.iew.wb_consumers 13650 # num instructions consuming a value +system.cpu.iew.wb_rate 0.374035 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762711 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.243420 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25892 79.33% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3639 11.15% 90.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1211 3.71% 94.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 601 1.84% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 338 1.04% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 300 0.92% 97.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 54 0.17% 99.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3555 10.90% 90.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1191 3.65% 94.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 577 1.77% 95.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 319 0.98% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 311 0.95% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 392 1.20% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 57 0.17% 99.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 239 0.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 32615 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,104 +547,104 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 62661 # The number of ROB reads -system.cpu.rob.rob_writes 65377 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 239 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 62190 # The number of ROB reads +system.cpu.rob.rob_writes 64431 # The number of ROB writes +system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 4.030202 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.030202 # CPI: Total CPI of All Threads -system.cpu.ipc 0.248127 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.248127 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36851 # number of integer regfile reads -system.cpu.int_regfile_writes 20552 # number of integer regfile writes -system.cpu.misc_regfile_reads 8143 # number of misc regfile reads +system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads +system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 36480 # number of integer regfile reads +system.cpu.int_regfile_writes 20296 # number of integer regfile writes +system.cpu.misc_regfile_reads 8094 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.825953 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 99.158435 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.825953 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024372 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024372 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.158435 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024209 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits -system.cpu.dcache.overall_hits::total 4642 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4573 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4573 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4573 # number of overall hits +system.cpu.dcache.overall_hits::total 4573 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 145 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 145 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses -system.cpu.dcache.overall_misses::total 549 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9476500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9476500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27259981 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27259981 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36736481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36736481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36736481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36736481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 554 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 554 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 554 # number of overall misses +system.cpu.dcache.overall_misses::total 554 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11443500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11443500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29003985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29003985 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40447485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40447485 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40447485 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40447485 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3685 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3685 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5127 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5127 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5127 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5127 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.039349 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66915.265938 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66915.265938 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.108055 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.108055 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.108055 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.108055 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73009.900722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73009.900722 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.956522 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 406 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 406 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 406 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -642,138 +653,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5190500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5190500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11645000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6888000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6888000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12966000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12966000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12966000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12966000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017639 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 206.188252 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 204.747820 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 206.188252 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.100678 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.100678 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 204.747820 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.099975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.099975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses -system.cpu.icache.tags.data_accesses 15425 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits -system.cpu.icache.overall_hits::total 6949 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses -system.cpu.icache.overall_misses::total 581 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40938500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40938500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40938500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40938500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40938500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40938500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70462.134251 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70462.134251 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 194 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses +system.cpu.icache.tags.data_accesses 15259 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits +system.cpu.icache.overall_hits::total 6856 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses +system.cpu.icache.overall_misses::total 590 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45891500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45891500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45891500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45891500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45891500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45891500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77782.203390 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77782.203390 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77782.203390 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77782.203390 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27977500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27977500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27977500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27977500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27977500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27977500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76650.684932 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76650.684932 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 367 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30257500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30257500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30257500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30257500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82445.504087 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82445.504087 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 305.425349 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 303.316506 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.546698 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 99.878652 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003048 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.009321 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.106814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 99.209691 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4631 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -782,64 +793,64 @@ system.cpu.l2cache.overall_hits::cpu.inst 2 # n system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 365 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 365 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 148 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 367 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 515 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994550 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994550 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76253.012048 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76253.012048 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75501.377410 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75501.377410 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78392.307692 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78392.307692 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75991.193738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75991.193738 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81326.027397 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81326.027397 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82708.576998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82708.576998 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -848,119 +859,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 365 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 365 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5499000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5499000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23777000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23777000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4465500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4465500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9964500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33741500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23777000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9964500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33741500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26034000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26034000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26034000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26034000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37319500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66253.012048 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66253.012048 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65501.377410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65501.377410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 367 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 32832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062257 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 513 99.61% 99.61% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 515 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 257500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 428 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 511 # Request fanout histogram +system.membus.snoop_fanout::samples 513 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 513 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 513 # Request fanout histogram +system.membus.reqLayer0.occupancy 627500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2693500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2707250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |