diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic')
4 files changed, 170 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..421dd8a46 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,102 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..df7964c68 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:02:00 +gem5 started Jan 23 2012 04:24:24 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 7618500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..389636d62 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,45 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7618500 # Number of ticks simulated +final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 296178 # Simulator instruction rate (inst/s) +host_tick_rate 148615294 # Simulator tick rate (ticks/s) +host_mem_usage 203776 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 15175 # Number of instructions simulated +system.physmem.bytes_read 72223 # Number of bytes read from this memory +system.physmem.bytes_inst_read 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9042 # Number of bytes written to this memory +system.physmem.num_reads 17446 # Number of read requests responded to by this memory +system.physmem.num_writes 1442 # Number of write requests responded to by this memory +system.physmem.num_other 6 # Number of other requests responded to by this memory +system.physmem.bw_read 9479950121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 10666797926 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 385 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls +system.cpu.num_int_insts 12231 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 29059 # number of times the integer registers were read +system.cpu.num_int_register_writes 13832 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 3684 # number of memory refs +system.cpu.num_load_insts 2232 # Number of load instructions +system.cpu.num_store_insts 1452 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 15238 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- |