diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index f6532c6ee..54833842f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000042 # Number of seconds simulated -sim_ticks 41800000 # Number of ticks simulated -final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000043 # Number of seconds simulated +sim_ticks 43120000 # Number of ticks simulated +final_tick 43120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 488993 # Simulator instruction rate (inst/s) -host_op_rate 488707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345414902 # Simulator tick rate (ticks/s) -host_mem_usage 221064 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 107758 # Simulator instruction rate (inst/s) +host_op_rate 107745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 306125993 # Simulator tick rate (ticks/s) +host_mem_usage 219936 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 412615955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 204823748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 617439703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 412615955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 412615955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 412615955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 204823748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 617439703 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 83600 # number of cpu cycles simulated +system.cpu.numCycles 86240 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15175 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 3684 # nu system.cpu.num_load_insts 2232 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 83600 # Number of busy cycles +system.cpu.num_busy_cycles 86240 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use +system.cpu.icache.tagsinuse 152.912665 # Cycle average of tags in use system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 153.436702 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074920 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074920 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 152.912665 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074664 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074664 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14941 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14941 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14941 # number of demand (read+write) hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.642881 # Cycle average of tags in use system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.842991 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023887 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023887 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.642881 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023839 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023839 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2173 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2173 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.636297 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.765242 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.470886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000960 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005622 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 152.238639 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.397658 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004646 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000958 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005604 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits |