diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc')
3 files changed, 544 insertions, 544 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index d7ab6a34e..60e6f3a9f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27167500 # Number of ticks simulated -final_tick 27167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27282000 # Number of ticks simulated +final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49297 # Simulator instruction rate (inst/s) -host_op_rate 49293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88314525 # Simulator tick rate (ticks/s) -host_mem_usage 232472 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host +host_inst_rate 50184 # Simulator instruction rate (inst/s) +host_op_rate 50180 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90285398 # Simulator tick rate (ticks/s) +host_mem_usage 232468 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 702015276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 325094322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1027109598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 702015276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 702015276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 702015276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 325094322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1027109598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27134000 # Total gap between requests +system.physmem.totGap 27248500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # By system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation -system.physmem.totQLat 1645750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10137000 # Sum of mem lat for all requests +system.physmem.totQLat 1525500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 6311250 # Total cycles spent in bank access -system.physmem.avgQLat 3774.66 # Average queueing delay per request -system.physmem.avgBankLat 14475.34 # Average bank access latency per request +system.physmem.totBankLat 6325000 # Total cycles spent in bank access +system.physmem.avgQLat 3498.85 # Average queueing delay per request +system.physmem.avgBankLat 14506.88 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23250.00 # Average memory access latency -system.physmem.avgRdBW 1027.11 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23005.73 # Average memory access latency +system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1027.11 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.02 # Data bus utilization in percentage +system.physmem.busUtil 7.99 # Data bus utilization in percentage system.physmem.avgRdQLen 0.37 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 62233.94 # Average gap between requests -system.membus.throughput 1024753842 # Throughput (bytes/s) +system.physmem.avgGap 62496.56 # Average gap between requests +system.membus.throughput 1020453046 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -203,7 +203,7 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4057250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.9 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted @@ -215,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54336 # number of cpu cycles simulated +system.cpu.numCycles 54565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -237,12 +237,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21896 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36768 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 32.332155 # Percentage of cycles cpu is active +system.cpu.activity 32.196463 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -254,36 +254,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.583696 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.583696 # CPI: Total CPI of All Threads -system.cpu.ipc 0.279042 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads +system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.279042 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 40910 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.709217 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44983 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.213266 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45533 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 16.201045 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 51458 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.296673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45027 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 17.132288 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.384950 # Cycle average of tags in use -system.cpu.icache.total_refs 3004 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.384950 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082219 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082219 # Average percentage of cache occupancy +system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -296,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25319500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25319500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25319500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25319500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25319500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25319500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -314,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66455.380577 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66455.380577 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66455.380577 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66455.380577 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,26 +340,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20038500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20038500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66573.089701 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66573.089701 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1029465354 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -374,21 +374,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 448500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.348050 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 167.722707 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.625344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -406,17 +406,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19715000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3728500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23443500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5878000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5878000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19715000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9606500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19715000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9606500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29321500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -439,17 +439,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.454849 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70349.056604 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66600.852273 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69152.941176 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69152.941176 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67097.254005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67097.254005 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -469,17 +469,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16042000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19118500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16042000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7917250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23959250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16042000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7917250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23959250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -491,27 +491,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53652.173913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58047.169811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54313.920455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 98.129274 # Cycle average of tags in use -system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 98.129274 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023957 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023957 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -530,14 +530,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4284500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4284500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25306500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25306500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29591000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29591000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29591000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29591000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -556,19 +556,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73870.689655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73870.689655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.009479 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.009479 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61647.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61647.916667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1016 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.882353 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.969697 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -588,14 +588,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9749000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9749000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -604,14 +604,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71377.358491 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71377.358491 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70188.235294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70188.235294 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3e2a9c814..5128d5dc2 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26399500 # Number of ticks simulated -final_tick 26399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 26524500 # Number of ticks simulated +final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93938 # Simulator instruction rate (inst/s) -host_op_rate 93929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171756334 # Simulator tick rate (ticks/s) +host_inst_rate 52714 # Simulator instruction rate (inst/s) +host_op_rate 52709 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96835127 # Simulator tick rate (ticks/s) host_mem_usage 234512 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_seconds 0.27 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812136593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 356370386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1168506979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812136593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812136593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812136593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 356370386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1168506979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 482 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26239500 # Total gap between requests +system.physmem.totGap 26363500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # By system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation -system.physmem.totQLat 1765750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10927000 # Sum of mem lat for all requests +system.physmem.totQLat 1755500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests system.physmem.totBusLat 2410000 # Total cycles spent in databus access -system.physmem.totBankLat 6751250 # Total cycles spent in bank access -system.physmem.avgQLat 3663.38 # Average queueing delay per request -system.physmem.avgBankLat 14006.74 # Average bank access latency per request +system.physmem.totBankLat 6765000 # Total cycles spent in bank access +system.physmem.avgQLat 3642.12 # Average queueing delay per request +system.physmem.avgBankLat 14035.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22670.12 # Average memory access latency -system.physmem.avgRdBW 1168.51 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22677.39 # Average memory access latency +system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1168.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.13 # Data bus utilization in percentage +system.physmem.busUtil 9.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.41 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 430 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54438.80 # Average gap between requests -system.membus.throughput 1168506979 # Throughput (bytes/s) +system.physmem.avgGap 54696.06 # Average gap between requests +system.membus.throughput 1163000245 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -200,104 +200,104 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 583000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4486500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6719 # Number of BP lookups -system.cpu.branchPred.condPredicted 4457 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5025 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2433 # Number of BTB hits +system.cpu.branchPred.lookups 6716 # Number of BP lookups +system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.417910 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 52800 # number of cpu cycles simulated +system.cpu.numCycles 53050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12414 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31130 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6719 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2877 # Number of branches that fetch has predicted taken +system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3041 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8772 # Number of cycles fetch has spent blocked +system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 994 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5381 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33187 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.938018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.130523 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24054 72.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4509 13.59% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 475 1.43% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33187 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127254 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.589583 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13016 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9761 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8340 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29004 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13656 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 501 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8734 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7953 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8344 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7952 # Number of cycles rename is running system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26651 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 23943 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49443 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49443 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49456 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10124 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3527 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2284 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21113 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33187 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.636183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.261114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23946 72.15% 72.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3557 10.72% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2326 7.01% 89.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1693 5.10% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 889 2.68% 97.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 472 1.42% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 239 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33187 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -333,113 +333,113 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15643 74.09% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15651 74.10% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2108 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21113 # Type of FU issued -system.cpu.iq.rate 0.399867 # Inst issue rate +system.cpu.iq.FU_type_0::total 21122 # Type of FU issued +system.cpu.iq.rate 0.398153 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006963 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75656 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31087 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19513 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21260 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1302 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 836 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 398 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3527 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2284 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 359 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24307 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1209 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20068 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1134 # number of nop insts executed system.cpu.iew.exec_refs 5224 # number of memory reference insts executed -system.cpu.iew.exec_branches 4238 # Number of branches executed +system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.380076 # Inst execution rate -system.cpu.iew.wb_sent 19741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19513 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9111 # num instructions producing a value -system.cpu.iew.wb_consumers 11226 # num instructions consuming a value +system.cpu.iew.exec_rate 0.378398 # Inst execution rate +system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19522 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9120 # num instructions producing a value +system.cpu.iew.wb_consumers 11235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.369564 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.811598 # average fanout of values written-back +system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1075 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484146 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.180879 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23994 76.62% 76.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4076 13.02% 89.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.44% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 350 1.12% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 272 0.87% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.03% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 115 0.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -450,24 +450,24 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54580 # The number of ROB reads -system.cpu.rob.rob_writes 50280 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19613 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54596 # The number of ROB reads +system.cpu.rob.rob_writes 50298 # The number of ROB writes +system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.657523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.657523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.273409 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.273409 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32029 # number of integer regfile reads -system.cpu.int_regfile_writes 17831 # number of integer regfile writes +system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads +system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32043 # number of integer regfile reads +system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1173355556 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -482,55 +482,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 505500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 187.819339 # Cycle average of tags in use -system.cpu.icache.total_refs 4874 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.462908 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 187.819339 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.091709 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.091709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4874 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4874 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4874 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4874 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4874 # number of overall hits -system.cpu.icache.overall_hits::total 4874 # number of overall hits +system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits +system.cpu.icache.overall_hits::total 4873 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses system.cpu.icache.overall_misses::total 507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30807500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30807500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30807500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30807500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30807500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30807500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5381 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5381 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5381 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5381 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5381 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5381 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094220 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094220 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094220 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094220 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094220 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094220 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60764.299803 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60764.299803 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60764.299803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60764.299803 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5380 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001053 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # 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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65344.776119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71742.187500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66370.927318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68746.987952 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68746.987952 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66780.082988 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66780.082988 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -683,27 +683,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52981.343284 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59523.437500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54030.701754 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56593.373494 # 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number of replacements -system.cpu.dcache.tagsinuse 98.861742 # Cycle average of tags in use -system.cpu.dcache.total_refs 4001 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.217687 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 98.861742 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024136 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024136 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -722,14 +722,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7949500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7949500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24575974 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24575974 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32525474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32525474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32525474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32525474 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -748,19 +748,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63091.269841 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63091.269841 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60087.955990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60087.955990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60795.278505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60795.278505 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -780,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5790000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5790000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10446000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -796,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69759.036145 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69759.036145 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index b595d4238..ac8c29d55 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use -system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits |