diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref')
11 files changed, 2812 insertions, 2627 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt index b23a2b88f..cdfe6dd6a 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000167 # Number of seconds simulated -sim_ticks 167328500 # Number of ticks simulated -final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 167318000 # Number of ticks simulated +final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54302 # Simulator instruction rate (inst/s) -host_op_rate 54316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79708249 # Simulator tick rate (ticks/s) -host_mem_usage 244184 # Number of bytes of host memory used -host_seconds 2.10 # Real time elapsed on the host +host_inst_rate 259842 # Simulator instruction rate (inst/s) +host_op_rate 259907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 381385356 # Simulator tick rate (ticks/s) +host_mem_usage 261864 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host sim_insts 113991 # Number of instructions simulated sim_ops 114022 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory system.physmem.bytes_read::total 69760 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 52672 # Nu system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1090 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 166995000 # Total gap between requests +system.physmem.totGap 166987000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -201,15 +201,15 @@ system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # By system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation -system.physmem.totQLat 15434500 # Total ticks spent queuing -system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 15449500 # Total ticks spent queuing +system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.26 # Data bus utilization in percentage @@ -221,59 +221,59 @@ system.physmem.readRowHits 874 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 153206.42 # Average gap between requests +system.physmem.avgGap 153199.08 # Average gap between requests system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ) -system.physmem_0.averagePower 555.501490 # Core power per rank (mW) -system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.517657 # Core power per rank (mW) +system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ) -system.physmem_1.averagePower 539.085991 # Core power per rank (mW) -system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ) +system.physmem_1.averagePower 539.101715 # Core power per rank (mW) +system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 31621 # Number of BP lookups -system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15507 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31578 # Number of BP lookups +system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15512 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 43 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 334657 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 334636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 113991 # Number of instructions committed system.cpu.committedOps 114022 # Number of ops (including micro ops) committed -system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.935819 # CPI: cycles per instruction -system.cpu.ipc 0.340620 # IPC: instructions per cycle +system.cpu.cpi 2.935635 # CPI: cycles per instruction +system.cpu.ipc 0.340642 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction @@ -344,38 +344,38 @@ system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 114022 # Class of committed instruction -system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked -system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked +system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits -system.cpu.dcache.overall_hits::total 44060 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits +system.cpu.dcache.overall_hits::total 44057 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses @@ -384,42 +384,42 @@ system.cpu.dcache.demand_misses::cpu.data 459 # n system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses system.cpu.dcache.overall_misses::total 459 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,14 +442,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 268 system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses @@ -458,68 +458,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18 # number of replacements -system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101823 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits -system.cpu.icache.overall_hits::total 49677 # number of overall hits +system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101789 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits +system.cpu.icache.overall_hits::total 49660 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses system.cpu.icache.overall_misses::total 823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,36 +534,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 823 system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id @@ -571,7 +571,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits @@ -594,16 +594,16 @@ system.cpu.l2cache.overall_misses::cpu.data 267 # system.cpu.l2cache.overall_misses::total 1090 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) @@ -632,16 +632,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -662,16 +662,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 267 system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -686,23 +686,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution @@ -740,7 +740,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 891 # Transaction distribution system.membus.trans_dist::ReadExReq 199 # Transaction distribution system.membus.trans_dist::ReadExResp 199 # Transaction distribution @@ -761,7 +761,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1090 # Request fanout histogram -system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt index 8b3036b08..0712c8493 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000796 # Nu sim_ticks 796036 # Number of ticks simulated final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 51863 # Simulator instruction rate (inst/s) -host_op_rate 51862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 623875 # Simulator tick rate (ticks/s) -host_mem_usage 411084 # Number of bytes of host memory used -host_seconds 1.28 # Real time elapsed on the host +host_inst_rate 163786 # Simulator instruction rate (inst/s) +host_op_rate 163781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1970174 # Simulator tick rate (ticks/s) +host_mem_usage 428500 # Number of bytes of host memory used +host_seconds 0.40 # Real time elapsed on the host sim_insts 66173 # Number of instructions simulated sim_ops 66173 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -401,13 +401,35 @@ system.ruby.miss_latency_hist_seqr::stdev 31.144722 system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% system.ruby.miss_latency_hist_seqr::total 14050 system.ruby.Directory.incomplete_times_seqr 14049 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999377 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.715164 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999913 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999915 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.995586 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.113609 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.070590 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999992 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999340 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.996224 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999442 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.105874 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.715264 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.823722 system.ruby.network.routers0.msg_count.Control::2 14050 @@ -418,6 +440,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 112400 system.ruby.network.routers0.msg_bytes.Data::2 1011312 system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.715189 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.998751 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999824 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.823722 system.ruby.network.routers1.msg_count.Control::2 14050 @@ -428,6 +456,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 112400 system.ruby.network.routers1.msg_bytes.Data::2 1011312 system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.715249 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.998123 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999732 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.996859 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999541 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.715212 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.997493 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999638 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.715232 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 8.823722 system.ruby.network.routers2.msg_count.Control::2 14050 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt index c2cf1b21c..042307b53 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000339 # Number of seconds simulated -sim_ticks 339160000 # Number of ticks simulated -final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 339173000 # Number of ticks simulated +final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25032 # Simulator instruction rate (inst/s) -host_op_rate 25032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28360795 # Simulator tick rate (ticks/s) -host_mem_usage 244952 # Number of bytes of host memory used -host_seconds 11.96 # Real time elapsed on the host +host_inst_rate 215547 # Simulator instruction rate (inst/s) +host_op_rate 215545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244214530 # Simulator tick rate (ticks/s) +host_mem_usage 263004 # Number of bytes of host memory used +host_seconds 1.39 # Real time elapsed on the host sim_insts 299354 # Number of instructions simulated sim_ops 299354 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory system.physmem.bytes_read::total 95040 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 74688 # Nu system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1485 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338943500 # Total gap between requests +system.physmem.totGap 338956500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation -system.physmem.totQLat 19805250 # Total ticks spent queuing -system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 20061750 # Total ticks spent queuing +system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.19 # Data bus utilization in percentage @@ -221,58 +221,58 @@ system.physmem.readRowHits 1195 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 228244.78 # Average gap between requests +system.physmem.avgGap 228253.54 # Average gap between requests system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ) -system.physmem_0.averagePower 553.629673 # Core power per rank (mW) -system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states +system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ) +system.physmem_0.averagePower 553.841711 # Core power per rank (mW) +system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ) -system.physmem_1.averagePower 537.082660 # Core power per rank (mW) -system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states +system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ) +system.physmem_1.averagePower 536.767851 # Core power per rank (mW) +system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 80709 # Number of BP lookups -system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38294 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 80662 # Number of BP lookups +system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38260 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678320 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678346 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 299354 # Number of instructions committed system.cpu.committedOps 299354 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.265946 # CPI: cycles per instruction -system.cpu.ipc 0.441317 # IPC: instructions per cycle +system.cpu.cpi 2.266033 # CPI: cycles per instruction +system.cpu.ipc 0.441300 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction @@ -344,34 +344,34 @@ system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 299354 # Class of committed instruction -system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked -system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked +system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits -system.cpu.dcache.overall_hits::total 119907 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits +system.cpu.dcache.overall_hits::total 119892 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses @@ -380,22 +380,22 @@ system.cpu.dcache.demand_misses::cpu.data 511 # n system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses @@ -404,14 +404,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,84 +432,84 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 320 system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 80 # number of replacements -system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 273696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits -system.cpu.icache.overall_hits::total 135081 # number of overall hits +system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses +system.cpu.icache.tags.data_accesses 273390 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits +system.cpu.icache.overall_hits::total 134928 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses system.cpu.icache.overall_misses::total 1178 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,36 +524,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1178 system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id @@ -561,7 +561,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits @@ -588,16 +588,16 @@ system.cpu.l2cache.overall_misses::cpu.data 318 # system.cpu.l2cache.overall_misses::total 1485 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) @@ -626,16 +626,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -656,16 +656,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 318 system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses @@ -680,23 +680,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution @@ -734,7 +734,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1283 # Transaction distribution system.membus.trans_dist::ReadExReq 202 # Transaction distribution system.membus.trans_dist::ReadExResp 202 # Transaction distribution @@ -755,9 +755,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1485 # Request fanout histogram -system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt index fef27ae57..c7042114d 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.006394 # Nu sim_ticks 6393532 # Number of ticks simulated final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 13428 # Simulator instruction rate (inst/s) -host_op_rate 13428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 286950 # Simulator tick rate (ticks/s) -host_mem_usage 412476 # Number of bytes of host memory used -host_seconds 22.28 # Real time elapsed on the host +host_inst_rate 80438 # Simulator instruction rate (inst/s) +host_op_rate 80438 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1718903 # Simulator tick rate (ticks/s) +host_mem_usage 429644 # Number of bytes of host memory used +host_seconds 3.72 # Real time elapsed on the host sim_insts 299191 # Number of instructions simulated sim_ops 299191 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,13 +403,35 @@ system.ruby.miss_latency_hist_seqr::stdev 36.989317 system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% system.ruby.miss_latency_hist_seqr::total 97760 system.ruby.Directory.incomplete_times_seqr 97759 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999944 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.755056 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999599 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.065339 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061161 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999918 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999657 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999931 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.091740 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.755068 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.645070 system.ruby.network.routers0.msg_count.Control::2 97760 @@ -420,6 +442,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 782080 system.ruby.network.routers0.msg_bytes.Data::2 7038432 system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.755059 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999887 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999978 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.645070 system.ruby.network.routers1.msg_count.Control::2 97760 @@ -430,6 +458,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 782080 system.ruby.network.routers1.msg_bytes.Data::2 7038432 system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.755066 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.999830 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999967 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.999715 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999943 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.755062 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999773 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999955 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.755064 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.645070 system.ruby.network.routers2.msg_count.Control::2 97760 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt index a1e10e23b..f8dd393b0 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000270 # Number of seconds simulated -sim_ticks 270200000 # Number of ticks simulated -final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 269998000 # Number of ticks simulated +final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24805 # Simulator instruction rate (inst/s) -host_op_rate 24804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29619482 # Simulator tick rate (ticks/s) -host_mem_usage 244928 # Number of bytes of host memory used -host_seconds 9.12 # Real time elapsed on the host +host_inst_rate 216821 # Simulator instruction rate (inst/s) +host_op_rate 216819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 258712153 # Simulator tick rate (ticks/s) +host_mem_usage 263004 # Number of bytes of host memory used +host_seconds 1.04 # Real time elapsed on the host sim_insts 226275 # Number of instructions simulated sim_ops 226275 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory system.physmem.bytes_read::total 86336 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 67072 # Nu system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1349 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 269959000 # Total gap between requests +system.physmem.totGap 269757000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation -system.physmem.totQLat 15283750 # Total ticks spent queuing -system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 15217250 # Total ticks spent queuing +system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.50 # Data bus utilization in percentage @@ -221,59 +221,59 @@ system.physmem.readRowHits 1101 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 200117.87 # Average gap between requests +system.physmem.avgGap 199968.12 # Average gap between requests system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ) -system.physmem_0.averagePower 548.697113 # Core power per rank (mW) -system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states +system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ) +system.physmem_0.averagePower 549.494877 # Core power per rank (mW) +system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ) -system.physmem_1.averagePower 540.858753 # Core power per rank (mW) -system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ) +system.physmem_1.averagePower 541.901675 # Core power per rank (mW) +system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 61485 # Number of BP lookups -system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups -system.cpu.branchPred.BTBHits 29457 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 61459 # Number of BP lookups +system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups +system.cpu.branchPred.BTBHits 29463 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 540400 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 539996 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 226275 # Number of instructions committed system.cpu.committedOps 226275 # Number of ops (including micro ops) committed -system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.388244 # CPI: cycles per instruction -system.cpu.ipc 0.418718 # IPC: instructions per cycle +system.cpu.cpi 2.386459 # CPI: cycles per instruction +system.cpu.ipc 0.419031 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction @@ -344,34 +344,34 @@ system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 226275 # Class of committed instruction -system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked -system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked +system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits -system.cpu.dcache.overall_hits::total 90015 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits +system.cpu.dcache.overall_hits::total 90016 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses @@ -380,22 +380,22 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses @@ -404,14 +404,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,84 +434,84 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 302 system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 69 # number of replacements -system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 206597 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits -system.cpu.icache.overall_hits::total 101722 # number of overall hits +system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses +system.cpu.icache.tags.data_accesses 206433 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits +system.cpu.icache.overall_hits::total 101640 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses system.cpu.icache.overall_misses::total 1051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,36 +526,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1051 system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id @@ -563,7 +563,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -590,16 +590,16 @@ system.cpu.l2cache.overall_misses::cpu.data 301 # system.cpu.l2cache.overall_misses::total 1349 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) @@ -628,16 +628,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -658,16 +658,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 301 system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses @@ -682,23 +682,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution @@ -736,7 +736,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1144 # Transaction distribution system.membus.trans_dist::ReadExReq 205 # Transaction distribution system.membus.trans_dist::ReadExResp 205 # Transaction distribution @@ -757,9 +757,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1349 # Request fanout histogram -system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt index 7007d9f9a..5fcbb579c 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000113 # Number of seconds simulated -sim_ticks 113397000 # Number of ticks simulated -final_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 113383000 # Number of ticks simulated +final_tick 113383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22733 # Simulator instruction rate (inst/s) -host_op_rate 22733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11398414 # Simulator tick rate (ticks/s) -host_mem_usage 246096 # Number of bytes of host memory used -host_seconds 9.95 # Real time elapsed on the host +host_inst_rate 167766 # Simulator instruction rate (inst/s) +host_op_rate 167765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84106882 # Simulator tick rate (ticks/s) +host_mem_usage 263760 # Number of bytes of host memory used +host_seconds 1.35 # Real time elapsed on the host sim_insts 226159 # Number of instructions simulated sim_ops 226159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65920 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory -system.physmem.bytes_read::total 85120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 85184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65920 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1030 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1330 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1330 # Number of read requests accepted +system.physmem.num_reads::total 1331 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 581392272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169902014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 751294286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 581392272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 581392272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 581392272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169902014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 751294286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1331 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1331 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 85184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 85120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 85184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,16 +46,16 @@ system.physmem.perBankRdBursts::0 174 # Pe system.physmem.perBankRdBursts::1 18 # Per bank write bursts system.physmem.perBankRdBursts::2 15 # Per bank write bursts system.physmem.perBankRdBursts::3 82 # Per bank write bursts -system.physmem.perBankRdBursts::4 195 # Per bank write bursts +system.physmem.perBankRdBursts::4 194 # Per bank write bursts system.physmem.perBankRdBursts::5 254 # Per bank write bursts system.physmem.perBankRdBursts::6 22 # Per bank write bursts system.physmem.perBankRdBursts::7 4 # Per bank write bursts system.physmem.perBankRdBursts::8 25 # Per bank write bursts system.physmem.perBankRdBursts::9 103 # Per bank write bursts -system.physmem.perBankRdBursts::10 149 # Per bank write bursts +system.physmem.perBankRdBursts::10 150 # Per bank write bursts system.physmem.perBankRdBursts::11 145 # Per bank write bursts system.physmem.perBankRdBursts::12 50 # Per bank write bursts -system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::13 52 # Per bank write bursts system.physmem.perBankRdBursts::14 14 # Per bank write bursts system.physmem.perBankRdBursts::15 29 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 113291000 # Total gap between requests +system.physmem.totGap 113277000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1330 # Read request sizes (log2) +system.physmem.readPktSize::6 1331 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,94 +187,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation -system.physmem.totQLat 16749000 # Total ticks spent queuing -system.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.641509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 252.461189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.274727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 49 23.11% 23.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43 20.28% 43.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38 17.92% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18 8.49% 69.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13 6.13% 75.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 3.77% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.83% 82.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.36% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32 15.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 212 # Bytes accessed per row activation +system.physmem.totQLat 17606250 # Total ticks spent queuing +system.physmem.totMemAccLat 42562500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6655000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13227.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31977.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 751.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 751.29 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.86 # Data bus utilization in percentage -system.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 5.87 # Data bus utilization in percentage +system.physmem.busUtilRead 5.87 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.58 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1108 # Number of row buffer hits during reads +system.physmem.readRowHits 1107 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 85181.20 # Average gap between requests -system.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem.avgGap 85106.69 # Average gap between requests +system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 771120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 390885 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5447820 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 9821100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 199200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 40147950 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1260960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ) -system.physmem_0.averagePower 587.821160 # Core power per rank (mW) -system.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 66643995 # Total energy per rank (pJ) +system.physmem_0.averagePower 587.773777 # Core power per rank (mW) +system.physmem_0.totalIdleTime 90897000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states -system.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 3282750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18328750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 88042000 # Time in different power states +system.physmem_1.actEnergy 828240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 413655 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4055520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 7853460 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 220320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 41175660 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2031360 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ) -system.physmem_1.averagePower 574.770608 # Core power per rank (mW) -system.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 65183175 # Total energy per rank (pJ) +system.physmem_1.averagePower 574.889920 # Core power per rank (mW) +system.physmem_1.totalIdleTime 95520250 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 78040 # Number of BP lookups -system.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups -system.cpu.branchPred.BTBHits 36023 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 5288750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13978500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 90301250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 78097 # Number of BP lookups +system.cpu.branchPred.condPredicted 47857 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4973 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 59652 # Number of BTB lookups +system.cpu.branchPred.BTBHits 36130 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 60.567961 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6672 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8160 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 14779 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6634 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8145 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2576 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -295,244 +295,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 226795 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 113383000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226767 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 336548 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78040 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 60631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 73708 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 336580 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78097 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42764 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 87814 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10240 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 400 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 177 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 60514 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2320 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 167219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.012810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.818543 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 90347 54.03% 54.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11793 7.05% 61.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13895 8.31% 69.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 11689 6.99% 76.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5745 3.44% 79.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6911 4.13% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2836 1.70% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4645 2.78% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19358 11.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70165 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68795 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full +system.cpu.fetch.rateDist::total 167219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344393 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.484255 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 72610 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18818 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70228 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1268 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4295 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 35338 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 921 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 310147 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2548 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4295 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 75141 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8221 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3161 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68810 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7591 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 298778 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 743 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 207984 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 389381 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 387034 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2347 # Number of floating rename lookups system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 52843 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 133 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 335 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261697 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle +system.cpu.rename.skidInsts 3092 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 62122 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43306 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1169 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 342 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 273422 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 166 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261550 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 571 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47419 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26031 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 167219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.564117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.884378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67857 40.58% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36223 21.66% 62.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23953 14.32% 76.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10828 6.48% 83.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10307 6.16% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8097 4.84% 94.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7553 4.52% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1302 0.78% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1099 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 167219 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 716 10.62% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2981 44.22% 54.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2955 43.84% 98.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 88 1.31% 99.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 159688 61.05% 61.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 170 0.06% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 59226 22.64% 84.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 40848 15.62% 99.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 727 0.28% 99.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261697 # Type of FU issued -system.cpu.iq.rate 1.153892 # Inst issue rate -system.cpu.iq.fu_busy_cnt 6752 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 261550 # Type of FU issued +system.cpu.iq.rate 1.153387 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6741 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025773 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 694940 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 318115 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249943 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2691 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2944 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1007 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266784 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1390 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5624 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6077 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 9 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4295 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4907 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 918 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 273579 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3363 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 62122 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43306 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 157 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1293 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3450 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4743 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 58349 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7506 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 98174 # number of memory reference insts executed -system.cpu.iew.exec_branches 57098 # Number of branches executed -system.cpu.iew.exec_stores 39775 # Number of stores executed -system.cpu.iew.exec_rate 1.120642 # Inst execution rate -system.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 251000 # cumulative count of insts written-back -system.cpu.iew.wb_producers 95690 # num instructions producing a value -system.cpu.iew.wb_consumers 132115 # num instructions consuming a value -system.cpu.iew.wb_rate 1.106726 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 98069 # number of memory reference insts executed +system.cpu.iew.exec_branches 57083 # Number of branches executed +system.cpu.iew.exec_stores 39720 # Number of stores executed +system.cpu.iew.exec_rate 1.120286 # Inst execution rate +system.cpu.iew.wb_sent 252158 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 250950 # cumulative count of insts written-back +system.cpu.iew.wb_producers 95653 # num instructions producing a value +system.cpu.iew.wb_consumers 131997 # num instructions consuming a value +system.cpu.iew.wb_rate 1.106643 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724660 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 47451 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4148 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158171 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.429839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.156696 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83501 52.79% 52.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25809 16.32% 69.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14383 9.09% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10997 6.95% 85.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5860 3.70% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5977 3.78% 92.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3309 2.09% 94.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1266 0.80% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7069 4.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158171 # Number of insts commited each cycle system.cpu.commit.committedInsts 226159 # Number of instructions committed system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -582,103 +582,103 @@ system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 226159 # Class of committed instruction -system.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 422850 # The number of ROB reads -system.cpu.rob.rob_writes 556608 # The number of ROB writes -system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7069 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 423217 # The number of ROB reads +system.cpu.rob.rob_writes 556357 # The number of ROB writes +system.cpu.timesIdled 459 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59548 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 226159 # Number of Instructions Simulated system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.002812 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads -system.cpu.ipc 0.997196 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 329004 # number of integer regfile reads -system.cpu.int_regfile_writes 174767 # number of integer regfile writes -system.cpu.fp_regfile_reads 880 # number of floating regfile reads -system.cpu.fp_regfile_writes 753 # number of floating regfile writes -system.cpu.misc_regfile_reads 448 # number of misc regfile reads +system.cpu.cpi 1.002688 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.002688 # CPI: Total CPI of All Threads +system.cpu.ipc 0.997319 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.997319 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 329254 # number of integer regfile reads +system.cpu.int_regfile_writes 174794 # number of integer regfile writes +system.cpu.fp_regfile_reads 878 # number of floating regfile reads +system.cpu.fp_regfile_writes 754 # number of floating regfile writes +system.cpu.misc_regfile_reads 446 # number of misc regfile reads system.cpu.misc_regfile_writes 313 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 244.658569 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 87565 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 290.913621 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 244.658569 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059731 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059731 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179361 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits -system.cpu.dcache.overall_hits::total 87597 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses -system.cpu.dcache.overall_misses::total 1933 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 179301 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179301 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51833 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 35732 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 35732 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 87565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 87565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 87565 # number of overall hits +system.cpu.dcache.overall_hits::total 87565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 438 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1497 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1497 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1935 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1935 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1935 # number of overall misses +system.cpu.dcache.overall_misses::total 1935 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36015000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36015000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 97868425 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 97868425 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133883425 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133883425 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133883425 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133883425 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52271 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52271 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 89500 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 89500 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 89500 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 89500 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008379 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008379 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040211 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040211 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021620 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021620 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021620 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021620 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82226.027397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 82226.027397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65376.369405 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65376.369405 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69190.400517 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69190.400517 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.253165 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 341 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1293 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1634 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1634 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1634 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1634 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses @@ -687,144 +687,144 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 301 system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16055500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16055500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24812500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24812500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24812500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24812500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17206500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17206500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25753000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001856 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001856 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003362 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003362 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90278.350515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90278.350515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78703.431373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78703.431373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 69 # number of replacements -system.cpu.icache.tags.tagsinuse 535.650396 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59273 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1034 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 57.323985 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003363 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003363 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88108.247423 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88108.247423 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84345.588235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84345.588235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 70 # number of replacements +system.cpu.icache.tags.tagsinuse 535.835535 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59155 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1035 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 57.154589 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 535.650396 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.261548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.261548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 535.835535 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.261638 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.261638 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 122286 # Number of tag accesses -system.cpu.icache.tags.data_accesses 122286 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 59273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59273 # number of overall hits -system.cpu.icache.overall_hits::total 59273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1353 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1353 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1353 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1353 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1353 # number of overall misses -system.cpu.icache.overall_misses::total 1353 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 109130497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 109130497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 109130497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 109130497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 109130497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 109130497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60626 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60626 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60626 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60626 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022317 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.022317 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.022317 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80658.164819 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80658.164819 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80658.164819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80658.164819 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 122053 # Number of tag accesses +system.cpu.icache.tags.data_accesses 122053 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 59155 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59155 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59155 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59155 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59155 # number of overall hits +system.cpu.icache.overall_hits::total 59155 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1354 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1354 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1354 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1354 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1354 # number of overall misses +system.cpu.icache.overall_misses::total 1354 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 109143498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 109143498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 109143498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 109143498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 109143498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 109143498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60509 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60509 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60509 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60509 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60509 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60509 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022377 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.022377 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.022377 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.022377 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.022377 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.022377 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80608.196455 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80608.196455 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80608.196455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80608.196455 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2475 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.794118 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 69 # number of writebacks -system.cpu.icache.writebacks::total 69 # number of writebacks +system.cpu.icache.writebacks::writebacks 70 # number of writebacks +system.cpu.icache.writebacks::total 70 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 319 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 319 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 319 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 319 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86838997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 86838997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86838997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 86838997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86838997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 86838997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017055 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.017055 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.017055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83983.556093 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83983.556093 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1035 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1035 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1035 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1035 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86827498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 86827498 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86827498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 86827498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86827498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 86827498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.017105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.017105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83891.302415 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83891.302415 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 808.401303 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 71 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1330 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.053383 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 808.901136 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 72 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.054095 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 563.637058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 244.764245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017201 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.024670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1330 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 879 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040588 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12538 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12538 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits +system.cpu.l2cache.tags.occ_blocks::cpu.inst 564.214692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 244.686444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017218 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.024686 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1331 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040619 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12555 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12555 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 70 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 70 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -833,66 +833,66 @@ system.cpu.l2cache.overall_hits::cpu.inst 2 # n system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 204 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 204 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1029 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1029 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1030 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1030 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 97 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 97 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1029 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1330 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1029 # number of overall misses +system.cpu.l2cache.demand_misses::total 1331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1030 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses -system.cpu.l2cache.overall_misses::total 1330 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15749000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15749000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85256500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 85256500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8611500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8611500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 85256500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24360500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 109617000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 85256500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24360500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 109617000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 1331 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85245000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 85245000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8401000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8401000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 85245000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 25301000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 110546000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 85245000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 25301000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 110546000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 70 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 70 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 204 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 204 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1031 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1031 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1032 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1032 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1031 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 301 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1332 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1031 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1333 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 301 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1333 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998060 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998060 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998062 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998062 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998062 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.998498 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998060 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.998500 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998062 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.998498 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77200.980392 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77200.980392 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82853.741497 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82853.741497 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88778.350515 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88778.350515 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82418.796992 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82418.796992 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.998500 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82843.137255 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82843.137255 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82762.135922 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82762.135922 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86608.247423 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86608.247423 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83054.845980 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83054.845980 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -901,120 +901,120 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1029 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1029 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1030 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1030 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 97 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 97 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1330 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1029 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1330 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13709000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13709000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74966500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74966500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7641500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7641500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74966500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21350500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74966500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21350500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96317000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 1331 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74945000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74945000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7431000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7431000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74945000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 97236000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74945000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 97236000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998062 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.998498 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.998500 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.998498 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67200.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67200.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72853.741497 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72853.741497 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78778.350515 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78778.350515 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.998500 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72843.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72843.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72762.135922 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72762.135922 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76608.247423 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76608.247423 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1406 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 70 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2137 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 89792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 3 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1336 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002246 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047351 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1333 99.78% 99.78% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1336 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 773000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1552500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 1331 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1126 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1127 # Transaction distribution system.membus.trans_dist::ReadExReq 204 # Transaction distribution system.membus.trans_dist::ReadExResp 204 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1127 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2662 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 85184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1330 # Request fanout histogram +system.membus.snoop_fanout::samples 1331 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1331 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1330 # Request fanout histogram -system.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1331 # Request fanout histogram +system.membus.reqLayer0.occupancy 1624000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 7014000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt index 2726406d4..8fec50473 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.004665 # Nu sim_ticks 4665394 # Number of ticks simulated final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17585 # Simulator instruction rate (inst/s) -host_op_rate 17585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 362753 # Simulator tick rate (ticks/s) -host_mem_usage 412420 # Number of bytes of host memory used -host_seconds 12.86 # Real time elapsed on the host +host_inst_rate 87650 # Simulator instruction rate (inst/s) +host_op_rate 87650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1808106 # Simulator tick rate (ticks/s) +host_mem_usage 429644 # Number of bytes of host memory used +host_seconds 2.58 # Real time elapsed on the host sim_insts 226159 # Number of instructions simulated sim_ops 226159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -402,13 +402,35 @@ system.ruby.miss_latency_hist_seqr::stdev 37.140999 system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% system.ruby.miss_latency_hist_seqr::total 72247 system.ruby.Directory.incomplete_times_seqr 72246 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999904 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.751856 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 242968 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 72247 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 315215 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999322 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.067565 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061941 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999887 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999420 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999905 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092910 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.751873 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.742647 system.ruby.network.routers0.msg_count.Control::2 72247 @@ -419,6 +441,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 577976 system.ruby.network.routers0.msg_bytes.Data::2 5201496 system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.751860 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999808 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999970 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.742647 system.ruby.network.routers1.msg_count.Control::2 72247 @@ -429,6 +457,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 577976 system.ruby.network.routers1.msg_bytes.Data::2 5201496 system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.751870 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.999712 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999954 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.999518 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999922 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.751864 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999615 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999938 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.751867 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.742647 system.ruby.network.routers2.msg_count.Control::2 72247 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt index 4aec07287..4c33c60ec 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000165 # Nu sim_ticks 165091500 # Number of ticks simulated final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30601 # Simulator instruction rate (inst/s) -host_op_rate 30601 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44574860 # Simulator tick rate (ticks/s) -host_mem_usage 244264 # Number of bytes of host memory used -host_seconds 3.70 # Real time elapsed on the host +host_inst_rate 261359 # Simulator instruction rate (inst/s) +host_op_rate 261351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 380682439 # Simulator tick rate (ticks/s) +host_mem_usage 261856 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host sim_insts 113337 # Number of instructions simulated sim_ops 113337 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # By system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation -system.physmem.totQLat 16657750 # Total ticks spent queuing -system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 16727250 # Total ticks spent queuing +system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s @@ -229,19 +229,19 @@ system.physmem_0.readEnergy 3348660 # En system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ) -system.physmem_0.averagePower 555.739358 # Core power per rank (mW) +system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.750261 # Core power per rank (mW) system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ) @@ -249,31 +249,31 @@ system.physmem_1.writeEnergy 0 # En system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ) -system.physmem_1.averagePower 547.349607 # Core power per rank (mW) +system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ) +system.physmem_1.averagePower 547.351788 # Core power per rank (mW) system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 31704 # Number of BP lookups -system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15332 # Number of BTB hits +system.cpu.branchPred.lookups 31695 # Number of BP lookups +system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15330 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -301,7 +301,7 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 113337 # Number of instructions committed system.cpu.committedOps 113337 # Number of ops (including micro ops) committed -system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 2.913285 # CPI: cycles per instruction system.cpu.ipc 0.343255 # IPC: instructions per cycle @@ -344,16 +344,16 @@ system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 113337 # Class of committed instruction -system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked +system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id @@ -361,17 +361,17 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits -system.cpu.dcache.overall_hits::total 43868 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits +system.cpu.dcache.overall_hits::total 43871 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses @@ -380,38 +380,38 @@ system.cpu.dcache.demand_misses::cpu.data 453 # n system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses system.cpu.dcache.overall_misses::total 453 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,14 +434,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 263 system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses @@ -450,68 +450,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 14 # number of replacements -system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101777 # Number of data accesses +system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101683 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits -system.cpu.icache.overall_hits::total 49717 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits +system.cpu.icache.overall_hits::total 49670 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses system.cpu.icache.overall_misses::total 781 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015466 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015466 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015466 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015466 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87673.495519 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 87673.495519 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 87673.495519 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 87673.495519 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,33 +526,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 781 system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67692000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015466 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015466 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015466 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86673.495519 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86673.495519 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 603.610931 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.574887 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036044 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy @@ -586,16 +586,16 @@ system.cpu.l2cache.overall_misses::cpu.data 262 # system.cpu.l2cache.overall_misses::total 1043 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66520500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 66520500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7011500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7011500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 66520500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22831500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 89352000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 66520500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22831500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 89352000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses) @@ -624,16 +624,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198 system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85173.495519 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85173.495519 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109554.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109554.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85668.264621 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -654,16 +654,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 262 system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58710500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58710500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6371500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6371500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58710500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20211500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78922000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58710500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20211500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78922000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -678,16 +678,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198 system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75173.495519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75173.495519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99554.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99554.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -753,9 +753,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1043 # Request fanout histogram -system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt index 0be26640f..0c1b30ad6 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000067 # Number of seconds simulated -sim_ticks 66726000 # Number of ticks simulated -final_tick 66726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 66743000 # Number of ticks simulated +final_tick 66743000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30660 # Simulator instruction rate (inst/s) -host_op_rate 30660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18058105 # Simulator tick rate (ticks/s) -host_mem_usage 245440 # Number of bytes of host memory used -host_seconds 3.70 # Real time elapsed on the host +host_inst_rate 234636 # Simulator instruction rate (inst/s) +host_op_rate 234630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 138224430 # Simulator tick rate (ticks/s) +host_mem_usage 263644 # Number of bytes of host memory used +host_seconds 0.48 # Real time elapsed on the host sim_insts 113291 # Number of instructions simulated sim_ops 113291 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory -system.physmem.bytes_read::total 66432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 66368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 772 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1038 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 741420136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 254173785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 995593921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 741420136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 741420136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 741420136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 254173785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 995593921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1039 # Number of read requests accepted +system.physmem.num_reads::total 1037 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 740272388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 254109045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 994381433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 740272388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 740272388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 740272388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 254109045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 994381433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1038 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1039 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1038 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 66496 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 66432 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 66496 # Total read bytes from the system interface side +system.physmem.bytesReadSys 66432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::0 89 # Pe system.physmem.perBankRdBursts::1 8 # Per bank write bursts system.physmem.perBankRdBursts::2 16 # Per bank write bursts system.physmem.perBankRdBursts::3 108 # Per bank write bursts -system.physmem.perBankRdBursts::4 64 # Per bank write bursts +system.physmem.perBankRdBursts::4 63 # Per bank write bursts system.physmem.perBankRdBursts::5 91 # Per bank write bursts system.physmem.perBankRdBursts::6 61 # Per bank write bursts system.physmem.perBankRdBursts::7 30 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 66707000 # Total gap between requests +system.physmem.totGap 66724000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1039 # Read request sizes (log2) +system.physmem.readPktSize::6 1038 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 579 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,94 +187,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.131707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.178317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.046077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 71 34.63% 34.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 47 22.93% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 29 14.15% 71.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 5.37% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 11 5.37% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 2.93% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.46% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 2.44% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22 10.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 205 # Bytes accessed per row activation -system.physmem.totQLat 13576000 # Total ticks spent queuing -system.physmem.totMemAccLat 33057250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13066.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.407960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.437814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 320.986499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 66 32.84% 32.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 49 24.38% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 13.93% 71.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 5.47% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 11 5.47% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 2.99% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.49% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.49% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22 10.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 201 # Bytes accessed per row activation +system.physmem.totQLat 13663500 # Total ticks spent queuing +system.physmem.totMemAccLat 33126000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5190000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13163.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31816.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 996.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31913.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 995.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 996.55 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 995.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.79 # Data bus utilization in percentage -system.physmem.busUtilRead 7.79 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.78 # Data bus utilization in percentage +system.physmem.busUtilRead 7.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 821 # Number of row buffer hits during reads +system.physmem.readRowHits 824 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 64203.08 # Average gap between requests -system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 413655 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3334380 # Energy for read commands per rank (pJ) +system.physmem.avgGap 64281.31 # Average gap between requests +system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 821100 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 406065 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3327240 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6568110 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 113280 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 22288140 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1209600 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 6538470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 110400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 22321770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1215840 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 39679665 # Total energy per rank (pJ) -system.physmem_0.averagePower 594.663495 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51714500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 59500 # Time in different power states +system.physmem_0.totalEnergy 39658005 # Total energy per rank (pJ) +system.physmem_0.averagePower 594.183051 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51789750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 53500 # Time in different power states system.physmem_0.memoryStateTime::REF 2080000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3148750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 12569500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 48868250 # Time in different power states -system.physmem_1.actEnergy 721140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 364320 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 3164000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 12517250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 48928250 # Time in different power states +system.physmem_1.actEnergy 706860 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 356730 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4084080 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6353220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 143040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 20623170 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 2762880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 6307620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 140640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 21247890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2284320 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 39968970 # Total energy per rank (pJ) -system.physmem_1.averagePower 598.999194 # Core power per rank (mW) -system.physmem_1.totalIdleTime 52416000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 150500 # Time in different power states +system.physmem_1.totalEnergy 40045260 # Total energy per rank (pJ) +system.physmem_1.averagePower 599.985167 # Core power per rank (mW) +system.physmem_1.totalIdleTime 52550750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 144500 # Time in different power states system.physmem_1.memoryStateTime::REF 2080000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 7195250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12079500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 45220750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 39966 # Number of BP lookups -system.cpu.branchPred.condPredicted 24999 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2671 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 33955 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19441 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 5948000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 11967750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 46602750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40127 # Number of BP lookups +system.cpu.branchPred.condPredicted 25071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 34324 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19560 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 57.255191 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 56.986365 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7662 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3924 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3738 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1190 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 7732 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3910 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3822 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1192 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -295,243 +295,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 45 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 66726000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 133453 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 66743000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 133487 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 32838 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 168786 # Number of instructions fetch has processed -system.cpu.fetch.Branches 39966 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23365 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 44071 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5482 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22322 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.101053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.833149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 32821 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 168943 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40127 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23470 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 44129 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5494 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1272 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.102406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.833567 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 43916 54.67% 54.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3396 4.23% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6102 7.60% 66.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5424 6.75% 73.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2470 3.07% 76.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6562 8.17% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1937 2.41% 86.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1614 2.01% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8913 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 43897 54.63% 54.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3425 4.26% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6099 7.59% 66.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5421 6.75% 73.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2445 3.04% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6593 8.20% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1925 2.40% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1654 2.06% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8898 11.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299476 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.264760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33037 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11879 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 80357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.300606 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.265614 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33044 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11875 # Number of cycles decode is blocked system.cpu.decode.RunCycles 32363 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 923 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2132 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6308 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 640 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 154953 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1928 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2132 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34625 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3379 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1413 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7186 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 148471 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 97 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 431 # Number of times rename has blocked due to LQ full +system.cpu.decode.UnblockCycles 936 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2139 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 19097 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 639 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 154927 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1938 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2139 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34647 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3538 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1406 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31612 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7015 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 148450 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 267 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 6512 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 101480 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 195404 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 195404 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 101534 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 195335 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 195335 # Number of integer rename lookups system.cpu.rename.CommittedMaps 76188 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 25292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 58 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 58 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3325 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 28879 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22638 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 630 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 25346 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 57 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3248 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29003 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22614 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 628 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 137222 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 131068 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 381 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23997 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13432 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.631538 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.013515 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 137191 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 60 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 131006 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 401 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.630300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.012996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 38041 47.35% 47.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10252 12.76% 60.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8094 10.08% 70.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8074 10.05% 80.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5916 7.36% 87.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4749 5.91% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3775 4.70% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1117 1.39% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 316 0.39% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 38076 47.38% 47.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10267 12.78% 60.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8067 10.04% 70.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8077 10.05% 80.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5915 7.36% 87.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4760 5.92% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3768 4.69% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1110 1.38% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 317 0.39% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80357 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 175 6.09% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1363 47.43% 53.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1336 46.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 179 6.20% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1370 47.45% 53.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1338 46.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 45 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 81693 62.33% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27948 21.32% 83.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21223 16.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 81559 62.26% 62.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27992 21.37% 83.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21251 16.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 131068 # Type of FU issued -system.cpu.iq.rate 0.982129 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2874 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021928 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 345725 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 161326 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 125053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 131006 # Type of FU issued +system.cpu.iq.rate 0.981414 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2887 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022037 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 345657 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 161246 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 125018 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133897 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 133848 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2531 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 2541 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5099 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 5223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2926 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 2902 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 101 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2132 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2287 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 246 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 137289 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 950 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 28879 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22638 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 2139 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2305 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 218 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 137249 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 965 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29003 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22614 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 58 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 224 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1893 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2391 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 126811 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 27146 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4257 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 1896 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2394 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 126750 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 27173 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4256 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 47872 # number of memory reference insts executed -system.cpu.iew.exec_branches 29089 # Number of branches executed -system.cpu.iew.exec_stores 20726 # Number of stores executed -system.cpu.iew.exec_rate 0.950230 # Inst execution rate -system.cpu.iew.wb_sent 125714 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 125053 # cumulative count of insts written-back -system.cpu.iew.wb_producers 49299 # num instructions producing a value -system.cpu.iew.wb_consumers 72928 # num instructions consuming a value -system.cpu.iew.wb_rate 0.937056 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675996 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 24018 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 47912 # number of memory reference insts executed +system.cpu.iew.exec_branches 29064 # Number of branches executed +system.cpu.iew.exec_stores 20739 # Number of stores executed +system.cpu.iew.exec_rate 0.949531 # Inst execution rate +system.cpu.iew.wb_sent 125653 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 125018 # cumulative count of insts written-back +system.cpu.iew.wb_producers 49237 # num instructions producing a value +system.cpu.iew.wb_consumers 72853 # num instructions consuming a value +system.cpu.iew.wb_rate 0.936556 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675840 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 23968 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 75915 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.492340 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.298348 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2069 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 75913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.492379 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.297345 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42174 55.55% 55.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10802 14.23% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5429 7.15% 76.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4052 5.34% 82.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3273 4.31% 86.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3050 4.02% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2519 3.32% 93.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 909 1.20% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3707 4.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42174 55.56% 55.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10790 14.21% 69.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5413 7.13% 76.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4064 5.35% 82.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3292 4.34% 86.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3056 4.03% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2525 3.33% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 907 1.19% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3692 4.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 75915 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 75913 # Number of insts commited each cycle system.cpu.commit.committedInsts 113291 # Number of instructions committed system.cpu.commit.committedOps 113291 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -581,98 +581,98 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 113291 # Class of committed instruction -system.cpu.commit.bw_lim_events 3707 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 208932 # The number of ROB reads -system.cpu.rob.rob_writes 279096 # The number of ROB writes -system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3692 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 208895 # The number of ROB reads +system.cpu.rob.rob_writes 279024 # The number of ROB writes +system.cpu.timesIdled 415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53130 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 113291 # Number of Instructions Simulated system.cpu.committedOps 113291 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.177966 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.177966 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848921 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848921 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 166154 # number of integer regfile reads -system.cpu.int_regfile_writes 85972 # number of integer regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.cpi 1.178267 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178267 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848704 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848704 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 166268 # number of integer regfile reads +system.cpu.int_regfile_writes 85929 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 217.973737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42393 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 217.985310 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42417 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 265 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 159.973585 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 160.064151 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 217.973737 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.053216 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.053216 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 217.985310 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.053219 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.053219 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.064697 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88473 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88473 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24147 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24147 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 88517 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88517 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24171 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24171 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18246 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18246 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 42393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42393 # number of overall hits -system.cpu.dcache.overall_hits::total 42393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 245 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 245 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42417 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42417 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42417 # number of overall hits +system.cpu.dcache.overall_hits::total 42417 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 243 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 243 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1466 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1466 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1711 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1711 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1711 # number of overall misses -system.cpu.dcache.overall_misses::total 1711 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20376500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20376500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95969940 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95969940 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 116346440 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 116346440 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 116346440 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 116346440 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24392 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1709 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1709 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1709 # number of overall misses +system.cpu.dcache.overall_misses::total 1709 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20232000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20232000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95961940 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95961940 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 116193940 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 116193940 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 116193940 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 116193940 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24414 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44104 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44104 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010044 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 44126 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44126 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44126 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44126 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009953 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009953 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.074371 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.074371 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038795 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038795 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038795 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038795 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83169.387755 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 83169.387755 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65463.806276 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65463.806276 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67999.088252 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67999.088252 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.038730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038730 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038730 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83259.259259 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83259.259259 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65458.349250 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65458.349250 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67989.432417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67989.432417 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.714286 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 175 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 173 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1269 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1269 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1444 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1444 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1444 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1444 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1442 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1442 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1442 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1442 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses @@ -681,88 +681,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 267 system.cpu.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6394500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6394500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15710500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15710500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22105000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22105000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22100500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22100500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22100500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22100500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002867 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002867 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009994 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009994 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006054 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006054 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006054 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006054 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79748.730964 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79748.730964 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82790.262172 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82790.262172 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82790.262172 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82790.262172 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006051 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006051 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91307.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91307.142857 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79741.116751 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79741.116751 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82773.408240 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82773.408240 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82773.408240 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82773.408240 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 16 # number of replacements -system.cpu.icache.tags.tagsinuse 390.097209 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21273 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27.449032 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 390.093191 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21217 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 773 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27.447607 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 390.097209 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.190477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.190477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 759 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 390.093191 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.190475 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.190475 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 757 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 680 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.370605 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45403 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45403 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 21273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21273 # number of overall hits -system.cpu.icache.overall_hits::total 21273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1041 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1041 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1041 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1041 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1041 # number of overall misses -system.cpu.icache.overall_misses::total 1041 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81501497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81501497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81501497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81501497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81501497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81501497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22314 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22314 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22314 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22314 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22314 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22314 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046652 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.046652 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.046652 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.046652 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.046652 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.046652 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78291.543708 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78291.543708 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78291.543708 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78291.543708 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2316 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.369629 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45285 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45285 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 21217 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21217 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 21217 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21217 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 21217 # number of overall hits +system.cpu.icache.overall_hits::total 21217 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses +system.cpu.icache.overall_misses::total 1039 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81350998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81350998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81350998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81350998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81350998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81350998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22256 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22256 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22256 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22256 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046684 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.046684 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.046684 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.046684 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.046684 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.046684 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78297.399423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78297.399423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78297.399423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78297.399423 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 36 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 67.783784 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 16 # number of writebacks system.cpu.icache.writebacks::total 16 # number of writebacks @@ -772,89 +772,89 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 266 system.cpu.icache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 266 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 266 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65524999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65524999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65524999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65524999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65524999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65524999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 773 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 773 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 773 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65540000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65540000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.034732 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.034732 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.034732 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84548.385806 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84548.385806 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84548.385806 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84548.385806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84548.385806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84548.385806 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84786.545925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84786.545925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84786.545925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84786.545925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84786.545925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84786.545925 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 612.345284 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 612.540827 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1038 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.015414 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1037 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.015429 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 394.329847 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 218.015437 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012034 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006653 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.018687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1038 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 394.513827 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 218.027000 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012040 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006654 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.018693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1037 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 951 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031677 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 9486 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 9486 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031647 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 9477 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 9477 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_misses::cpu.data 197 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 197 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 773 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 773 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 772 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 772 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 70 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 70 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 773 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1040 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 773 # number of overall misses +system.cpu.l2cache.demand_misses::total 1039 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses -system.cpu.l2cache.overall_misses::total 1040 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15415000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15415000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 64356500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 64356500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6291000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6291000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 64356500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21706000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 86062500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64356500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21706000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 86062500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 1039 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15413500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15413500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 64376500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 64376500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6288000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6288000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 64376500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 21701500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 86078000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 64376500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 21701500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 86078000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 197 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 773 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 773 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 772 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 772 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 70 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 70 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 773 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 772 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 267 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1040 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 773 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1039 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 772 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 267 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1040 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1039 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses @@ -867,18 +867,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78248.730964 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78248.730964 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83255.498060 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83255.498060 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89871.428571 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89871.428571 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82752.403846 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82752.403846 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78241.116751 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78241.116751 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83389.248705 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83389.248705 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89828.571429 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89828.571429 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82846.968239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82846.968239 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -887,28 +887,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 197 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 772 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 772 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 70 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 70 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1039 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1040 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13445000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13445000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 56626500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 56626500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5611000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5611000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56626500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19056000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 75682500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56626500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19056000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 75682500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 1039 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13443500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13443500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 56656500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 56656500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5608000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5608000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56656500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19051500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 75708000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56656500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19051500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 75708000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -921,86 +921,86 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68248.730964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68248.730964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73255.498060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73255.498060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80157.142857 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80157.142857 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 18 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68241.116751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68241.116751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73389.248705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73389.248705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80114.285714 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80114.285714 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1056 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 843 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 841 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 773 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 70 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1561 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2096 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2093 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50432 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 67456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1042 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001919 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043790 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 67392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1040 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000962 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031009 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1040 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1039 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1042 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 545000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1040 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 544000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1162500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1159500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 397500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1039 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 1038 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 841 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 840 # Transaction distribution system.membus.trans_dist::ReadExReq 197 # Transaction distribution system.membus.trans_dist::ReadExResp 197 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 842 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2077 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2077 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 841 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2075 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2075 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 66368 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1039 # Request fanout histogram +system.membus.snoop_fanout::samples 1038 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1039 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1038 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1039 # Request fanout histogram -system.membus.reqLayer0.occupancy 1253500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1038 # Request fanout histogram +system.membus.reqLayer0.occupancy 1251500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 5477500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5471250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 8.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt index bf416790e..72cb05f08 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.001842 # Nu sim_ticks 1841805 # Number of ticks simulated final_tick 1841805 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30529 # Simulator instruction rate (inst/s) -host_op_rate 30529 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 496310 # Simulator tick rate (ticks/s) -host_mem_usage 411128 # Number of bytes of host memory used -host_seconds 3.71 # Real time elapsed on the host +host_inst_rate 106701 # Simulator instruction rate (inst/s) +host_op_rate 106700 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1734637 # Simulator tick rate (ticks/s) +host_mem_usage 428500 # Number of bytes of host memory used +host_seconds 1.06 # Real time elapsed on the host sim_insts 113291 # Number of instructions simulated sim_ops 113291 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -402,13 +402,35 @@ system.ruby.miss_latency_hist_seqr::stdev 34.809845 system.ruby.miss_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% system.ruby.miss_latency_hist_seqr::total 29717 system.ruby.Directory.incomplete_times_seqr 29716 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999752 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.740878 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 127112 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 29717 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 156829 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.998244 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.085150 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.064534 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999715 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.998498 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999759 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.096797 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.740922 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.066815 system.ruby.network.routers0.msg_count.Control::2 29717 @@ -419,6 +441,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 237736 system.ruby.network.routers0.msg_bytes.Data::2 2139336 system.ruby.network.routers0.msg_bytes.Response_Data::4 2139624 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.740889 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999504 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999924 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.066815 system.ruby.network.routers1.msg_count.Control::2 29717 @@ -429,6 +457,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 237736 system.ruby.network.routers1.msg_bytes.Data::2 2139336 system.ruby.network.routers1.msg_bytes.Response_Data::4 2139624 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.740915 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.999254 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999884 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.998751 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999802 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.740899 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999003 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999844 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.740908 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 8.066815 system.ruby.network.routers2.msg_count.Control::2 29717 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 4050dbfe4..2de808a88 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29908500 # Number of ticks simulated -final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29673500 # Number of ticks simulated +final_tick 29673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19226 # Simulator instruction rate (inst/s) -host_op_rate 19225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39829510 # Simulator tick rate (ticks/s) -host_mem_usage 234412 # Number of bytes of host memory used -host_seconds 0.75 # Real time elapsed on the host +host_inst_rate 97740 # Simulator instruction rate (inst/s) +host_op_rate 97731 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 200871294 # Simulator tick rate (ticks/s) +host_mem_usage 251556 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23360 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 365 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 32640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 512 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 781048866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 314559406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1095608272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 781048866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 781048866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 781048866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 314559406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1095608272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 513 # Number of read requests accepted +system.physmem.num_reads::total 510 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 782920788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317050567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1099971355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 782920788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 782920788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 782920788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317050567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1099971355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 511 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 513 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32832 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32832 # Total read bytes from the system interface side +system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 105 # Per bank write bursts +system.physmem.perBankRdBursts::0 104 # Per bank write bursts system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 55 # Per bank write bursts -system.physmem.perBankRdBursts::3 27 # Per bank write bursts -system.physmem.perBankRdBursts::4 23 # Per bank write bursts +system.physmem.perBankRdBursts::2 54 # Per bank write bursts +system.physmem.perBankRdBursts::3 28 # Per bank write bursts +system.physmem.perBankRdBursts::4 22 # Per bank write bursts system.physmem.perBankRdBursts::5 0 # Per bank write bursts system.physmem.perBankRdBursts::6 32 # Per bank write bursts system.physmem.perBankRdBursts::7 38 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29877000 # Total gap between requests +system.physmem.totGap 29642000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 513 # Read request sizes (log2) +system.physmem.readPktSize::6 511 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,11 +92,11 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -188,328 +188,329 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 253.933476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.475070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.025641 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 252.718123 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.605052 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 24.36% 46.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 6719500 # Total ticks spent queuing -system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst +system.physmem.totQLat 6610250 # Total ticks spent queuing +system.physmem.totMemAccLat 16191500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12935.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31685.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1102.13 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1102.13 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.58 # Data bus utilization in percentage -system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.61 # Data bus utilization in percentage +system.physmem.busUtilRead 8.61 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 424 # Number of row buffer hits during reads +system.physmem.readRowHits 422 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 58239.77 # Average gap between requests -system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) +system.physmem.avgGap 58007.83 # Average gap between requests +system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 364140 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2184840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3606960 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 9847320 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) -system.physmem_0.averagePower 608.449701 # Core power per rank (mW) -system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 18086550 # Total energy per rank (pJ) +system.physmem_0.averagePower 609.513459 # Core power per rank (mW) +system.physmem_0.totalIdleTime 21469250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states -system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7251250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 21598000 # Time in different power states +system.physmem_1.actEnergy 271320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 2504580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 86400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10184760 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 622560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) -system.physmem_1.averagePower 576.319973 # Core power per rank (mW) -system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 17098680 # Total energy per rank (pJ) +system.physmem_1.averagePower 576.222419 # Core power per rank (mW) +system.physmem_1.totalIdleTime 23952750 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1286000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4831250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22868250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 12304 # Number of BP lookups -system.cpu.branchPred.condPredicted 7429 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1435 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9156 # Number of BTB lookups +system.physmem_1.memoryStateTime::PRE_PDN 1619750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4797750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22333000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11901 # Number of BP lookups +system.cpu.branchPred.condPredicted 7287 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1354 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9352 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 730 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 685 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9156 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1824 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7332 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 865 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 9352 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1949 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7403 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 793 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29908500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59818 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 29673500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 59348 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15502 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 57440 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12304 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2554 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17524 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3065 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1117 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15163 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 55604 # Number of instructions fetch has processed +system.cpu.fetch.Branches 11901 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2634 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 17364 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2905 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 12 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1168 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7446 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 730 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 35692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.609324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.874327 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 7191 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 701 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 35180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.580557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.839184 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23194 64.98% 64.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4479 12.55% 77.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 496 1.39% 78.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 441 1.24% 80.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.13% 82.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 680 1.91% 84.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 284 0.80% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 358 1.00% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4999 14.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22867 65.00% 65.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4490 12.76% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 508 1.44% 79.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 450 1.28% 80.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 761 2.16% 82.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 731 2.08% 84.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 296 0.84% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 343 0.97% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4734 13.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.205691 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.960246 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12333 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13299 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7732 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1532 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 41071 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1532 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13082 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2036 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9748 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7750 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1544 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 36233 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 35180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.200529 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.936914 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13233 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7639 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 762 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1452 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 39805 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1452 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 12828 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9904 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7640 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1543 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 35279 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 31392 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 65112 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 53717 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 30611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 63420 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 52396 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17573 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 793 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 16792 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 761 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 767 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4154 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 4391 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 27854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 724 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 24627 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14142 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10452 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 35180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.700028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.493682 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 35180 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164 53.07% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51 17.59% 69.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88 30.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18085 73.44% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 4096 16.63% 90.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2446 9.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 25030 # Type of FU issued -system.cpu.iq.rate 0.418436 # Inst issue rate -system.cpu.iq.fu_busy_cnt 309 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 24627 # Type of FU issued +system.cpu.iq.rate 0.414959 # Inst issue rate +system.cpu.iq.fu_busy_cnt 290 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011776 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 84846 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 42748 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 22066 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 24917 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 2166 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1355 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1532 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2073 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 30726 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1452 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1841 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 30085 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 231 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4391 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 724 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 209 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23080 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3816 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1547 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1532 # number of nop insts executed -system.cpu.iew.exec_refs 6190 # number of memory reference insts executed -system.cpu.iew.exec_branches 4984 # Number of branches executed -system.cpu.iew.exec_stores 2308 # Number of stores executed -system.cpu.iew.exec_rate 0.391722 # Inst execution rate -system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22369 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10409 # num instructions producing a value -system.cpu.iew.wb_consumers 13648 # num instructions consuming a value -system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1507 # number of nop insts executed +system.cpu.iew.exec_refs 6070 # number of memory reference insts executed +system.cpu.iew.exec_branches 4884 # Number of branches executed +system.cpu.iew.exec_stores 2254 # Number of stores executed +system.cpu.iew.exec_rate 0.388893 # Inst execution rate +system.cpu.iew.wb_sent 22529 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22066 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10367 # num instructions producing a value +system.cpu.iew.wb_consumers 13651 # num instructions consuming a value +system.cpu.iew.wb_rate 0.371807 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.759432 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14855 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1354 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 32262 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.469965 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.260994 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3555 10.90% 90.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1191 3.65% 94.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 577 1.77% 95.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 319 0.98% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 311 0.95% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 392 1.20% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 57 0.17% 99.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 239 0.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25609 79.38% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3577 11.09% 90.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1157 3.59% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 603 1.87% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 332 1.03% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 298 0.92% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 393 1.22% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 58 0.18% 99.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 235 0.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 32262 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,104 +560,104 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 239 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 62190 # The number of ROB reads -system.cpu.rob.rob_writes 64431 # The number of ROB writes +system.cpu.commit.bw_lim_events 235 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 61221 # The number of ROB reads +system.cpu.rob.rob_writes 63021 # The number of ROB writes system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 24168 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads -system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36473 # number of integer regfile reads -system.cpu.int_regfile_writes 20293 # number of integer regfile writes -system.cpu.misc_regfile_reads 8093 # number of misc regfile reads +system.cpu.cpi 4.111111 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.111111 # CPI: Total CPI of All Threads +system.cpu.ipc 0.243243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.243243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 36173 # number of integer regfile reads +system.cpu.int_regfile_writes 20126 # number of integer regfile writes +system.cpu.misc_regfile_reads 7956 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 98.931439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4528 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.013699 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.931439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024153 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024153 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3540 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 10292 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10292 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 3489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3489 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4573 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4573 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4573 # number of overall hits -system.cpu.dcache.overall_hits::total 4573 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 145 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 145 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4522 # number of overall hits +system.cpu.dcache.overall_hits::total 4522 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 554 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 554 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 554 # number of overall misses -system.cpu.dcache.overall_misses::total 554 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11443500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11443500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29003985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29003985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40447485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40447485 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40447485 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40447485 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3685 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3685 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 545 # number of overall misses +system.cpu.dcache.overall_misses::total 545 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10734500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10734500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29028485 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29028485 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39762985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39762985 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39762985 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39762985 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5127 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5127 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5127 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5127 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.039349 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5067 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5067 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5067 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5067 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037517 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037517 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.108055 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.108055 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.108055 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.108055 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73009.900722 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73009.900722 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.107559 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.107559 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.107559 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.107559 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78930.147059 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78930.147059 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70974.290954 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70974.290954 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72959.605505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72959.605505 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 406 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 406 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 406 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 397 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 397 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 397 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 397 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -665,138 +666,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6888000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6888000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12966000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12966000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12966000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12966000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017639 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12986500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12986500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12986500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12986500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017931 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017931 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93538.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93538.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83210.843373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83210.843373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 202.053622 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6606 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.098630 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses -system.cpu.icache.tags.data_accesses 15259 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits -system.cpu.icache.overall_hits::total 6856 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses -system.cpu.icache.overall_misses::total 590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 202.053622 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.098659 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.098659 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 14747 # Number of tag accesses +system.cpu.icache.tags.data_accesses 14747 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 6606 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6606 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6606 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6606 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6606 # number of overall hits +system.cpu.icache.overall_hits::total 6606 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 585 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 585 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 585 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 585 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 585 # number of overall misses +system.cpu.icache.overall_misses::total 585 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45161000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45161000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45161000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45161000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45161000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45161000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 7191 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7191 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 7191 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7191 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 7191 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7191 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081352 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081352 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081352 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081352 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081352 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77198.290598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77198.290598 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77198.290598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77198.290598 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 367 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30255500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30255500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30255500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30255500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30255500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30255500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 220 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 220 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 220 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 220 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29981500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29981500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29981500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29981500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29981500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29981500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050758 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050758 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050758 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82141.095890 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82141.095890 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 303.310888 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 300.398022 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.103605 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 99.207284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4631 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 201.414921 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 98.983101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006147 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.009167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -805,64 +806,64 @@ system.cpu.l2cache.overall_hits::cpu.inst 2 # n system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 365 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 365 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 513 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses -system.cpu.l2cache.overall_misses::total 513 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12745500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 42427500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29682000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12745500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 42427500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 511 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6781000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6781000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29411000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 29411000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5985000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5985000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 29411000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12766000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 42177000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 29411000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12766000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 42177000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 367 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 367 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 367 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 515 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 367 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 515 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994550 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994550 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81698.795181 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81698.795181 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81022.038567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81022.038567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92076.923077 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92076.923077 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82538.160470 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82538.160470 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -871,119 +872,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 365 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 365 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 515 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003883 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062257 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 513 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 515 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 257500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 428 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 513 # Request fanout histogram +system.membus.snoop_fanout::samples 511 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 513 # Request fanout histogram -system.membus.reqLayer0.occupancy 627500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 511 # Request fanout histogram +system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2707250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2697250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |