diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref')
16 files changed, 2200 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini new file mode 100644 index 000000000..7db48bf0e --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -0,0 +1,240 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=InOrderCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +activity=0 +cachePorts=2 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +cpu_id=0 +dataMemPort=dcache_port +defer_registration=false +div16Latency=1 +div16RepeatRate=1 +div24Latency=1 +div24RepeatRate=1 +div32Latency=1 +div32RepeatRate=1 +div8Latency=1 +div8RepeatRate=1 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchBuffSize=4 +fetchMemPort=icache_port +functionTrace=false +functionTraceStart=0 +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +memBlockSize=64 +multLatency=1 +multRepeatRate=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +stageTracing=false +stageWidth=4 +system=system +threadModel=SMT +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout new file mode 100755 index 000000000..38fdee473 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:02:00 +gem5 started Jan 23 2012 04:24:21 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 25058500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt new file mode 100644 index 000000000..7b0904682 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -0,0 +1,279 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25058500 # Number of ticks simulated +final_tick 25058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 55020 # Simulator instruction rate (inst/s) +host_tick_rate 90849063 # Simulator tick rate (ticks/s) +host_mem_usage 212976 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host +sim_insts 15175 # Number of instructions simulated +system.physmem.bytes_read 27904 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19072 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 436 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 1113554283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 761099028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1113554283 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 50118 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 21993 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32493 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17625 # Number of cycles cpu stages are processed. +system.cpu.activity 35.167006 # Percentage of cycles cpu is active +system.cpu.comLoads 2226 # Number of Load instructions committed +system.cpu.comStores 1448 # Number of Store instructions committed +system.cpu.comBranches 3359 # Number of Branches instructions committed +system.cpu.comNops 726 # Number of Nop instructions committed +system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed +system.cpu.comInts 7177 # Number of Integer instructions committed +system.cpu.comFloats 0 # Number of Floating Point instructions committed +system.cpu.committedInsts 15175 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 15175 # Number of Instructions Simulated (Total) +system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads +system.cpu.ipc 0.302785 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.302785 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 5166 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3601 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2377 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 4346 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2912 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 172 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 67.004142 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 3084 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2082 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14334 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25445 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 5192 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3845 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1598 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 716 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2314 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 1045 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 68.889550 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11051 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 36528 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13590 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 27.116006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40773 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9345 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.645995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41295 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8823 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.604453 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47234 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 5.754420 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40795 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9323 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.602099 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 165.645515 # Cycle average of tags in use +system.cpu.icache.total_refs 3085 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 165.645515 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.080882 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3085 # number of ReadReq hits +system.cpu.icache.demand_hits 3085 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3085 # number of overall hits +system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses +system.cpu.icache.demand_misses 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 20100000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 20100000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 20100000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 3451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 3451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 3451 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.106056 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.106056 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.106056 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54918.032787 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54918.032787 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54918.032787 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 301 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 301 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 301 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 15872000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15872000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15872000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.087221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.087221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.087221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52730.897010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use +system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 97.082868 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.023702 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 2168 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 1142 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits +system.cpu.dcache.demand_hits 3310 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 3310 # number of overall hits +system.cpu.dcache.ReadReq_misses 58 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 300 # number of WriteReq misses +system.cpu.dcache.demand_misses 358 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3282500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 16398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19680500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19680500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.026056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.208044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.097601 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.097601 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56594.827586 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54660 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54973.463687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54973.463687 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 44 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 215 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 220 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 220 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4545000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53547.169811 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53470.588235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 196.307447 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005991 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 352 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 437 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 18310500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4442500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 22753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 22753000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 354 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.994350 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52018.465909 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52066.361556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52066.361556 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14048500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3416000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17464500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17464500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994350 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39910.511364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40188.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini new file mode 100644 index 000000000..6652fe60b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -0,0 +1,535 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout new file mode 100755 index 000000000..14970f00a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:02:00 +gem5 started Jan 23 2012 04:24:22 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 18114000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt new file mode 100644 index 000000000..3a1cfc4e9 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -0,0 +1,472 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18114000 # Number of ticks simulated +final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 74785 # Simulator instruction rate (inst/s) +host_tick_rate 93746300 # Simulator tick rate (ticks/s) +host_mem_usage 213808 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +sim_insts 14449 # Number of instructions simulated +system.physmem.bytes_read 30464 # Number of bytes read from this memory +system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 476 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 1681793088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1165948990 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1681793088 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 36229 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 5641 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7524 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7253 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 639 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 18581 # Type of FU issued +system.cpu.iq.rate 0.512876 # Inst issue rate +system.cpu.iq.fu_busy_cnt 139 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1102 # number of nop insts executed +system.cpu.iew.exec_refs 4620 # number of memory reference insts executed +system.cpu.iew.exec_branches 3963 # Number of branches executed +system.cpu.iew.exec_stores 1758 # Number of stores executed +system.cpu.iew.exec_rate 0.492837 # Inst execution rate +system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 17429 # cumulative count of insts written-back +system.cpu.iew.wb_producers 8123 # num instructions producing a value +system.cpu.iew.wb_consumers 9726 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle +system.cpu.commit.count 15175 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 3674 # Number of memory references committed +system.cpu.commit.loads 2226 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 3359 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 12186 # Number of committed integer instructions. +system.cpu.commit.function_calls 187 # Number of function calls committed. +system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 46300 # The number of ROB reads +system.cpu.rob.rob_writes 43308 # The number of ROB writes +system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 14449 # Number of Instructions Simulated +system.cpu.committedInsts_total 14449 # Number of Instructions Simulated +system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads +system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28557 # number of integer regfile reads +system.cpu.int_regfile_writes 15938 # number of integer regfile writes +system.cpu.misc_regfile_reads 6251 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use +system.cpu.icache.total_refs 4151 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 193.216525 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.094344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 4151 # number of ReadReq hits +system.cpu.icache.demand_hits 4151 # number of demand (read+write) hits +system.cpu.icache.overall_hits 4151 # number of overall hits +system.cpu.icache.ReadReq_misses 457 # number of ReadReq misses +system.cpu.icache.demand_misses 457 # number of demand (read+write) misses +system.cpu.icache.overall_misses 457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15956000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15956000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15956000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.099175 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.099175 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.099175 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34914.660832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34914.660832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34914.660832 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 125 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.072049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.072049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.072049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use +system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 102.149831 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.024939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 2672 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits +system.cpu.dcache.demand_hits 3706 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 3706 # number of overall hits +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses +system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 2786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 4228 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 4228 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.040919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.123463 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.123463 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.034532 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.034532 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 228.374360 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006969 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 476 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..421dd8a46 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,102 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..df7964c68 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:02:00 +gem5 started Jan 23 2012 04:24:24 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 7618500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..389636d62 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,45 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7618500 # Number of ticks simulated +final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 296178 # Simulator instruction rate (inst/s) +host_tick_rate 148615294 # Simulator tick rate (ticks/s) +host_mem_usage 203776 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 15175 # Number of instructions simulated +system.physmem.bytes_read 72223 # Number of bytes read from this memory +system.physmem.bytes_inst_read 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9042 # Number of bytes written to this memory +system.physmem.num_reads 17446 # Number of read requests responded to by this memory +system.physmem.num_writes 1442 # Number of write requests responded to by this memory +system.physmem.num_other 6 # Number of other requests responded to by this memory +system.physmem.bw_read 9479950121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 10666797926 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 385 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls +system.cpu.num_int_insts 12231 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 29059 # number of times the integer registers were read +system.cpu.num_int_register_writes 13832 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 3684 # number of memory refs +system.cpu.num_load_insts 2232 # Number of load instructions +system.cpu.num_store_insts 1452 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 15238 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..fb5a1cb83 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,205 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..d982745c0 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:02:00 +gem5 started Jan 23 2012 04:24:28 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 41800000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..f52890637 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,230 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000042 # Number of seconds simulated +sim_ticks 41800000 # Number of ticks simulated +final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 146106 # Simulator instruction rate (inst/s) +host_tick_rate 402347608 # Simulator tick rate (ticks/s) +host_mem_usage 212484 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +sim_insts 15175 # Number of instructions simulated +system.physmem.bytes_read 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 416 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 83600 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 385 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls +system.cpu.num_int_insts 12231 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 29059 # number of times the integer registers were read +system.cpu.num_int_register_writes 13831 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 3684 # number of memory refs +system.cpu.num_load_insts 2232 # Number of load instructions +system.cpu.num_store_insts 1452 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 83600 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use +system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 153.436702 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.074920 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits +system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits +system.cpu.icache.overall_hits 14941 # number of overall hits +system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses +system.cpu.icache.demand_misses 280 # number of demand (read+write) misses +system.cpu.icache.overall_misses 280 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use +system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 97.842991 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.023887 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 1357 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits +system.cpu.dcache.demand_hits 3530 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 3530 # number of overall hits +system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 85 # number of WriteReq misses +system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4760000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.037623 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.037623 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 184.236128 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005622 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 416 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |