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-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt315
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt217
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt34
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt49
4 files changed, 343 insertions, 272 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 2ad955d95..bc6a50393 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000028 # Number of seconds simulated
-sim_ticks 27662000 # Number of ticks simulated
-final_tick 27662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 27671000 # Number of ticks simulated
+final_tick 27671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71683 # Simulator instruction rate (inst/s)
-host_op_rate 71677 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 130761776 # Simulator tick rate (ticks/s)
-host_mem_usage 270740 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 87465 # Simulator instruction rate (inst/s)
+host_op_rate 87458 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 159601098 # Simulator tick rate (ticks/s)
+host_mem_usage 286440 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19008 # Nu
system.physmem.num_reads::cpu.inst 297 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 435 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 687152050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 319282771 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1006434820 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 687152050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 687152050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 687152050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 319282771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1006434820 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 686928553 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 319178924 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1006107477 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 686928553 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 686928553 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 686928553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 319178924 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1006107477 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 436 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 27628500 # Total gap between requests
+system.physmem.totGap 27637500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -92,8 +92,8 @@ system.physmem.writePktSize::5 0 # Wr
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 115 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -199,44 +199,52 @@ system.physmem.bytesPerActivate::640-767 3 4.55% 78.79% # By
system.physmem.bytesPerActivate::768-895 3 4.55% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 16.67% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation
-system.physmem.totQLat 2526750 # Total ticks spent queuing
-system.physmem.totMemAccLat 10701750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2648750 # Total ticks spent queuing
+system.physmem.totMemAccLat 10823750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5795.30 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6075.11 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24545.30 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1008.75 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24825.11 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1008.42 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1008.75 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1008.42 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.88 # Data bus utilization in percentage
system.physmem.busUtilRead 7.88 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 362 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 63368.12 # Average gap between requests
+system.physmem.avgGap 63388.76 # Average gap between requests
system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1258750 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 21617500 # Time in different power states
+system.physmem.memoryStateTime::ACT 21626500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1006434820 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 351 # Transaction distribution
system.membus.trans_dist::ReadResp 350 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 27840 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 436 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 436 # Request fanout histogram
system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks)
@@ -252,7 +260,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 55325 # number of cpu cycles simulated
+system.cpu.numCycles 55343 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
@@ -274,12 +282,12 @@ system.cpu.execution_unit.executions 11045 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 21861 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 21863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 438 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 37757 # Number of cycles cpu's stages were not processed
+system.cpu.timesIdled 440 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 37775 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
-system.cpu.activity 31.754180 # Percentage of cycles cpu is active
+system.cpu.activity 31.743852 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
@@ -291,36 +299,36 @@ system.cpu.committedInsts 15162 # Nu
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
-system.cpu.cpi 3.648925 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 3.650112 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 3.648925 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.274053 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 3.650112 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.273964 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.274053 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 41899 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.273964 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 41917 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 24.267510 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 45972 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization 24.259617 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 45990 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 16.905558 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 46522 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization 16.900060 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 46540 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 15.911432 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 52447 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization 15.906257 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 52465 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 5.201988 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 46016 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization 5.200296 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 46034 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 16.826028 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization 16.820555 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 168.857752 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 168.877638 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 168.857752 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.082450 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.082450 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 168.877638 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.082460 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.082460 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
@@ -339,12 +347,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
system.cpu.icache.overall_misses::total 381 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 25881500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 25881500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 25881500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 25881500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 25881500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 25881500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25899500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25899500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25899500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25899500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 25899500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25899500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
@@ -357,12 +365,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67930.446194 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67930.446194 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67930.446194 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67930.446194 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67930.446194 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67930.446194 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67977.690289 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67977.690289 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67977.690289 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67977.690289 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67977.690289 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67977.690289 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -383,26 +391,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20450500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 20450500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20450500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 20450500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20450500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 20450500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20459500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 20459500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20459500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 20459500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20459500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 20459500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67941.860465 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67941.860465 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67941.860465 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67941.860465 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67941.860465 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67941.860465 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67971.760797 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67971.760797 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 1011062107 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
@@ -410,11 +417,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 85 # T
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 439 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 439 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 439 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks)
@@ -422,16 +439,16 @@ system.cpu.toL2Bus.respLayer0.utilization 1.8 # L
system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 199.884332 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 199.907137 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.191422 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31.692910 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.211200 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31.695937 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000967 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006100 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.006101 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
@@ -455,16 +472,16 @@ system.cpu.l2cache.demand_misses::total 437 # nu
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20127000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20136000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3695250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 23822250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6008750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6008750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 20127000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9704000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 23831250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5999750 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5999750 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 20136000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9695000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 29831000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 20127000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9704000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 20136000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9695000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 29831000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
@@ -488,16 +505,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67314.381271 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67344.481605 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69721.698113 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67676.846591 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70691.176471 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70691.176471 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.381271 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70318.840580 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67702.414773 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70585.294118 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70585.294118 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67344.481605 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70253.623188 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68263.157895 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.381271 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70318.840580 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67344.481605 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70253.623188 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68263.157895 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@@ -518,16 +535,16 @@ system.cpu.l2cache.demand_mshr_misses::total 437
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16410500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16419500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19446750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4964250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4964250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16410500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8000500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19455750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4955250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4955250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16419500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7991500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 24411000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16410500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8000500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16419500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7991500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 24411000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
@@ -540,27 +557,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54884.615385 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54914.715719 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57287.735849 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55246.448864 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58402.941176 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58402.941176 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54884.615385 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57974.637681 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.017045 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58297.058824 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58297.058824 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54884.615385 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57974.637681 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 98.520897 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 98.520897 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.024053 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.024053 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
@@ -587,12 +604,12 @@ system.cpu.dcache.overall_misses::cpu.data 480 #
system.cpu.dcache.overall_misses::total 480 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 25916250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 25916250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 30184500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 30184500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 30184500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 30184500 # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@@ -613,12 +630,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.130897
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61412.914692 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61412.914692 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62884.375000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62884.375000 # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
@@ -645,12 +662,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 138
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6096750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6096750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9846500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9846500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9846500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9846500 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
@@ -661,12 +678,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71726.470588 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71726.470588 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 07c326366..5e7063deb 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu
sim_ticks 25944000 # Number of ticks simulated
final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 14664 # Simulator instruction rate (inst/s)
-host_op_rate 14664 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26353337 # Simulator tick rate (ticks/s)
-host_mem_usage 237548 # Number of bytes of host memory used
-host_seconds 0.98 # Real time elapsed on the host
+host_inst_rate 79125 # Simulator instruction rate (inst/s)
+host_op_rate 79119 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 142180718 # Simulator tick rate (ticks/s)
+host_mem_usage 289004 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # By
system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation
-system.physmem.totQLat 2648500 # Total ticks spent queuing
-system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2786000 # Total ticks spent queuing
+system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s
@@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 780000 # Ti
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22761250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1211224175 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 409 # Transaction distribution
system.membus.trans_dist::ReadResp 408 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 31424 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 492 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 492 # Request fanout histogram
system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks)
@@ -540,7 +548,6 @@ system.cpu.int_regfile_reads 33400 # nu
system.cpu.int_regfile_writes 18599 # number of integer regfile writes
system.cpu.misc_regfile_reads 7136 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
@@ -548,11 +555,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 83 # T
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks)
@@ -560,12 +577,12 @@ system.cpu.toL2Bus.respLayer0.utilization 2.2 # L
system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id
@@ -586,12 +603,12 @@ system.cpu.icache.demand_misses::cpu.inst 528 # n
system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses
system.cpu.icache.overall_misses::total 528 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses
@@ -604,12 +621,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.081822
system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@@ -630,24 +647,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 346
system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66614.884393 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66614.884393 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use
@@ -655,8 +672,8 @@ system.cpu.l2cache.tags.total_refs 2 # To
system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902478 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 34.634175 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy
@@ -683,16 +700,16 @@ system.cpu.l2cache.demand_misses::total 492 # nu
system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
system.cpu.l2cache.overall_misses::total 492 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22682250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4667500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 22682250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10818500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 22682250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10818500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses)
@@ -716,16 +733,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.995951 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.773256 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71807.692308 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@@ -746,16 +763,16 @@ system.cpu.l2cache.demand_mshr_misses::total 492
system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18356250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3880500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18356250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9012000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18356250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9012000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
@@ -768,25 +785,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59700 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 98.823641 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
@@ -813,14 +830,14 @@ system.cpu.dcache.demand_misses::cpu.data 548 # n
system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses
system.cpu.dcache.overall_misses::total 548 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8661750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8661750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 34754974 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 34754974 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 34754974 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 34754974 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@@ -839,14 +856,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.117445
system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63421.485401 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63421.485401 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
@@ -871,14 +888,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4732000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4732000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10967500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10967500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10967500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10967500 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
@@ -887,14 +904,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719
system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72800 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72800 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 33f452573..8d8eb59bc 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds 0.000008 # Nu
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 945144 # Simulator instruction rate (inst/s)
-host_op_rate 944261 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 473677660 # Simulator tick rate (ticks/s)
-host_mem_usage 260980 # Number of bytes of host memory used
+host_inst_rate 893248 # Simulator instruction rate (inst/s)
+host_op_rate 892512 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 447738368 # Simulator tick rate (ticks/s)
+host_mem_usage 276192 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
@@ -37,9 +37,29 @@ system.physmem.bw_write::total 1187861272 # Wr
system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 10676563321 # Throughput (bytes/s)
-system.membus.data_through_bus 81270 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.trans_dist::ReadReq 17432 # Transaction distribution
+system.membus.trans_dist::ReadResp 17432 # Transaction distribution
+system.membus.trans_dist::WriteReq 1442 # Transaction distribution
+system.membus.trans_dist::WriteResp 1442 # Transaction distribution
+system.membus.trans_dist::SwapReq 6 # Transaction distribution
+system.membus.trans_dist::SwapResp 6 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 18880 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram
+system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 18880 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 15225 # number of cpu cycles simulated
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 853f97527..6363c4d14 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu
sim_ticks 41368000 # Number of ticks simulated
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 324057 # Simulator instruction rate (inst/s)
-host_op_rate 323947 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 883591781 # Simulator tick rate (ticks/s)
-host_mem_usage 269720 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 245276 # Simulator instruction rate (inst/s)
+host_op_rate 245221 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 668919684 # Simulator tick rate (ticks/s)
+host_mem_usage 285672 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 430090892 # In
system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 643589248 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 331 # Transaction distribution
system.membus.trans_dist::ReadResp 331 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 26624 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 416 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 416 # Request fanout histogram
system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
@@ -427,7 +435,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
@@ -435,11 +442,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 85 # T
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)