diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level')
4 files changed, 0 insertions, 1196 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini deleted file mode 100644 index 5a1f94c78..000000000 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini +++ /dev/null @@ -1,432 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911:0:0:0:0 -memories=system.mem_ctrl -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.clk_domain] -type=SrcClockDomain -children=voltage_domain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.clk_domain.voltage_domain - -[system.clk_domain.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.clk_domain -cpu_id=-1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=65536 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.l2bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=65536 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=16384 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.icache_port -mem_side=system.l2bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=16384 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=tests/test-progs/hello/bin/alpha/linux/hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable= -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.l2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.l2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=262144 -system=system -tags=system.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.l2bus.master[0] -mem_side=system.membus.slave[0] - -[system.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.mem_ctrl] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:536870911:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.mem_ctrl.port -slave=system.l2cache.mem_side system.system_port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr deleted file mode 100755 index 2f9507495..000000000 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout deleted file mode 100755 index 2e75b8af5..000000000 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout +++ /dev/null @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28074 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level - -Global frequency set at 1000000000000 ticks per second -Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 64758000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt deleted file mode 100644 index 58d0eeab6..000000000 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ /dev/null @@ -1,745 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000065 # Number of seconds simulated -sim_ticks 64758000 # Number of ticks simulated -final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 610635 # Simulator instruction rate (inst/s) -host_op_rate 610062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6117087273 # Simulator tick rate (ticks/s) -host_mem_usage 638532 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 6453 # Number of instructions simulated -sim_ops 6453 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 446 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 64501000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation -system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 144621.08 # Average gap between requests -system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states -system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1190 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1197 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2055 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2065 # DTB accesses -system.cpu.itb.fetch_hits 6464 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6481 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 64758 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6453 # Number of instructions committed -system.cpu.committedOps 6453 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls -system.cpu.num_int_insts 6380 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8392 # number of times the integer registers were read -system.cpu.num_int_register_writes 4621 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2065 # number of memory refs -system.cpu.num_load_insts 1197 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 64758 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1060 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction -system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::MemRead 1196 18.51% 86.55% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.32% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6463 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits -system.cpu.dcache.overall_hits::total 1887 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13209 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits -system.cpu.icache.overall_hits::total 6183 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses -system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 376 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 449 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 449 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use -system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 4534 # Number of tag accesses -system.l2cache.tags.data_accesses 4534 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.l2cache.overall_hits::total 3 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.l2cache.demand_misses::total 446 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.l2cache.overall_misses::cpu.data 168 # number of overall misses -system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 373 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 446 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 446 # Request fanout histogram -system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |