diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/alpha/linux')
6 files changed, 390 insertions, 354 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini index 407eb5e1e..1efeb5f99 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -153,27 +153,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -193,6 +193,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -202,7 +203,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -224,9 +225,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -235,6 +236,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -246,7 +248,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -254,3 +256,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout index 7b44dd5a2..4e8f563cb 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39594 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:47 +gem5 executing on e108600-lin, pid 28091 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 405365000 because target called exit() +Exiting @ tick 461109000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index f8c482cd0..090f011e7 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000415 # Number of seconds simulated -sim_ticks 414695000 # Number of ticks simulated -final_tick 414695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000461 # Number of seconds simulated +sim_ticks 461109000 # Number of ticks simulated +final_tick 461109000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187951 # Simulator instruction rate (inst/s) -host_op_rate 187881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12069868237 # Simulator tick rate (ticks/s) -host_mem_usage 635076 # Number of bytes of host memory used +host_inst_rate 212686 # Simulator instruction rate (inst/s) +host_op_rate 212584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15184120914 # Simulator tick rate (ticks/s) +host_mem_usage 634004 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory @@ -26,63 +26,63 @@ system.mem_ctrl.num_reads::cpu.data 1190 # Nu system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 62339792 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 21326517 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 83666309 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 62339792 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 62339792 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16146807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16146807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 62339792 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 37473324 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 99813116 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 56064835 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 19179847 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 75244682 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 56064835 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 56064835 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 14521512 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 14521512 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 56064835 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 33701359 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 89766194 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 7654 # Number of read requests accepted system.mem_ctrl.writeReqs 865 # Number of write requests accepted system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 478016 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 11840 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 746 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 752 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 766 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 764 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 249 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 1431 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 91 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 26 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 20 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 414618000 # Total gap between requests +system.mem_ctrl.totGap 461032000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 7469 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,12 +146,12 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 6 # What write queue length does an incoming req see @@ -193,87 +193,95 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 765 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 630.044444 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 420.142008 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 402.263677 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 142 18.56% 18.56% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 72 9.41% 27.97% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 39 5.10% 33.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 50 6.54% 39.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 49 6.41% 46.01% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 26 3.40% 49.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 3.53% 52.94% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 39 5.10% 58.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 321 41.96% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 765 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 766 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 629.556136 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 420.481555 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 399.288519 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 144 18.80% 18.80% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 67 8.75% 27.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 42 5.48% 33.03% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 49 6.40% 39.43% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 40 5.22% 44.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 39 5.09% 49.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 38 4.96% 54.70% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 34 4.44% 59.14% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 313 40.86% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 766 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1155.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1053.155116 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 490.786070 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1343 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1728-1791 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1237 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1086.549947 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 686.122730 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1152-1279 2 33.33% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2304-2431 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 26666250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 166710000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 37345000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3570.26 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 73323250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 213217000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9827.54 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22320.26 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1152.69 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 14.82 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 83.68 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.15 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28577.54 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1035.56 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 13.32 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 75.25 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 14.52 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.12 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.01 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.09 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 22.92 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 6707 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 73.95 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48669.80 # Average gap between requests -system.mem_ctrl.pageHitRate 89.55 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3409560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1860375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37159200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 187920 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 262129320 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 17820750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 349520805 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 846.438251 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 26708250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 13780000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 372456750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 2373840 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1295250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 20833800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 434160 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 231001335 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 45144000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 328036065 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 794.350717 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 73389500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 13780000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 325838500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.avgWrQLen 23.97 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 6701 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 86 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.81 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 76.11 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 54118.09 # Average gap between requests +system.mem_ctrl.pageHitRate 89.61 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3184440 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1681185 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 34164900 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 130500 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 65335680 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1899360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 128211240 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 12180000 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 283051065 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 613.847162 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 312833500 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 882000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 31715250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 132053500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 281118250 # Time in different power states +system.mem_ctrl_1.actEnergy 2313360 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1225785 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 19099500 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 370620 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 35649120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 44402430 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1287360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 129142620 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 18055680 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 8894220 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 260440695 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 564.812507 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 359701750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 1420000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 15098000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 30156500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 47020500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 84176750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 283237250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -307,8 +315,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 414695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 414695 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 461109000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 461109 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -327,7 +335,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 414695 # Number of busy cycles +system.cpu.num_busy_cycles 461109 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -372,7 +380,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7654 # Transaction distribution system.membus.trans_dist::ReadResp 7653 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution @@ -396,10 +404,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8519 # Request fanout histogram system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 14691750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3578000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 14690000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 3572750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini index f8108d4cd..5a1f94c78 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -151,7 +151,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -275,7 +275,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -320,27 +320,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -360,6 +360,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -369,7 +370,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -391,9 +392,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -402,6 +403,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -413,7 +415,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -421,3 +423,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout index 7505aca67..2e75b8af5 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39597 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28074 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 61470000 because target called exit() +Exiting @ tick 64758000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 1f58ca472..47755a477 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000062 # Number of seconds simulated -sim_ticks 62213000 # Number of ticks simulated -final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000065 # Number of seconds simulated +sim_ticks 64758000 # Number of ticks simulated +final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 276862 # Simulator instruction rate (inst/s) -host_op_rate 276760 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2667377590 # Simulator tick rate (ticks/s) -host_mem_usage 639424 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 560678 # Simulator instruction rate (inst/s) +host_op_rate 559951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5612828222 # Simulator tick rate (ticks/s) +host_mem_usage 638096 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61962000 # Total gap between requests +system.mem_ctrl.totGap 64501000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,80 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation +system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 138928.25 # Average gap between requests -system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 144621.08 # Average gap between requests +system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states +system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -284,8 +294,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 62213 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 64758 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -304,7 +314,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 62213 # Number of busy cycles +system.cpu.num_busy_cycles 64758 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -343,23 +353,23 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -376,14 +386,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -400,14 +410,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,14 +432,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -438,31 +448,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses system.cpu.icache.tags.data_accesses 13209 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits @@ -475,12 +485,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses @@ -493,12 +503,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,31 +521,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -563,28 +573,28 @@ system.l2bus.snoop_fanout::total 449 # Re system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4534 # Number of tag accesses system.l2cache.tags.data_accesses 4534 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -602,17 +612,17 @@ system.l2cache.demand_misses::total 446 # nu system.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.l2cache.overall_misses::cpu.data 168 # number of overall misses system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) @@ -635,17 +645,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,17 +673,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses @@ -685,24 +695,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -725,7 +735,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- |