diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt')
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index f933f7176..60d51d141 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 411650 # Simulator instruction rate (inst/s) -host_op_rate 475781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4107877451 # Simulator tick rate (ticks/s) -host_mem_usage 655016 # Number of bytes of host memory used +host_inst_rate 523400 # Simulator instruction rate (inst/s) +host_op_rate 604831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5220928914 # Simulator tick rate (ticks/s) +host_mem_usage 655332 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated @@ -503,8 +503,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses @@ -537,7 +535,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 70 # number of replacements system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. @@ -595,8 +592,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses @@ -621,7 +616,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -744,8 +738,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses @@ -790,7 +782,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution |