diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/arm')
8 files changed, 2098 insertions, 0 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini new file mode 100644 index 000000000..9250f1293 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -0,0 +1,328 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[2] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.membus.slave[1] +icache_port=system.membus.slave[0] + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/arm/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.cpu.icache_port system.cpu.dcache_port system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout new file mode 100755 index 000000000..0a8438e59 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -0,0 +1,13 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:23:26 +gem5 started Jul 8 2015 14:24:31 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 325849000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt new file mode 100644 index 000000000..a106dd982 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -0,0 +1,480 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000326 # Number of seconds simulated +sim_ticks 325849000 # Number of ticks simulated +final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 60983 # Simulator instruction rate (inst/s) +host_op_rate 70534 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3982742967 # Simulator tick rate (ticks/s) +host_mem_usage 686060 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +sim_insts 4988 # Number of instructions simulated +sim_ops 5770 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory +system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory +system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 1061 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory +system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory +system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 61709565 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 14337930 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 76047494 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 61709565 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 61709565 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 11342677 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 11342677 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 61709565 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 25680607 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 87390172 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 6089 # Number of read requests accepted +system.mem_ctrl.writeReqs 936 # Number of write requests accepted +system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 384000 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 3072 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 856 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 724 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 364 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 505 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 303 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 487 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 194 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 431 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 80 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 30 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 325773000 # Total gap between requests +system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 160 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 16 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 920 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 5991 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 9 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 3 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 495 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 775.886869 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 648.412049 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 330.044561 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 19 3.84% 3.84% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 31 6.26% 10.10% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 37 7.47% 17.58% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 33 6.67% 24.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 20 4.04% 28.28% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 33 6.67% 34.95% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 27 5.45% 40.40% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 25 5.05% 45.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 270 54.55% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 495 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1299.666667 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1199.462709 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 577.403094 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-703 1 33.33% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1471 1 33.33% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1792-1855 1 33.33% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 3 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::16 3 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 3 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 17801000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 130301000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 30000000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 2966.83 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 21716.83 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1178.46 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 9.43 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 76.06 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 11.34 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 9.28 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.21 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 24.64 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5504 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 44 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 91.73 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 55.00 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 46373.38 # Average gap between requests +system.mem_ctrl.pageHitRate 91.25 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2782080 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1518000 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37915800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 212134050 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 5616000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 280816890 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 878.932981 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 6234500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 303655500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 7932600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 182238975 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.numCycles 325849 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 4988 # Number of instructions committed +system.cpu.committedOps 5770 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 215 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls +system.cpu.num_int_insts 4977 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 8084 # number of times the integer registers were read +system.cpu.num_int_register_writes 2992 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read +system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written +system.cpu.num_mem_refs 2035 # number of memory refs +system.cpu.num_load_insts 1085 # Number of load instructions +system.cpu.num_store_insts 950 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 325848.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1107 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction +system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5831 # Class of executed instruction +system.membus.trans_dist::ReadReq 6078 # Transaction distribution +system.membus.trans_dist::ReadResp 6088 # Transaction distribution +system.membus.trans_dist::WriteReq 925 # Transaction distribution +system.membus.trans_dist::WriteResp 925 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14049 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28476 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7025 # Request fanout histogram +system.membus.snoop_fanout::mean 0.715730 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.451098 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1997 28.43% 28.43% # Request fanout histogram +system.membus.snoop_fanout::1 5028 71.57% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 7025 # Request fanout histogram +system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 11411750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3326000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini new file mode 100644 index 000000000..b60a06c99 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -0,0 +1,448 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=65536 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.l2bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=65536 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=16384 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.l2bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=16384 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/arm/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2bus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=262144 +system=system +tags=system.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +cpu_side=system.l2bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=262144 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.l2cache.mem_side system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout new file mode 100755 index 000000000..cd1c56413 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -0,0 +1,13 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:23:26 +gem5 started Jul 8 2015 14:24:31 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 49855000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt new file mode 100644 index 000000000..dde0dd6ed --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -0,0 +1,812 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000050 # Number of seconds simulated +sim_ticks 49855000 # Number of ticks simulated +final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 79800 # Simulator instruction rate (inst/s) +host_op_rate 92294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 797317444 # Simulator tick rate (ticks/s) +host_mem_usage 690160 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 4988 # Number of instructions simulated +sim_ops 5770 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory +system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 351 # Number of read requests accepted +system.mem_ctrl.writeReqs 0 # Number of write requests accepted +system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 49757000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation +system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrl.avgGap 141757.83 # Average gap between requests +system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.numCycles 49855 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 4988 # Number of instructions committed +system.cpu.committedOps 5770 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 215 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls +system.cpu.num_int_insts 4977 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 8084 # number of times the integer registers were read +system.cpu.num_int_register_writes 2992 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read +system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written +system.cpu.num_mem_refs 2035 # number of memory refs +system.cpu.num_load_insts 1085 # Number of load instructions +system.cpu.num_store_insts 950 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1107 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction +system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5831 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits +system.cpu.dcache.overall_hits::total 1833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses +system.cpu.dcache.overall_misses::total 142 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 70 # number of replacements +system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10305 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits +system.cpu.icache.overall_hits::total 4779 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses +system.cpu.icache.overall_misses::total 249 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.trans_dist::ReadResp 348 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution +system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution +system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution +system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 842 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.snoops 0 # Total snoops (count) +system.l2bus.snoop_fanout::samples 461 # Request fanout histogram +system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::total 461 # Request fanout histogram +system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) +system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) +system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) +system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.l2cache.tags.replacements 0 # number of replacements +system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use +system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. +system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. +system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id +system.l2cache.tags.tag_accesses 3959 # Number of tag accesses +system.l2cache.tags.data_accesses 3959 # Number of data accesses +system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits +system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits +system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits +system.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.l2cache.overall_hits::cpu.inst 24 # number of overall hits +system.l2cache.overall_hits::cpu.data 16 # number of overall hits +system.l2cache.overall_hits::total 40 # number of overall hits +system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses +system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.l2cache.ReadSharedReq_misses::cpu.inst 225 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses +system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses +system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses +system.l2cache.demand_misses::total 351 # number of demand (read+write) misses +system.l2cache.overall_misses::cpu.inst 225 # number of overall misses +system.l2cache.overall_misses::cpu.data 126 # number of overall misses +system.l2cache.overall_misses::total 351 # number of overall misses +system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles +system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses +system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses +system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses +system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses +system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses +system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses +system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses +system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses +system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses +system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses +system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses +system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses +system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency +system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2cache.fast_writes 0 # number of fast writes performed +system.l2cache.cache_copies 0 # number of cache copies performed +system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses +system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses +system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses +system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses +system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency +system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 351 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 351 # Request fanout histogram +system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |