diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/sparc/linux')
-rw-r--r-- | tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 010db5b17..718f7b51e 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 486070 # Simulator instruction rate (inst/s) -host_op_rate 485474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4661655450 # Simulator tick rate (ticks/s) -host_mem_usage 680524 # Number of bytes of host memory used +host_inst_rate 388058 # Simulator instruction rate (inst/s) +host_op_rate 387570 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3721714769 # Simulator tick rate (ticks/s) +host_mem_usage 636836 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated @@ -382,8 +382,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses @@ -416,7 +414,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 71 # number of replacements system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. @@ -474,8 +471,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses @@ -500,7 +495,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -623,8 +617,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses @@ -669,7 +661,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution system.membus.trans_dist::ReadExResp 82 # Transaction distribution |