diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt')
| -rw-r--r-- | tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt | 409 |
1 files changed, 210 insertions, 199 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index a74924642..bf9b895e3 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000056 # Number of seconds simulated -sim_ticks 56435000 # Number of ticks simulated -final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000059 # Number of seconds simulated +sim_ticks 58513000 # Number of ticks simulated +final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125605 # Simulator instruction rate (inst/s) -host_op_rate 226732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1240265940 # Simulator tick rate (ticks/s) -host_mem_usage 656384 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 325988 # Simulator instruction rate (inst/s) +host_op_rate 588251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3335289412 # Simulator tick rate (ticks/s) +host_mem_usage 654560 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14656 # Nu system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 364 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 56304000 # Total gap between requests +system.mem_ctrl.totGap 58376000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,77 +187,88 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation +system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 154681.32 # Average gap between requests -system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 160373.63 # Average gap between requests +system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states +system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states +system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states +system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56435 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 58513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -278,7 +289,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles +system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -317,23 +328,23 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits @@ -350,14 +361,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) @@ -374,14 +385,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,14 +407,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses @@ -412,31 +423,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits @@ -449,12 +460,12 @@ system.cpu.icache.demand_misses::cpu.inst 235 # n system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses @@ -467,12 +478,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,31 +496,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 235 system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -535,30 +546,30 @@ system.l2bus.snoop_fanout::min_value 0 # Re system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 370 # Request fanout histogram system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3788 # Number of tag accesses system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits @@ -576,17 +587,17 @@ system.l2cache.demand_misses::total 364 # nu system.l2cache.overall_misses::cpu.inst 229 # number of overall misses system.l2cache.overall_misses::cpu.data 135 # number of overall misses system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -609,17 +620,17 @@ system.l2cache.demand_miss_rate::total 0.983784 # mi system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,17 +648,17 @@ system.l2cache.demand_mshr_misses::total 364 # nu system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -659,24 +670,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.983784 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution @@ -701,7 +712,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 364 # Request fanout histogram system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |