diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5/ref/x86')
8 files changed, 1148 insertions, 1136 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini index 612b72e20..55e4fb657 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -180,10 +182,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout index 3227a9df4..7864b0cf9 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:11:23 -gem5 executing on e108600-lin, pid 17668 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:23 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87205 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 507841000 because target called exit() +Exiting @ tick 507841000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index 7797c05db..b34dd3952 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,398 +1,398 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000508 # Number of seconds simulated -sim_ticks 507841000 # Number of ticks simulated -final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118772 # Simulator instruction rate (inst/s) -host_op_rate 214398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10553661963 # Simulator tick rate (ticks/s) -host_mem_usage 651408 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 7160 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 7160 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 7283 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1084 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 114728823 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14112685 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 128841507 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 114728823 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 28211586 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 142940409 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 8367 # Number of read requests accepted -system.mem_ctrl.writeReqs 941 # Number of write requests accepted -system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 1619 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 965 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1103 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 10 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 54 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 34 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 4 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 507709000 # Total gap between requests -system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 8099 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 14 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 3 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 63 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 861 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 856 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 618.018692 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 421.107711 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 393.969749 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 856 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 82515500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 236378000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 10055.51 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28805.51 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1034.15 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 14.11 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 128.84 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 14.10 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.08 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.79 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7357 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.65 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54545.44 # Average gap between requests -system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3127320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1647030 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37149420 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 52200 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 70559160 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1716480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 113314290 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 13222080 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 17426520 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 294478260 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 579.862821 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 347720500 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 1584000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 15358000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 65707000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 142245250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 # Time in different power states -system.mem_ctrl_1.actEnergy 3034500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1601490 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 21441420 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 532440 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 51598110 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1155360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 151289970 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 18740160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 3216240 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 291946650 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 574.877779 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 391695500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 757000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 16646000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 11100000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 98712250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 507841000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 507841 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 507840.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 8367 # Transaction distribution -system.membus.trans_dist::ReadResp 8367 # Transaction distribution -system.membus.trans_dist::WriteReq 941 # Transaction distribution -system.membus.trans_dist::WriteResp 941 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 18616 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 72591 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 9308 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9308 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9308 # Request fanout histogram -system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 16544750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3432250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +sim_seconds 0.000508 +sim_ticks 507841000 +final_tick 507841000 +sim_freq 1000000000000 +host_inst_rate 110016 +host_op_rate 198569 +host_tick_rate 9773316243 +host_mem_usage 663056 +host_seconds 0.05 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 +system.mem_ctrl.bytes_read::cpu.inst 58264 +system.mem_ctrl.bytes_read::cpu.data 7167 +system.mem_ctrl.bytes_read::total 65431 +system.mem_ctrl.bytes_inst_read::cpu.inst 58264 +system.mem_ctrl.bytes_inst_read::total 58264 +system.mem_ctrl.bytes_written::cpu.data 7160 +system.mem_ctrl.bytes_written::total 7160 +system.mem_ctrl.num_reads::cpu.inst 7283 +system.mem_ctrl.num_reads::cpu.data 1084 +system.mem_ctrl.num_reads::total 8367 +system.mem_ctrl.num_writes::cpu.data 941 +system.mem_ctrl.num_writes::total 941 +system.mem_ctrl.bw_read::cpu.inst 114728823 +system.mem_ctrl.bw_read::cpu.data 14112685 +system.mem_ctrl.bw_read::total 128841507 +system.mem_ctrl.bw_inst_read::cpu.inst 114728823 +system.mem_ctrl.bw_inst_read::total 114728823 +system.mem_ctrl.bw_write::cpu.data 14098901 +system.mem_ctrl.bw_write::total 14098901 +system.mem_ctrl.bw_total::cpu.inst 114728823 +system.mem_ctrl.bw_total::cpu.data 28211586 +system.mem_ctrl.bw_total::total 142940409 +system.mem_ctrl.readReqs 8368 +system.mem_ctrl.writeReqs 941 +system.mem_ctrl.readBursts 8368 +system.mem_ctrl.writeBursts 941 +system.mem_ctrl.bytesReadDRAM 525248 +system.mem_ctrl.bytesReadWrQ 10304 +system.mem_ctrl.bytesWritten 7168 +system.mem_ctrl.bytesReadSys 65439 +system.mem_ctrl.bytesWrittenSys 7160 +system.mem_ctrl.servicedByWrQ 161 +system.mem_ctrl.mergedWrBursts 810 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 277 +system.mem_ctrl.perBankRdBursts::1 4 +system.mem_ctrl.perBankRdBursts::2 227 +system.mem_ctrl.perBankRdBursts::3 102 +system.mem_ctrl.perBankRdBursts::4 1619 +system.mem_ctrl.perBankRdBursts::5 965 +system.mem_ctrl.perBankRdBursts::6 1103 +system.mem_ctrl.perBankRdBursts::7 906 +system.mem_ctrl.perBankRdBursts::8 703 +system.mem_ctrl.perBankRdBursts::9 491 +system.mem_ctrl.perBankRdBursts::10 1059 +system.mem_ctrl.perBankRdBursts::11 59 +system.mem_ctrl.perBankRdBursts::12 11 +system.mem_ctrl.perBankRdBursts::13 489 +system.mem_ctrl.perBankRdBursts::14 78 +system.mem_ctrl.perBankRdBursts::15 114 +system.mem_ctrl.perBankWrBursts::0 10 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 3 +system.mem_ctrl.perBankWrBursts::9 54 +system.mem_ctrl.perBankWrBursts::10 34 +system.mem_ctrl.perBankWrBursts::11 7 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 4 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 507764000 +system.mem_ctrl.readPktSize::0 135 +system.mem_ctrl.readPktSize::1 14 +system.mem_ctrl.readPktSize::2 119 +system.mem_ctrl.readPktSize::3 8100 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 14 +system.mem_ctrl.writePktSize::1 3 +system.mem_ctrl.writePktSize::2 63 +system.mem_ctrl.writePktSize::3 861 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 8207 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 8 +system.mem_ctrl.wrQLenPdf::18 8 +system.mem_ctrl.wrQLenPdf::19 7 +system.mem_ctrl.wrQLenPdf::20 7 +system.mem_ctrl.wrQLenPdf::21 7 +system.mem_ctrl.wrQLenPdf::22 7 +system.mem_ctrl.wrQLenPdf::23 7 +system.mem_ctrl.wrQLenPdf::24 7 +system.mem_ctrl.wrQLenPdf::25 7 +system.mem_ctrl.wrQLenPdf::26 7 +system.mem_ctrl.wrQLenPdf::27 7 +system.mem_ctrl.wrQLenPdf::28 7 +system.mem_ctrl.wrQLenPdf::29 7 +system.mem_ctrl.wrQLenPdf::30 7 +system.mem_ctrl.wrQLenPdf::31 7 +system.mem_ctrl.wrQLenPdf::32 7 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 856 +system.mem_ctrl.bytesPerActivate::mean 618.018692 +system.mem_ctrl.bytesPerActivate::gmean 421.107711 +system.mem_ctrl.bytesPerActivate::stdev 393.969749 +system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% +system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% +system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% +system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% +system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% +system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% +system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% +system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% +system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% +system.mem_ctrl.bytesPerActivate::total 856 +system.mem_ctrl.rdPerTurnAround::samples 7 +system.mem_ctrl.rdPerTurnAround::mean 1165.285714 +system.mem_ctrl.rdPerTurnAround::gmean 941.793638 +system.mem_ctrl.rdPerTurnAround::stdev 714.559471 +system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% +system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% +system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% +system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% +system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% +system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% +system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% +system.mem_ctrl.rdPerTurnAround::total 7 +system.mem_ctrl.wrPerTurnAround::samples 7 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 7 +system.mem_ctrl.totQLat 82521500 +system.mem_ctrl.totMemAccLat 236402750 +system.mem_ctrl.totBusLat 41035000 +system.mem_ctrl.avgQLat 10055.01 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28805.01 +system.mem_ctrl.avgRdBW 1034.28 +system.mem_ctrl.avgWrBW 14.11 +system.mem_ctrl.avgRdBWSys 128.86 +system.mem_ctrl.avgWrBWSys 14.10 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.19 +system.mem_ctrl.busUtilRead 8.08 +system.mem_ctrl.busUtilWrite 0.11 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 23.79 +system.mem_ctrl.readRowHits 7358 +system.mem_ctrl.writeRowHits 98 +system.mem_ctrl.readRowHitRate 89.66 +system.mem_ctrl.writeRowHitRate 74.81 +system.mem_ctrl.avgGap 54545.49 +system.mem_ctrl.pageHitRate 89.42 +system.mem_ctrl_0.actEnergy 3127320 +system.mem_ctrl_0.preEnergy 1647030 +system.mem_ctrl_0.readEnergy 37149420 +system.mem_ctrl_0.writeEnergy 52200 +system.mem_ctrl_0.refreshEnergy 36263760.000000 +system.mem_ctrl_0.actBackEnergy 70559160 +system.mem_ctrl_0.preBackEnergy 1716480 +system.mem_ctrl_0.actPowerDownEnergy 113314290 +system.mem_ctrl_0.prePowerDownEnergy 13222080 +system.mem_ctrl_0.selfRefreshEnergy 17426520 +system.mem_ctrl_0.totalEnergy 294478260 +system.mem_ctrl_0.averagePower 579.862821 +system.mem_ctrl_0.totalIdleTime 347720500 +system.mem_ctrl_0.memoryStateTime::IDLE 1584000 +system.mem_ctrl_0.memoryStateTime::REF 15358000 +system.mem_ctrl_0.memoryStateTime::SREF 65707000 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 +system.mem_ctrl_0.memoryStateTime::ACT 142245250 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 +system.mem_ctrl_1.actEnergy 3034500 +system.mem_ctrl_1.preEnergy 1601490 +system.mem_ctrl_1.readEnergy 21441420 +system.mem_ctrl_1.writeEnergy 532440 +system.mem_ctrl_1.refreshEnergy 39336960.000000 +system.mem_ctrl_1.actBackEnergy 51598110 +system.mem_ctrl_1.preBackEnergy 1155360 +system.mem_ctrl_1.actPowerDownEnergy 151289970 +system.mem_ctrl_1.prePowerDownEnergy 18740160 +system.mem_ctrl_1.selfRefreshEnergy 3216240 +system.mem_ctrl_1.totalEnergy 291946650 +system.mem_ctrl_1.averagePower 574.877779 +system.mem_ctrl_1.totalIdleTime 391725750 +system.mem_ctrl_1.memoryStateTime::IDLE 757000 +system.mem_ctrl_1.memoryStateTime::REF 16646000 +system.mem_ctrl_1.memoryStateTime::SREF 11100000 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 +system.mem_ctrl_1.memoryStateTime::ACT 98712250 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 +system.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.apic_clk_domain.clock 16000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 507841000 +system.cpu.numCycles 507841 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5712 +system.cpu.committedOps 10314 +system.cpu.num_int_alu_accesses 10205 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 221 +system.cpu.num_conditional_control_insts 986 +system.cpu.num_int_insts 10205 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 19296 +system.cpu.num_int_register_writes 7977 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 7020 +system.cpu.num_cc_register_writes 3825 +system.cpu.num_mem_refs 2025 +system.cpu.num_load_insts 1084 +system.cpu.num_store_insts 941 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 507841 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1306 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 8275 80.23% 80.24% +system.cpu.op_class::IntMult 6 0.06% 80.30% +system.cpu.op_class::IntDiv 7 0.07% 80.37% +system.cpu.op_class::FloatAdd 0 0.00% 80.37% +system.cpu.op_class::FloatCmp 0 0.00% 80.37% +system.cpu.op_class::FloatCvt 0 0.00% 80.37% +system.cpu.op_class::FloatMult 0 0.00% 80.37% +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::FloatDiv 0 0.00% 80.37% +system.cpu.op_class::FloatMisc 0 0.00% 80.37% +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdAdd 0 0.00% 80.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% +system.cpu.op_class::SimdAlu 0 0.00% 80.37% +system.cpu.op_class::SimdCmp 0 0.00% 80.37% +system.cpu.op_class::SimdCvt 0 0.00% 80.37% +system.cpu.op_class::SimdMisc 0 0.00% 80.37% +system.cpu.op_class::SimdMult 0 0.00% 80.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdShift 0 0.00% 80.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% +system.cpu.op_class::MemRead 1084 10.51% 90.88% +system.cpu.op_class::MemWrite 941 9.12% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 10314 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 +system.membus.trans_dist::ReadReq 8368 +system.membus.trans_dist::ReadResp 8367 +system.membus.trans_dist::WriteReq 941 +system.membus.trans_dist::WriteResp 941 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14567 +system.membus.pkt_count_system.cpu.icache_port::total 14567 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 +system.membus.pkt_count_system.cpu.dcache_port::total 4050 +system.membus.pkt_count::total 18617 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 +system.membus.pkt_size_system.cpu.icache_port::total 58264 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 +system.membus.pkt_size_system.cpu.dcache_port::total 14327 +system.membus.pkt_size::total 72591 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 9309 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 9309 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 9309 +system.membus.reqLayer2.occupancy 10250000 +system.membus.reqLayer2.utilization 2.0 +system.membus.respLayer0.occupancy 16544750 +system.membus.respLayer0.utilization 3.3 +system.membus.respLayer1.occupancy 3432250 +system.membus.respLayer1.utilization 0.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini index c3a9301a3..be3d0013c 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -110,10 +112,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -127,6 +129,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -139,15 +142,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -175,10 +179,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -192,6 +196,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -204,15 +209,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -259,7 +265,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -272,10 +278,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -325,10 +332,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -342,6 +349,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -354,15 +362,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout index 736ff89ea..51ea33107 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:22 -gem5 executing on e108600-lin, pid 17647 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87157 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 58513000 because target called exit() +Exiting @ tick 58513000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index c7497d010..5f55051fc 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,722 +1,722 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 58513000 # Number of ticks simulated -final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297973 # Simulator instruction rate (inst/s) -host_op_rate 537391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3045372421 # Simulator tick rate (ticks/s) -host_mem_usage 656016 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 364 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 30 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 40 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 24 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 71 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 16 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58376000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 364 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation -system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 160373.63 # Average gap between requests -system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states -system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58513 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits -system.cpu.dcache.overall_hits::total 1890 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses -system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits -system.cpu.icache.overall_hits::total 7048 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses -system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 291 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 370 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.002703 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.051988 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 370 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use -system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3788 # Number of tag accesses -system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits -system.l2cache.demand_hits::total 6 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 6 # number of overall hits -system.l2cache.overall_hits::total 6 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.l2cache.demand_misses::total 364 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 229 # number of overall misses -system.l2cache.overall_misses::cpu.data 135 # number of overall misses -system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 235 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 370 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 285 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::total 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 364 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 364 # Request fanout histogram -system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +sim_seconds 0.000059 +sim_ticks 58513000 +final_tick 58513000 +sim_freq 1000000000000 +host_inst_rate 157408 +host_op_rate 284057 +host_tick_rate 1610644917 +host_mem_usage 667152 +host_seconds 0.04 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 +system.mem_ctrl.bytes_read::cpu.inst 14656 +system.mem_ctrl.bytes_read::cpu.data 8640 +system.mem_ctrl.bytes_read::total 23296 +system.mem_ctrl.bytes_inst_read::cpu.inst 14656 +system.mem_ctrl.bytes_inst_read::total 14656 +system.mem_ctrl.num_reads::cpu.inst 229 +system.mem_ctrl.num_reads::cpu.data 135 +system.mem_ctrl.num_reads::total 364 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+system.mem_ctrl.perBankRdBursts::6 13 +system.mem_ctrl.perBankRdBursts::7 24 +system.mem_ctrl.perBankRdBursts::8 17 +system.mem_ctrl.perBankRdBursts::9 71 +system.mem_ctrl.perBankRdBursts::10 62 +system.mem_ctrl.perBankRdBursts::11 14 +system.mem_ctrl.perBankRdBursts::12 2 +system.mem_ctrl.perBankRdBursts::13 14 +system.mem_ctrl.perBankRdBursts::14 4 +system.mem_ctrl.perBankRdBursts::15 16 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 0 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 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+system.mem_ctrl.bytesPerActivate::stdev 199.282229 +system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% +system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% +system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% +system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% +system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% +system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% +system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% +system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% +system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% +system.mem_ctrl.bytesPerActivate::total 108 +system.mem_ctrl.totQLat 5858750 +system.mem_ctrl.totMemAccLat 12683750 +system.mem_ctrl.totBusLat 1820000 +system.mem_ctrl.avgQLat 16095.47 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 34845.47 +system.mem_ctrl.avgRdBW 398.13 +system.mem_ctrl.avgWrBW 0.00 +system.mem_ctrl.avgRdBWSys 398.13 +system.mem_ctrl.avgWrBWSys 0.00 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 3.11 +system.mem_ctrl.busUtilRead 3.11 +system.mem_ctrl.busUtilWrite 0.00 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 0.00 +system.mem_ctrl.readRowHits 248 +system.mem_ctrl.writeRowHits 0 +system.mem_ctrl.readRowHitRate 68.13 +system.mem_ctrl.writeRowHitRate nan +system.mem_ctrl.avgGap 160373.63 +system.mem_ctrl.pageHitRate 68.13 +system.mem_ctrl_0.actEnergy 292740 +system.mem_ctrl_0.preEnergy 136620 +system.mem_ctrl_0.readEnergy 1170960 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 4302480.000000 +system.mem_ctrl_0.actBackEnergy 2975970 +system.mem_ctrl_0.preBackEnergy 96960 +system.mem_ctrl_0.actPowerDownEnergy 20164320 +system.mem_ctrl_0.prePowerDownEnergy 2885760 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 32025810 +system.mem_ctrl_0.averagePower 547.321100 +system.mem_ctrl_0.totalIdleTime 51467750 +system.mem_ctrl_0.memoryStateTime::IDLE 59000 +system.mem_ctrl_0.memoryStateTime::REF 1820000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 +system.mem_ctrl_0.memoryStateTime::ACT 4902000 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 +system.mem_ctrl_1.actEnergy 535500 +system.mem_ctrl_1.preEnergy 273240 +system.mem_ctrl_1.readEnergy 1428000 +system.mem_ctrl_1.writeEnergy 0 +system.mem_ctrl_1.refreshEnergy 4302480.000000 +system.mem_ctrl_1.actBackEnergy 3735210 +system.mem_ctrl_1.preBackEnergy 150720 +system.mem_ctrl_1.actPowerDownEnergy 22328040 +system.mem_ctrl_1.prePowerDownEnergy 370560 +system.mem_ctrl_1.selfRefreshEnergy 0 +system.mem_ctrl_1.totalEnergy 33123750 +system.mem_ctrl_1.averagePower 566.084895 +system.mem_ctrl_1.totalIdleTime 49870500 +system.mem_ctrl_1.memoryStateTime::IDLE 184000 +system.mem_ctrl_1.memoryStateTime::REF 1820000 +system.mem_ctrl_1.memoryStateTime::SREF 0 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 +system.mem_ctrl_1.memoryStateTime::ACT 6563000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 +system.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.apic_clk_domain.clock 16000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 58513000 +system.cpu.numCycles 58513 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5712 +system.cpu.committedOps 10314 +system.cpu.num_int_alu_accesses 10205 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 221 +system.cpu.num_conditional_control_insts 986 +system.cpu.num_int_insts 10205 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 19296 +system.cpu.num_int_register_writes 7977 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 7020 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+system.membus.pkt_size_system.l2cache.mem_side::total 23296 +system.membus.pkt_size::total 23296 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 364 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 364 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 364 +system.membus.reqLayer2.occupancy 364000 +system.membus.reqLayer2.utilization 0.6 +system.membus.respLayer0.occupancy 1951250 +system.membus.respLayer0.utilization 3.3 ---------- End Simulation Statistics ---------- |