diff options
Diffstat (limited to 'tests/quick/se/03.learning-gem5')
30 files changed, 1936 insertions, 1749 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini index 407eb5e1e..1efeb5f99 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -153,27 +153,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -193,6 +193,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -202,7 +203,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -224,9 +225,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -235,6 +236,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -246,7 +248,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -254,3 +256,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout index 7b44dd5a2..4e8f563cb 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39594 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:47 +gem5 executing on e108600-lin, pid 28091 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 405365000 because target called exit() +Exiting @ tick 461109000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index f8c482cd0..090f011e7 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000415 # Number of seconds simulated -sim_ticks 414695000 # Number of ticks simulated -final_tick 414695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000461 # Number of seconds simulated +sim_ticks 461109000 # Number of ticks simulated +final_tick 461109000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187951 # Simulator instruction rate (inst/s) -host_op_rate 187881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12069868237 # Simulator tick rate (ticks/s) -host_mem_usage 635076 # Number of bytes of host memory used +host_inst_rate 212686 # Simulator instruction rate (inst/s) +host_op_rate 212584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15184120914 # Simulator tick rate (ticks/s) +host_mem_usage 634004 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory @@ -26,63 +26,63 @@ system.mem_ctrl.num_reads::cpu.data 1190 # Nu system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 62339792 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 21326517 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 83666309 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 62339792 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 62339792 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16146807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16146807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 62339792 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 37473324 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 99813116 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 56064835 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 19179847 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 75244682 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 56064835 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 56064835 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 14521512 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 14521512 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 56064835 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 33701359 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 89766194 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 7654 # Number of read requests accepted system.mem_ctrl.writeReqs 865 # Number of write requests accepted system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 478016 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 11840 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 746 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 752 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 766 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 764 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 249 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 1431 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 91 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 26 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 20 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 414618000 # Total gap between requests +system.mem_ctrl.totGap 461032000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 7469 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,12 +146,12 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 6 # What write queue length does an incoming req see @@ -193,87 +193,95 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 765 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 630.044444 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 420.142008 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 402.263677 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 142 18.56% 18.56% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 72 9.41% 27.97% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 39 5.10% 33.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 50 6.54% 39.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 49 6.41% 46.01% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 26 3.40% 49.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 3.53% 52.94% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 39 5.10% 58.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 321 41.96% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 765 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 766 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 629.556136 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 420.481555 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 399.288519 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 144 18.80% 18.80% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 67 8.75% 27.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 42 5.48% 33.03% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 49 6.40% 39.43% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 40 5.22% 44.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 39 5.09% 49.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 38 4.96% 54.70% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 34 4.44% 59.14% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 313 40.86% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 766 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1155.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1053.155116 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 490.786070 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1343 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1728-1791 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1237 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1086.549947 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 686.122730 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1152-1279 2 33.33% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2304-2431 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 26666250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 166710000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 37345000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3570.26 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 73323250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 213217000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9827.54 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22320.26 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1152.69 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 14.82 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 83.68 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.15 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28577.54 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1035.56 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 13.32 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 75.25 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 14.52 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.12 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.01 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.09 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 22.92 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 6707 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 73.95 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48669.80 # Average gap between requests -system.mem_ctrl.pageHitRate 89.55 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3409560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1860375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37159200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 187920 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 262129320 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 17820750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 349520805 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 846.438251 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 26708250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 13780000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 372456750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 2373840 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1295250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 20833800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 434160 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 231001335 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 45144000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 328036065 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 794.350717 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 73389500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 13780000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 325838500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.avgWrQLen 23.97 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 6701 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 86 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.81 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 76.11 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 54118.09 # Average gap between requests +system.mem_ctrl.pageHitRate 89.61 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3184440 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1681185 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 34164900 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 130500 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 65335680 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1899360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 128211240 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 12180000 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 283051065 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 613.847162 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 312833500 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 882000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 31715250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 132053500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 281118250 # Time in different power states +system.mem_ctrl_1.actEnergy 2313360 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1225785 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 19099500 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 370620 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 35649120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 44402430 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1287360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 129142620 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 18055680 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 8894220 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 260440695 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 564.812507 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 359701750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 1420000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 15098000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 30156500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 47020500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 84176750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 283237250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -307,8 +315,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 414695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 414695 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 461109000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 461109 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -327,7 +335,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 414695 # Number of busy cycles +system.cpu.num_busy_cycles 461109 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -372,7 +380,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7654 # Transaction distribution system.membus.trans_dist::ReadResp 7653 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution @@ -396,10 +404,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8519 # Request fanout histogram system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 14691750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3578000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 14690000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 3572750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini index f8108d4cd..5a1f94c78 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -151,7 +151,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -275,7 +275,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -320,27 +320,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -360,6 +360,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -369,7 +370,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -391,9 +392,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -402,6 +403,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -413,7 +415,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -421,3 +423,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout index 7505aca67..2e75b8af5 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39597 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28074 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 61470000 because target called exit() +Exiting @ tick 64758000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 1f58ca472..47755a477 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000062 # Number of seconds simulated -sim_ticks 62213000 # Number of ticks simulated -final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000065 # Number of seconds simulated +sim_ticks 64758000 # Number of ticks simulated +final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 276862 # Simulator instruction rate (inst/s) -host_op_rate 276760 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2667377590 # Simulator tick rate (ticks/s) -host_mem_usage 639424 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 560678 # Simulator instruction rate (inst/s) +host_op_rate 559951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5612828222 # Simulator tick rate (ticks/s) +host_mem_usage 638096 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61962000 # Total gap between requests +system.mem_ctrl.totGap 64501000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,80 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation +system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 138928.25 # Average gap between requests -system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 144621.08 # Average gap between requests +system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states +system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -284,8 +294,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 62213 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 64758 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -304,7 +314,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 62213 # Number of busy cycles +system.cpu.num_busy_cycles 64758 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -343,23 +353,23 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -376,14 +386,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -400,14 +410,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,14 +432,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -438,31 +448,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses system.cpu.icache.tags.data_accesses 13209 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits @@ -475,12 +485,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses @@ -493,12 +503,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,31 +521,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -563,28 +573,28 @@ system.l2bus.snoop_fanout::total 449 # Re system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4534 # Number of tag accesses system.l2cache.tags.data_accesses 4534 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -602,17 +612,17 @@ system.l2cache.demand_misses::total 446 # nu system.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.l2cache.overall_misses::cpu.data 168 # number of overall misses system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) @@ -635,17 +645,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,17 +673,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses @@ -685,24 +695,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -725,7 +735,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini index 6eea99b33..2d26791e9 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -166,7 +166,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -271,27 +271,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -311,6 +311,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -320,7 +321,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -342,9 +343,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -353,6 +354,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -364,7 +366,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -372,3 +374,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout index eb0348157..40266a5d8 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:05:26 -gem5 executing on e108600-lin, pid 24207 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:23 +gem5 executing on e108600-lin, pid 17594 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 325849000 because target called exit() +Exiting @ tick 372284000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index 670cfd0c1..afb55617d 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000333 # Number of seconds simulated -sim_ticks 332645000 # Number of ticks simulated -final_tick 332645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000372 # Number of seconds simulated +sim_ticks 372284000 # Number of ticks simulated +final_tick 372284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141116 # Simulator instruction rate (inst/s) -host_op_rate 163173 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9403646091 # Simulator tick rate (ticks/s) -host_mem_usage 651444 # Number of bytes of host memory used +host_inst_rate 131983 # Simulator instruction rate (inst/s) +host_op_rate 152589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9840410910 # Simulator tick rate (ticks/s) +host_mem_usage 650048 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory @@ -26,16 +26,16 @@ system.mem_ctrl.num_reads::cpu.data 1061 # Nu system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 60448827 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14045003 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 74493830 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 60448827 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 60448827 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 11110944 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 11110944 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 60448827 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25155947 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 85604774 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 54012528 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 12549559 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 66562087 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 54012528 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 54012528 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 9927905 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 9927905 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 54012528 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 22477463 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 76489992 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6089 # Number of read requests accepted system.mem_ctrl.writeReqs 936 # Number of write requests accepted system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue @@ -82,7 +82,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 332568000 # Total gap between requests +system.mem_ctrl.totGap 372207000 # Total gap between requests system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) @@ -193,20 +193,20 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 498 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 770.698795 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 632.685353 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 340.090332 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 21 4.22% 4.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 40 8.03% 12.25% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 36 7.23% 19.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 28 5.62% 25.10% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 23 4.62% 29.72% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 25 5.02% 34.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 24 4.82% 39.56% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 28 5.62% 45.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 273 54.82% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 498 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 514 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 749.322957 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 608.037375 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 344.826867 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 514 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes @@ -221,58 +221,68 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 17899250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 130193000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 57609500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 169903250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 2988.69 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 9619.22 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21738.69 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1152.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 12.31 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 74.51 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 11.11 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28369.22 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1029.58 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 11.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 66.57 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 9.93 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.10 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.00 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.13 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.04 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5487 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 5473 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.62 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 91.38 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47340.64 # Average gap between requests -system.mem_ctrl.pageHitRate 91.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2812320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1534500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 38048400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 52983.20 # Average gap between requests +system.mem_ctrl.pageHitRate 91.19 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2727480 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1438305 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 35364420 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 216770715 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 6219750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 286745205 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 876.139742 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7265500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 309110750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7893600 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 188416350 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 31092000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 250498080 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 765.387945 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 51038750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 265729250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 64999380 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1619520 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 98643060 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 3533760 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 237214005 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 637.183891 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 225396250 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 954000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 133713750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 # Time in different power states +system.mem_ctrl_1.actEnergy 971040 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 512325 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 7389900 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 334080 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 27658800.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 18607080 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 791520 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 128152530 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 7837920 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 7265340 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 199520535 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 535.934929 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 328663750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 770000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 11706000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 27971000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 30385000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -302,7 +312,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +342,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +372,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,8 +403,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 332645000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 332645 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 372284000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 372284 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -415,7 +425,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 332644.999000 # Number of busy cycles +system.cpu.num_busy_cycles 372283.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -460,7 +470,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6078 # Transaction distribution system.membus.trans_dist::ReadResp 6088 # Transaction distribution system.membus.trans_dist::WriteReq 925 # Transaction distribution @@ -487,10 +497,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7025 # Request fanout histogram system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 11412500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3325250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 11413250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3327250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini index ad9e5a13b..733323a88 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -102,7 +102,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -198,7 +198,7 @@ sys=system [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -258,7 +258,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -393,7 +393,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -438,27 +438,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -478,6 +478,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -487,7 +488,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -509,9 +510,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -520,6 +521,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -531,7 +533,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -539,3 +541,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout index a3411dc5e..7a7d67b77 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:03:01 -gem5 executing on e108600-lin, pid 24156 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:17 +gem5 executing on e108600-lin, pid 17589 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 49855000 because target called exit() +Exiting @ tick 52453000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 005f27b4b..3eb7c70d8 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000050 # Number of seconds simulated -sim_ticks 50074000 # Number of ticks simulated -final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000052 # Number of seconds simulated +sim_ticks 52453000 # Number of ticks simulated +final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207988 # Simulator instruction rate (inst/s) -host_op_rate 240459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2085706484 # Simulator tick rate (ticks/s) -host_mem_usage 655032 # Number of bytes of host memory used +host_inst_rate 234245 # Simulator instruction rate (inst/s) +host_op_rate 270642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2457731659 # Simulator tick rate (ticks/s) +host_mem_usage 654144 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14400 # Nu system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 351 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 49975000 # Total gap between requests +system.mem_ctrl.totGap 52348000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,71 +187,81 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation +system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 142378.92 # Average gap between requests -system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.mem_ctrl.avgGap 149139.60 # Average gap between requests +system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states +system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states +system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states +system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -281,7 +291,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -311,7 +321,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +351,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -372,8 +382,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 50074 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 52453 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -394,7 +404,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles +system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -433,23 +443,23 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits @@ -470,14 +480,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -498,14 +508,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,14 +530,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -536,31 +546,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits @@ -573,12 +583,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -591,12 +601,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,31 +619,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -661,28 +671,28 @@ system.l2bus.snoop_fanout::total 391 # Re system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3959 # Number of tag accesses system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits @@ -703,17 +713,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -736,17 +746,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -764,17 +774,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -786,24 +796,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -826,7 +836,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 351 # Request fanout histogram system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 1866250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini index de0268a39..3f1a37472 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -155,27 +155,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -195,6 +195,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -204,7 +205,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -226,9 +227,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -237,6 +238,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -248,7 +250,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -256,3 +258,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout index 194a454d5..05f1fc1ff 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:23:13 -gem5 started Jul 21 2016 14:23:48 -gem5 executing on e108600-lin, pid 13288 +gem5 compiled Oct 13 2016 20:36:34 +gem5 started Oct 13 2016 20:36:59 +gem5 executing on e108600-lin, pid 36838 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 368887000 because target called exit() +Exiting @ tick 423127000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 60c6ac279..b290494a3 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000377 # Number of seconds simulated -sim_ticks 376893000 # Number of ticks simulated -final_tick 376893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000423 # Number of seconds simulated +sim_ticks 423127000 # Number of ticks simulated +final_tick 423127000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173660 # Simulator instruction rate (inst/s) -host_op_rate 173583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11593149844 # Simulator tick rate (ticks/s) -host_mem_usage 632708 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 243919 # Simulator instruction rate (inst/s) +host_op_rate 243782 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18277293383 # Simulator tick rate (ticks/s) +host_mem_usage 631884 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1135 # Nu system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 59879064 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 11411727 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 71290791 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 59879064 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 59879064 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9554436 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9554436 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 59879064 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 20966163 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 80845227 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 53336232 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 10164797 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 63501029 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 53336232 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 53336232 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 8510447 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 8510447 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 53336232 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 18675244 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 72011476 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6778 # Number of read requests accepted system.mem_ctrl.writeReqs 901 # Number of write requests accepted system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 428096 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 427712 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 811 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 808 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts @@ -55,14 +55,14 @@ system.mem_ctrl.perBankRdBursts::3 0 # Pe system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 519 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 516 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 350 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 1429 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 49 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts @@ -71,18 +71,18 @@ system.mem_ctrl.perBankWrBursts::3 0 # Pe system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 2 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 30 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 14 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 376816000 # Total gap between requests +system.mem_ctrl.totGap 423050000 # Total gap between requests system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6689 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6683 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -155,9 +155,9 @@ system.mem_ctrl.wrQLenPdf::22 5 # Wh system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see @@ -193,26 +193,26 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 838 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 513.374702 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 298.080754 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 413.335022 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 263 31.38% 31.38% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 85 10.14% 41.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 42 5.01% 46.54% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 43 5.13% 51.67% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 44 5.25% 56.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 53 6.32% 63.25% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 15 1.79% 65.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 22 2.63% 67.66% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 271 32.34% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 838 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 846 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 508.141844 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 296.960814 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 409.521445 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 262 30.97% 30.97% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 81 9.57% 40.54% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 50 5.91% 46.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 56 6.62% 53.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 41 4.85% 57.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 45 5.32% 63.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 28 3.31% 66.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 22 2.60% 69.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 261 30.85% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 846 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1522.250000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1505.224255 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 263.075876 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1343 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1385.500000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1320.719140 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 457.578044 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::768-831 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes @@ -221,57 +221,67 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 28198000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 153616750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 33445000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 4215.58 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 74613750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 199920000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 33415000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 11164.71 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22965.58 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1135.86 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 10.87 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 71.30 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.55 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 29914.71 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1010.84 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 9.68 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 63.51 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 8.51 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.96 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.87 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 7.97 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 7.90 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.23 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5853 # Number of row buffer hits during reads +system.mem_ctrl.avgWrQLen 22.62 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5839 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 57 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 87.50 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 63.33 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 49070.97 # Average gap between requests -system.mem_ctrl.pageHitRate 87.18 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 1020600 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 556875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 141780375 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 100031250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 276658020 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 739.727326 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 165010500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 196602500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 42939000 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 362880 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 252188235 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 3192750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 331284930 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 885.747138 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2538750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 12480000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 359011750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.readRowHitRate 87.37 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 61.29 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 55091.81 # Average gap between requests +system.mem_ctrl.pageHitRate 87.01 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 985320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 519915 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 8061060 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 26100 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 21232500 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1932000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 84890100 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 43723680 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 22684200 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 217245435 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 513.427832 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 369366500 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 2976000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 14106000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 71507250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 113857500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 34569250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 186111000 # Time in different power states +system.mem_ctrl_1.actEnergy 5090820 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 2690655 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 39648420 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 307980 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 77391750 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1169760 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 113578770 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 273562635 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 646.525303 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 250424500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 900000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 14040000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 1291250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 157762500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 249133250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -291,8 +301,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 376893000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 376893 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 423127000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 423127 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -311,7 +321,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 376893 # Number of busy cycles +system.cpu.num_busy_cycles 423127 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -356,7 +366,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6778 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution @@ -380,10 +390,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7679 # Request fanout histogram system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12853500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 12855500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3550250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini index cf4a132b7..4bc508e65 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -151,7 +151,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -277,7 +277,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -322,27 +322,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -362,6 +362,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -371,7 +372,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -393,9 +394,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -404,6 +405,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -415,7 +417,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -423,3 +425,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout index 760ae9b2e..26dbf1e79 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:23:13 -gem5 started Jul 21 2016 14:23:48 -gem5 executing on e108600-lin, pid 13287 +gem5 compiled Oct 13 2016 20:36:34 +gem5 started Oct 13 2016 20:36:59 +gem5 executing on e108600-lin, pid 36839 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 58892000 because target called exit() +Exiting @ tick 62333000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 27ea6dc01..3bd6c6ff6 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 59115000 # Number of ticks simulated -final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 62333000 # Number of ticks simulated +final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219311 # Simulator instruction rate (inst/s) -host_op_rate 219196 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2295881155 # Simulator tick rate (ticks/s) -host_mem_usage 637060 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 499257 # Simulator instruction rate (inst/s) +host_op_rate 498740 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5505866075 # Simulator tick rate (ticks/s) +host_mem_usage 635976 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 18752 # Nu system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 300835833 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 140663854 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 441499687 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 300835833 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 300835833 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 300835833 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 140663854 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 441499687 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 430 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58984000 # Total gap between requests +system.mem_ctrl.totGap 62196000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,81 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 241.840708 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 173.064480 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 223.138673 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 41 36.28% 62.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 20 17.70% 80.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.08% 87.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.77% 93.81% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 3 2.65% 96.46% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 0.88% 97.35% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation +system.mem_ctrl.totQLat 6850250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 14912750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 15930.81 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 34680.81 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 441.50 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 441.50 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.45 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.45 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 316 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 73.49 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137172.09 # Average gap between requests -system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 144641.86 # Average gap between requests +system.mem_ctrl.pageHitRate 73.49 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 192780 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 671160 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 2176830 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 210240 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 19527630 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 3815040 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 1573140 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 33182610 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 532.337778 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 56494000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 323000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 2086000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 4253250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 9935000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 2911750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 42824000 # Time in different power states +system.mem_ctrl_1.actEnergy 621180 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 2399040 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 5632170 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 168480 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 22617030 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 36749505 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 587.463363 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 49768000 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 176000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1843250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 167500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 10545750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 49600500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -270,8 +281,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59115 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62333000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 62333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -290,7 +301,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 59115 # Number of busy cycles +system.cpu.num_busy_cycles 62333 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -329,23 +340,23 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.045434 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.045434 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.084029 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.084029 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -362,14 +373,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10089000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10089000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5605000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5605000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15694000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15694000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15694000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15694000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -386,14 +397,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 112100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 112100 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 114554.744526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 114554.744526 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15420000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15420000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15420000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15420000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -424,31 +435,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 110100 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 110100 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 109.768952 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 109.768952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.428785 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.428785 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses system.cpu.icache.tags.data_accesses 11583 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits @@ -461,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst 297 # n system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses system.cpu.icache.overall_misses::total 297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32151000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32151000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32151000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32151000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32151000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32151000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses @@ -479,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 108252.525253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 108252.525253 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,31 +508,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297 system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31557000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31557000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31557000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31557000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31557000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31557000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -547,30 +558,30 @@ system.l2bus.snoop_fanout::min_value 0 # Re system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram system.l2bus.snoop_fanout::total 434 # Request fanout histogram system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 215.766788 # Cycle average of tags in use system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 129.675199 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 86.091590 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031659 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.021018 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.052677 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4654 # Number of tag accesses system.l2cache.tags.data_accesses 4654 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits @@ -588,17 +599,17 @@ system.l2cache.demand_misses::total 430 # nu system.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 430 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 5355000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 5355000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 30582000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9654000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 40236000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 30582000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 15009000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 45591000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 30582000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 15009000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 45591000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) @@ -621,17 +632,17 @@ system.l2cache.demand_miss_rate::total 0.990783 # mi system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 107100 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 107100 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 106025.581395 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 106025.581395 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +660,17 @@ system.l2cache.demand_mshr_misses::total 430 # nu system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4355000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 4355000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 24722000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7914000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 32636000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 24722000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 12269000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 36991000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 24722000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 12269000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 36991000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses @@ -671,24 +682,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.990783 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87100 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 87100 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -711,7 +722,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 430 # Request fanout histogram system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 2298250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini index a434b8376..d1ab85628 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -152,27 +152,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -192,6 +192,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -201,7 +202,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -223,9 +224,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -234,6 +235,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -245,7 +247,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -253,3 +255,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout index 9b1207098..4568a6760 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:37 -gem5 executing on e108600-lin, pid 38687 +gem5 compiled Oct 13 2016 20:43:27 +gem5 started Oct 13 2016 20:47:16 +gem5 executing on e108600-lin, pid 17418 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 333033000 because target called exit() +Hello World!Exiting @ tick 380341000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 9a120d100..ba7428ffa 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000340 # Number of seconds simulated -sim_ticks 340278000 # Number of ticks simulated -final_tick 340278000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000380 # Number of seconds simulated +sim_ticks 380341000 # Number of ticks simulated +final_tick 380341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140763 # Simulator instruction rate (inst/s) -host_op_rate 140716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8627820590 # Simulator tick rate (ticks/s) -host_mem_usage 633396 # Number of bytes of host memory used +host_inst_rate 148243 # Simulator instruction rate (inst/s) +host_op_rate 148143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10150108269 # Simulator tick rate (ticks/s) +host_mem_usage 632328 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory @@ -26,26 +26,26 @@ system.mem_ctrl.num_reads::cpu.data 718 # Nu system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 65722733 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 13635909 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 79358642 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 65722733 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 65722733 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 14884888 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 14884888 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 65722733 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 28520798 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 94243530 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 58799866 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 12199579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 70999445 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 58799866 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 58799866 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 13316997 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 13316997 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 58799866 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 25516576 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 84316442 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6310 # Number of read requests accepted system.mem_ctrl.writeReqs 673 # Number of write requests accepted system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 397824 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 397760 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 548 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts @@ -53,7 +53,7 @@ system.mem_ctrl.perBankRdBursts::1 84 # Pe system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 1005 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 1004 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 875 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts @@ -69,7 +69,7 @@ system.mem_ctrl.perBankWrBursts::1 0 # Pe system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 17 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 16 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 42 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 19 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts @@ -77,12 +77,12 @@ system.mem_ctrl.perBankWrBursts::9 5 # Pe system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 4 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 9 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 10 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 340201000 # Total gap between requests +system.mem_ctrl.totGap 380264000 # Total gap between requests system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 604 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6216 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6215 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -193,24 +193,24 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 569 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 706.474517 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 522.857650 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 386.052257 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 51 8.96% 8.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 75 13.18% 22.14% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 39 6.85% 29.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 23 4.04% 33.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 22 3.87% 36.91% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 18 3.16% 40.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 19 3.34% 43.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 24 4.22% 47.63% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 298 52.37% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 569 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 575 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 700.438261 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 528.229400 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 375.888489 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 575 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 772.333333 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 643.216539 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 524.537383 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes @@ -222,60 +222,70 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 19583750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 136133750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 31080000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3150.54 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 59680000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 176211250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 31075000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9602.57 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21900.54 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1169.11 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 18.06 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 79.37 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 14.88 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28352.57 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1045.80 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 16.15 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 71.01 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 13.32 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.27 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.13 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.14 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.30 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.17 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5657 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 82 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.01 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 65.60 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48718.46 # Average gap between requests -system.mem_ctrl.pageHitRate 90.51 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2653560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1447875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 30108000 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 505440 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 217242675 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 10477500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 284303130 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 848.491929 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 15805250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 11180000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 311151750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 1617840 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 882750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 17635800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 116640 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 174520890 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 47944500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 264586500 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 789.680799 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 79696000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11180000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 245540000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.avgWrQLen 23.12 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5650 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 83 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 90.91 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 66.40 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 54455.68 # Average gap between requests +system.mem_ctrl.pageHitRate 90.43 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2598960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1377585 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 28124460 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 401940 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 55884510 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 903360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 108619200 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 6618240 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 234030975 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 615.318415 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 255286000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 462000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 111848750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 # Time in different power states +system.mem_ctrl_1.actEnergy 1527960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 804540 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 16243500 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 99180 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 28273440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 35538930 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1997760 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 96272430 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 16892160 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 11758020 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 209407920 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 550.579039 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 297220000 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 3473000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 11978000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 42087750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 67670000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 340278000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 340278 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 380341000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 380341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -294,7 +304,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 340277.999000 # Number of busy cycles +system.cpu.num_busy_cycles 380340.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -339,7 +349,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6310 # Transaction distribution system.membus.trans_dist::ReadResp 6309 # Transaction distribution system.membus.trans_dist::WriteReq 673 # Transaction distribution @@ -363,10 +373,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6983 # Request fanout histogram system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer0.occupancy 12692500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2298500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 12691750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2300750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini index 24d190659..d90641228 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -151,7 +151,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -274,7 +274,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -319,27 +319,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -359,6 +359,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -368,7 +369,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -390,9 +391,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -401,6 +402,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -412,7 +414,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -420,3 +422,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout index 362a2e4dd..95530f5be 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38678 +gem5 compiled Oct 13 2016 20:43:27 +gem5 started Oct 13 2016 20:45:43 +gem5 executing on e108600-lin, pid 17392 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 53334000 because target called exit() +Hello World!Exiting @ tick 56511000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 563f4d9b3..898894976 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000054 # Number of seconds simulated -sim_ticks 53605000 # Number of ticks simulated -final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56511000 # Number of ticks simulated +final_tick 56511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205629 # Simulator instruction rate (inst/s) -host_op_rate 205519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1984690430 # Simulator tick rate (ticks/s) -host_mem_usage 637752 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 292382 # Simulator instruction rate (inst/s) +host_op_rate 292023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2971184542 # Simulator tick rate (ticks/s) +host_mem_usage 636424 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 16448 # Nu system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 291058378 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 155155633 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 446214011 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 291058378 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 291058378 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 291058378 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 155155633 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 446214011 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 394 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 53508000 # Total gap between requests +system.mem_ctrl.totGap 56394000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,77 +187,83 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 98 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 248.816327 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 183.748429 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 196.431638 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 98 # Bytes accessed per row activation +system.mem_ctrl.totQLat 5793000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 13180500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 14703.05 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 33453.05 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 446.21 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 446.21 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.49 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.49 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 292 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 74.11 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 135807.11 # Average gap between requests -system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 143131.98 # Average gap between requests +system.mem_ctrl.pageHitRate 74.11 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 421260 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 216315 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1756440 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 4075500 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 122880 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 21123630 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 357120 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 32375625 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 572.905837 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 47002000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 71000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 7357750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 # Time in different power states +system.mem_ctrl_1.actEnergy 307020 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 155595 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1056720 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 2785590 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 293760 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 20523420 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 1777920 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 31202505 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 552.146785 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 49582750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 557000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 4495750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 53605 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 56511000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 56511 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -276,7 +282,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles +system.cpu.num_busy_cycles 56510.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -315,23 +321,23 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 83.847801 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.081883 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.081883 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits @@ -348,14 +354,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6576000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8937000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15513000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15513000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15513000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15513000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -372,14 +378,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 112413.043478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 112413.043478 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,14 +400,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6464000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6464000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15237000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15237000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15237000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15237000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses @@ -410,31 +416,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 98.324434 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 98.324434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.384080 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.384080 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses system.cpu.icache.tags.data_accesses 11443 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits @@ -447,12 +453,12 @@ system.cpu.icache.demand_misses::cpu.inst 259 # n system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27828000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27828000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27828000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27828000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27828000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27828000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses @@ -465,12 +471,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 107444.015444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 107444.015444 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,31 +489,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 259 system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27310000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27310000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27310000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27310000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27310000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27310000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -533,30 +539,30 @@ system.l2bus.snoop_fanout::min_value 0 # Re system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 397 # Request fanout histogram system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 201.052259 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 118.133782 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 82.918477 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.028841 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.020244 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.049085 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4130 # Number of tag accesses system.l2cache.tags.data_accesses 4130 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits @@ -577,17 +583,17 @@ system.l2cache.demand_misses::total 394 # nu system.l2cache.overall_misses::cpu.inst 257 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8527000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8527000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26487000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 6273000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 32760000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 26487000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 14800000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 41287000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 26487000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 14800000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 41287000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) @@ -610,17 +616,17 @@ system.l2cache.demand_miss_rate::total 0.992443 # mi system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 105000 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 104789.340102 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 104789.340102 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,17 +644,17 @@ system.l2cache.demand_mshr_misses::total 394 # nu system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6887000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6887000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21347000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5173000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 26520000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 21347000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 12060000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 33407000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 12060000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 33407000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses @@ -660,24 +666,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.992443 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution system.membus.trans_dist::ReadExResp 82 # Transaction distribution @@ -700,7 +706,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 394 # Request fanout histogram system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 2102500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini index f9a7ceaa3..612b72e20 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -199,27 +199,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -239,6 +239,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -248,7 +249,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -270,9 +271,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -281,6 +282,7 @@ port=system.membus.master[2] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -292,7 +294,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -300,3 +302,10 @@ width=16 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.interrupts.int_master system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout index c68473235..3227a9df4 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18562 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:11:23 +gem5 executing on e108600-lin, pid 17668 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 445082000 because target called exit() +Exiting @ tick 507841000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index 7312a839d..d3b77ec90 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000455 # Number of seconds simulated -sim_ticks 454507000 # Number of ticks simulated -final_tick 454507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000508 # Number of seconds simulated +sim_ticks 507841000 # Number of ticks simulated +final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76712 # Simulator instruction rate (inst/s) -host_op_rate 138489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6101741543 # Simulator tick rate (ticks/s) -host_mem_usage 651776 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 96340 # Simulator instruction rate (inst/s) +host_op_rate 173892 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8558810197 # Simulator tick rate (ticks/s) +host_mem_usage 650468 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory @@ -26,29 +26,29 @@ system.mem_ctrl.num_reads::cpu.data 1084 # Nu system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 128191645 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 15768734 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 143960379 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 128191645 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 128191645 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 15753333 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 15753333 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 128191645 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 31522067 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 159713712 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 114728823 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 14112685 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 128841507 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 114728823 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 114728823 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 14098901 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 14098901 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 114728823 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 28211586 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 142940409 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 8367 # Number of read requests accepted system.mem_ctrl.writeReqs 941 # Number of write requests accepted system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 524736 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10752 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 819 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 273 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts @@ -58,13 +58,13 @@ system.mem_ctrl.perBankRdBursts::6 1103 # Pe system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1055 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 115 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 6 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 10 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts @@ -72,17 +72,17 @@ system.mem_ctrl.perBankWrBursts::4 0 # Pe system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 2 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 53 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 23 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 54 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 34 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 4 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 454381000 # Total gap between requests +system.mem_ctrl.totGap 507709000 # Total gap between requests system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 861 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8199 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,8 +146,8 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see @@ -155,13 +155,13 @@ system.mem_ctrl.wrQLenPdf::22 7 # Wh system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,94 +193,105 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 622.812721 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 426.803074 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 394.306776 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 142 16.73% 16.73% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 69 8.13% 24.85% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 77 9.07% 33.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 63 7.42% 41.34% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 55 6.48% 47.82% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 39 4.59% 52.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 28 3.30% 55.71% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 21 2.47% 58.19% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 355 41.81% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1282.333333 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1020.532539 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 764.587906 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrl.bytesPerActivate::samples 856 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 618.018692 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 421.107711 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 393.969749 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 856 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 29381000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 183112250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 40995000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3583.49 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 82515500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 236378000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 10055.51 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22333.49 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1154.52 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 13.52 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 143.96 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 15.75 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28805.51 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1034.15 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 14.11 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 128.84 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 14.10 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.13 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.02 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.08 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.84 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7356 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 85 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 69.67 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48816.18 # Average gap between requests +system.mem_ctrl.avgWrQLen 23.79 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 7357 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.65 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 54545.44 # Average gap between requests system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3281040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1790250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 40294800 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 248297130 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 53313000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 376511580 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 833.243697 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 86206500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 15080000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 350589750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 23275200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 583200 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 273625650 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 31095000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 362913120 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 803.149454 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 50725000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 15080000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 387261000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_0.actEnergy 3127320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1647030 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37149420 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 52200 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 70559160 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1716480 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 113314290 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 13222080 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 17426520 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 294478260 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 579.862821 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 347720500 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 1584000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15358000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 65707000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 142245250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 # Time in different power states +system.mem_ctrl_1.actEnergy 3034500 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1601490 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 21441420 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 532440 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 51598110 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1155360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 151289970 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 18740160 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 3216240 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 291946650 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 574.877779 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 391695500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 757000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 16646000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 11100000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 98712250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 454507000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 454507 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 507841000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 507841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -301,7 +312,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 454506.999000 # Number of busy cycles +system.cpu.num_busy_cycles 507840.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -346,7 +357,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 8367 # Transaction distribution system.membus.trans_dist::ReadResp 8367 # Transaction distribution system.membus.trans_dist::WriteReq 941 # Transaction distribution @@ -374,10 +385,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 9308 # Request fanout histogram system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 16547250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3431500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.reqLayer2.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 16544750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3432250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini index 1ce461f16..c3a9301a3 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -106,7 +106,7 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -171,7 +171,7 @@ system=system [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -321,7 +321,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -366,27 +366,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -406,6 +406,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -415,7 +416,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -437,9 +438,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -448,6 +449,7 @@ port=system.membus.master[2] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -459,7 +461,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -467,3 +469,10 @@ width=16 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout index cdf63e901..736ff89ea 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18545 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:22 +gem5 executing on e108600-lin, pid 17647 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 55844000 because target called exit() +Exiting @ tick 58513000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index a74924642..bf9b895e3 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000056 # Number of seconds simulated -sim_ticks 56435000 # Number of ticks simulated -final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000059 # Number of seconds simulated +sim_ticks 58513000 # Number of ticks simulated +final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125605 # Simulator instruction rate (inst/s) -host_op_rate 226732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1240265940 # Simulator tick rate (ticks/s) -host_mem_usage 656384 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 325988 # Simulator instruction rate (inst/s) +host_op_rate 588251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3335289412 # Simulator tick rate (ticks/s) +host_mem_usage 654560 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14656 # Nu system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 364 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 56304000 # Total gap between requests +system.mem_ctrl.totGap 58376000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,77 +187,88 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation +system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 154681.32 # Average gap between requests -system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 160373.63 # Average gap between requests +system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states +system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states +system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states +system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56435 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 58513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -278,7 +289,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles +system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -317,23 +328,23 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits @@ -350,14 +361,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) @@ -374,14 +385,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,14 +407,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses @@ -412,31 +423,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits @@ -449,12 +460,12 @@ system.cpu.icache.demand_misses::cpu.inst 235 # n system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses @@ -467,12 +478,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,31 +496,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 235 system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -535,30 +546,30 @@ system.l2bus.snoop_fanout::min_value 0 # Re system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 370 # Request fanout histogram system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3788 # Number of tag accesses system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits @@ -576,17 +587,17 @@ system.l2cache.demand_misses::total 364 # nu system.l2cache.overall_misses::cpu.inst 229 # number of overall misses system.l2cache.overall_misses::cpu.data 135 # number of overall misses system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -609,17 +620,17 @@ system.l2cache.demand_miss_rate::total 0.983784 # mi system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,17 +648,17 @@ system.l2cache.demand_mshr_misses::total 364 # nu system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -659,24 +670,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.983784 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution @@ -701,7 +712,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 364 # Request fanout histogram system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |