diff options
Diffstat (limited to 'tests/quick/se/04.gpu')
3 files changed, 577 insertions, 532 deletions
diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini index bd0cc03e4..28bcdeb18 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini @@ -420,7 +420,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello +executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello gid=100 input=cin kvmInSE=false @@ -476,6 +476,7 @@ n_wf=8 num_SIMDs=4 num_global_mem_pipes=1 num_shared_mem_pipes=1 +out_of_order_data_delivery=false p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 @@ -808,6 +809,7 @@ n_wf=8 num_SIMDs=4 num_global_mem_pipes=1 num_shared_mem_pipes=1 +out_of_order_data_delivery=false p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 @@ -1152,7 +1154,7 @@ translation_port=system.dispatcher_coalescer.slave[0] [system.cpu2.cl_driver] type=ClDriver -codefile=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm eventq_index=0 filename=hsa diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout index c30fce800..6eab10f97 100755 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ru gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 21:24:38 -gem5 started Oct 13 2016 21:24:54 -gem5 executing on e108600-lin, pid 29892 -command line: /work/curdun01/gem5-external.hg/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO +gem5 compiled Nov 29 2016 19:21:01 +gem5 started Nov 29 2016 19:21:23 +gem5 executing on zizzer, pid 11568 +command line: /z/powerjg/gem5-upstream/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -Using GPU kernel code file(s) /arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm Global frequency set at 1000000000000 ticks per second Forcing maxCoalescedReqs to 32 (TLB assoc.) Forcing maxCoalescedReqs to 32 (TLB assoc.) @@ -20,4 +20,4 @@ info: Entering event queue @ 0. Starting simulation... keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 the gpu says: elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe -Exiting @ tick 668137500 because target called exit() +Exiting @ tick 667407500 because target called exit() diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index 738fdd2f1..a879bebf2 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000668 # Number of seconds simulated -sim_ticks 668137500 # Number of ticks simulated -final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000667 # Number of seconds simulated +sim_ticks 667407500 # Number of ticks simulated +final_tick 667407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245703 # Simulator instruction rate (inst/s) -host_op_rate 505252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2451366703 # Simulator tick rate (ticks/s) -host_mem_usage 1323744 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 72185 # Simulator instruction rate (inst/s) +host_op_rate 148440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 719412350 # Simulator tick rate (ticks/s) +host_mem_usage 1308600 # Number of bytes of host memory used +host_seconds 0.93 # Real time elapsed on the host sim_insts 66963 # Number of instructions simulated sim_ops 137705 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory -system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory -system.mem_ctrls.bw_read::dir_cntrl0 148568221 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 148568221 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::dir_cntrl0 148568221 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 148568221 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1551 # Number of read requests accepted +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::dir_cntrl0 99136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 99136 # Number of bytes read from this memory +system.mem_ctrls.num_reads::dir_cntrl0 1549 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1549 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::dir_cntrl0 148538936 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 148538936 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 148538936 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 148538936 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1549 # Number of read requests accepted system.mem_ctrls.writeReqs 0 # Number of write requests accepted -system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.readBursts 1549 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadDRAM 99136 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side +system.mem_ctrls.bytesReadSys 99136 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 91 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts @@ -68,14 +68,14 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 667904000 # Total gap between requests +system.mem_ctrls.totGap 667174000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1549 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) @@ -83,13 +83,13 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1540 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -180,28 +180,28 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 203.636364 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 145.087483 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 194.740960 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 203.371901 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 144.930715 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 194.713066 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 167 34.50% 71.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 64 13.22% 84.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 168 34.71% 71.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 63 13.02% 84.30% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 20 4.13% 94.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 2.07% 96.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 3.93% 94.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 11 2.27% 96.49% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation -system.mem_ctrls.totQLat 31097995 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 60179245 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 20050.29 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 31625750 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 60669500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 7745000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20416.88 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38800.29 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 148.57 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 39166.88 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 148.54 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 148.57 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 148.54 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage @@ -209,94 +209,94 @@ system.mem_ctrls.busUtilRead 1.16 # Da system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads +system.mem_ctrls.readRowHits 1060 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 68.43 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrls.avgGap 430627.98 # Average gap between requests -system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined +system.mem_ctrls.avgGap 430712.72 # Average gap between requests +system.mem_ctrls.pageHitRate 68.43 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4890900 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4876620 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 18618480 # Energy for active background per rank (pJ) +system.mem_ctrls_0.actBackEnergy 18588840 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 210199470 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 42511680 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 15622140 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 347158215 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 519.590975 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 622801252 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.actPowerDownEnergy 210561990 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 42231360 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 15446940 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 347021295 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 519.954143 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 622134250 # Total Idle time Per DRAM Rank system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 51287000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 110705750 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 21255248 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 460983502 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 50557000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 109975750 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 21192250 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 461776500 # Time in different power states system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 21589320 # Energy for active background per rank (pJ) +system.mem_ctrls_1.actBackEnergy 21584190 # Energy for active background per rank (pJ) system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 243172830 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 28283040 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 3067740 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 359152785 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 537.543223 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 616852750 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.actPowerDownEnergy 243510840 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 28002720 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 2892540 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 359030145 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 537.947423 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 616133750 # Total Idle time Per DRAM Rank system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 10481250 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 73643500 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 27629000 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 533297750 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 9751250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 72913500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 27618000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 534038750 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks -system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory -system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory -system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory -system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 2856 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 2856 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::total 822304 # Number of bytes read from this memory system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory -system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory -system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory -system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 1576 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 1576 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::total 699912 # Number of instructions bytes read from this memory system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory -system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory -system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory -system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 547 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 547 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::total 104875 # Number of read requests responded to by this memory system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory -system.ruby.phys_mem.bw_read::cpu0.inst 1042839236 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu0.data 179352304 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::total 1232009878 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu0.inst 1042839236 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::total 1048826028 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu0.data 108910217 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::total 109676526 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu0.inst 1042839236 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu0.data 288262521 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::total 1341686404 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.phys_mem.bw_read::cpu0.inst 1043979877 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu0.data 179548477 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::total 1232086843 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu0.inst 1043979877 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::total 1048702629 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu0.data 109029341 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::total 109796489 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.inst 1043979877 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.data 288577818 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::total 1341883332 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 114203 @@ -308,10 +308,10 @@ system.ruby.outstanding_req_hist_seqr::total 114203 system.ruby.outstanding_req_hist_coalsr::bucket_size 1 system.ruby.outstanding_req_hist_coalsr::max_bucket 9 system.ruby.outstanding_req_hist_coalsr::samples 27 -system.ruby.outstanding_req_hist_coalsr::mean 1.629630 -system.ruby.outstanding_req_hist_coalsr::gmean 1.438746 -system.ruby.outstanding_req_hist_coalsr::stdev 0.926040 -system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_coalsr::mean 2.074074 +system.ruby.outstanding_req_hist_coalsr::gmean 1.820631 +system.ruby.outstanding_req_hist_coalsr::stdev 1.071517 +system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 10 37.04% 37.04% | 9 33.33% 70.37% | 4 14.81% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist_coalsr::total 27 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 @@ -324,10 +324,10 @@ system.ruby.latency_hist_seqr::total 114203 system.ruby.latency_hist_coalsr::bucket_size 64 system.ruby.latency_hist_coalsr::max_bucket 639 system.ruby.latency_hist_coalsr::samples 27 -system.ruby.latency_hist_coalsr::mean 171 -system.ruby.latency_hist_coalsr::gmean 22.942606 -system.ruby.latency_hist_coalsr::stdev 184.818206 -system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_coalsr::mean 175.777778 +system.ruby.latency_hist_coalsr::gmean 29.086037 +system.ruby.latency_hist_coalsr::stdev 175.084668 +system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_coalsr::total 27 system.ruby.hit_latency_hist_seqr::bucket_size 64 system.ruby.hit_latency_hist_seqr::max_bucket 639 @@ -348,10 +348,10 @@ system.ruby.miss_latency_hist_seqr::total 112668 system.ruby.miss_latency_hist_coalsr::bucket_size 64 system.ruby.miss_latency_hist_coalsr::max_bucket 639 system.ruby.miss_latency_hist_coalsr::samples 27 -system.ruby.miss_latency_hist_coalsr::mean 171 -system.ruby.miss_latency_hist_coalsr::gmean 22.942606 -system.ruby.miss_latency_hist_coalsr::stdev 184.818206 -system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_coalsr::mean 175.777778 +system.ruby.miss_latency_hist_coalsr::gmean 29.086037 +system.ruby.miss_latency_hist_coalsr::stdev 175.084668 +system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_coalsr::total 27 system.ruby.L1Cache.incomplete_times_seqr 112609 system.ruby.L2Cache.incomplete_times_seqr 59 @@ -377,27 +377,27 @@ system.cp_cntrl0.L2cache.demand_misses 1535 # Nu system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes -system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads +system.cp_cntrl0.L2cache.num_tag_array_reads 12057 # number of tag array reads system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes -system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu0.clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu0.workload.num_syscalls 21 # Number of system calls system.cpu0.numPwrStateTransitions 2 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2825501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2095501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 2825501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2825501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 2095501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 2095501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2825501 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 1336275 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2095501 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 1334815 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 66963 # Number of instructions committed @@ -417,10 +417,10 @@ system.cpu0.num_cc_register_writes 42183 # nu system.cpu0.num_mem_refs 27198 # number of memory refs system.cpu0.num_load_insts 16684 # Number of load instructions system.cpu0.num_store_insts 10514 # Number of store instructions -system.cpu0.num_idle_cycles 5651.003992 # Number of idle cycles -system.cpu0.num_busy_cycles 1330623.996008 # Number of busy cycles -system.cpu0.not_idle_fraction 0.995771 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.004229 # Percentage of idle cycles +system.cpu0.num_idle_cycles 4191.003994 # Number of idle cycles +system.cpu0.num_busy_cycles 1330623.996006 # Number of busy cycles +system.cpu0.not_idle_fraction 0.996860 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.003140 # Percentage of idle cycles system.cpu0.Branches 16199 # Number of branches fetched system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction @@ -463,10 +463,10 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 137705 # Class of executed instruction system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu1.clk_domain.clock 1000 # Clock period in ticks -system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 498 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 309 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands @@ -658,7 +658,7 @@ system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 470 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 284 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -850,7 +850,7 @@ system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 473 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1042,7 +1042,7 @@ system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 467 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 274 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1232,27 +1232,27 @@ system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands -system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it @@ -1271,9 +1271,9 @@ system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 2741 # number of cycles the CU issues nothing system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued @@ -1281,57 +1281,79 @@ system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 970 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 548 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 566 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 523 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 625 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 340 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 335 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::stdev 0.250206 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::stdev 0.277106 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::1 59 1.65% 98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::2 38 1.06% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::0 2741 96.51% 96.51% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::1 57 2.01% 98.52% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::2 42 1.48% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 37.225806 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 154.644552 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 90 # number of CU transitions from active to idle +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 90 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 29.322222 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 145.995831 # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 76 84.44% 84.44% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.78% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.11% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 6 6.67% 100.00% # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 90 # duration of idle periods in cycles system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs0.valu_insts 68 # Number of vector ALU insts issued. +system.cpu1.CUs0.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. +system.cpu1.CUs0.salu_insts 0 # Number of scalar ALU insts issued. +system.cpu1.CUs0.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. +system.cpu1.CUs0.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. +system.cpu1.CUs0.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. +system.cpu1.CUs0.thread_cycles_valu 3076 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. +system.cpu1.CUs0.valu_utilization 70.680147 # Percentage of active vector ALU threads in a wave. +system.cpu1.CUs0.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. +system.cpu1.CUs0.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. +system.cpu1.CUs0.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. +system.cpu1.CUs0.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. +system.cpu1.CUs0.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. +system.cpu1.CUs0.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. +system.cpu1.CUs0.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). +system.cpu1.CUs0.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs0.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). +system.cpu1.CUs0.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs0.scalar_mem_writes 0 # Number of scalar mem write insts. +system.cpu1.CUs0.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. +system.cpu1.CUs0.scalar_mem_reads 0 # Number of scalar mem read insts. +system.cpu1.CUs0.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests -system.cpu1.CUs0.tlb_cycles -455223738000 # total number of cycles for all uncoalesced requests -system.cpu1.CUs0.avg_translation_latency -591968449.934981 # Avg. translation latency for data translations +system.cpu1.CUs0.tlb_cycles -454892896000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs0.avg_translation_latency -591538226.267880 # Avg. translation latency for data translations system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB @@ -1407,23 +1429,23 @@ system.cpu1.CUs0.local_mem_instr_cnt 6 # dy system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::mean 92.127660 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::stdev 237.147810 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::mean 71.028369 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::stdev 225.061514 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::4-5 61 43.26% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 74.47% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 76.60% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) -system.cpu1.CUs0.num_total_cycles 3570 # number of cycles the CU ran for -system.cpu1.CUs0.vpc 1.896078 # Vector Operations per cycle (this CU only) -system.cpu1.CUs0.ipc 0.039496 # Instructions per cycle (this CU only) +system.cpu1.CUs0.num_total_cycles 2840 # number of cycles the CU ran for +system.cpu1.CUs0.vpc 2.383451 # Vector Operations per cycle (this CU only) +system.cpu1.CUs0.ipc 0.049648 # Instructions per cycle (this CU only) system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) @@ -1501,10 +1523,10 @@ system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts -system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 591 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 406 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands @@ -1696,7 +1718,7 @@ system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 562 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1888,7 +1910,7 @@ system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 561 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -2080,7 +2102,7 @@ system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 551 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 364 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -2270,27 +2292,27 @@ system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands -system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it @@ -2309,67 +2331,89 @@ system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 2740 # number of cycles the CU issues nothing +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 100 # number of cycles the CU issued at least one instruction system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 973 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 662 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 634 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 606 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 795 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 437 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 431 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 422 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 408 # Number of cycles no instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::stdev 0.249084 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::stdev 0.275831 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::1 58 1.62% 98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::2 40 1.12% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::0 2740 96.48% 96.48% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::1 59 2.08% 98.56% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::2 41 1.44% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 35.776596 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 153.908027 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 91 # number of CU transitions from active to idle +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 91 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 30.010989 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 148.108031 # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 76 83.52% 83.52% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.10% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 6 6.59% 100.00% # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 91 # duration of idle periods in cycles system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs1.valu_insts 68 # Number of vector ALU insts issued. +system.cpu1.CUs1.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. +system.cpu1.CUs1.salu_insts 0 # Number of scalar ALU insts issued. +system.cpu1.CUs1.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. +system.cpu1.CUs1.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. +system.cpu1.CUs1.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. +system.cpu1.CUs1.thread_cycles_valu 3071 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. +system.cpu1.CUs1.valu_utilization 70.565257 # Percentage of active vector ALU threads in a wave. +system.cpu1.CUs1.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. +system.cpu1.CUs1.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. +system.cpu1.CUs1.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. +system.cpu1.CUs1.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. +system.cpu1.CUs1.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. +system.cpu1.CUs1.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. +system.cpu1.CUs1.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). +system.cpu1.CUs1.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs1.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). +system.cpu1.CUs1.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs1.scalar_mem_writes 0 # Number of scalar mem write insts. +system.cpu1.CUs1.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. +system.cpu1.CUs1.scalar_mem_reads 0 # Number of scalar mem read insts. +system.cpu1.CUs1.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests -system.cpu1.CUs1.tlb_cycles -455230572000 # total number of cycles for all uncoalesced requests -system.cpu1.CUs1.avg_translation_latency -591977336.801040 # Avg. translation latency for data translations +system.cpu1.CUs1.tlb_cycles -454919630000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs1.avg_translation_latency -591572990.897269 # Avg. translation latency for data translations system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB @@ -2445,23 +2489,23 @@ system.cpu1.CUs1.local_mem_instr_cnt 6 # dy system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::mean 91.269504 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::stdev 240.230451 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::mean 72.113475 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::stdev 228.065470 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::4-5 60 42.55% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::6-7 34 24.11% 75.89% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::8-9 3 2.13% 78.01% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) -system.cpu1.CUs1.num_total_cycles 3570 # number of cycles the CU ran for -system.cpu1.CUs1.vpc 1.894118 # Vector Operations per cycle (this CU only) -system.cpu1.CUs1.ipc 0.039496 # Instructions per cycle (this CU only) +system.cpu1.CUs1.num_total_cycles 2840 # number of cycles the CU ran for +system.cpu1.CUs1.vpc 2.380986 # Vector Operations per cycle (this CU only) +system.cpu1.CUs1.ipc 0.049648 # Instructions per cycle (this CU only) system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) @@ -2539,20 +2583,20 @@ system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts -system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu2.num_kernel_launched 1 # number of kernel launched system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses -system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes -system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads -system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes -system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1549 # number of data array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1549 # number of tag array reads +system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1549 # number of tag array writes +system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue @@ -2560,7 +2604,7 @@ system.dispatcher_coalescer.local_queuing_cycles 0 system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks -system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses @@ -2577,7 +2621,7 @@ system.dispatcher_tlb.local_latency nan # Av system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks -system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue @@ -2585,7 +2629,7 @@ system.l1_coalescer0.local_queuing_cycles 0 # N system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks -system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue @@ -2593,7 +2637,7 @@ system.l1_coalescer1.local_queuing_cycles 0 # N system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks -system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses @@ -2610,7 +2654,7 @@ system.l1_tlb0.local_latency 0 # Av system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks -system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses @@ -2627,7 +2671,7 @@ system.l1_tlb1.local_latency 0 # Av system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2635,7 +2679,7 @@ system.l2_coalescer.local_queuing_cycles 1000 # Nu system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks -system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses system.l2_tlb.local_TLB_hits 3 # Number of TLB hits system.l2_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2652,7 +2696,7 @@ system.l2_tlb.local_latency 8625.125000 # Av system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2660,7 +2704,7 @@ system.l3_coalescer.local_queuing_cycles 1000 # Nu system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks -system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses system.l3_tlb.local_TLB_hits 0 # Number of TLB hits system.l3_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2675,7 +2719,7 @@ system.l3_tlb.unique_pages 5 # Nu system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) -system.piobus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.piobus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.piobus.trans_dist::WriteReq 94 # Transaction distribution system.piobus.trans_dist::WriteResp 94 # Transaction distribution system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) @@ -2686,47 +2730,47 @@ system.piobus.reqLayer0.occupancy 188000 # La system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007896 -system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 -system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 -system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 -system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 -system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 -system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 -system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 -system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 -system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 -system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 -system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009900 -system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 +system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007895 +system.ruby.network.ext_links0.int_node.msg_count.Control::0 1549 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1549 +system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1561 +system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1537 +system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1549 +system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12392 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12392 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112392 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12296 +system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12392 +system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009908 +system.ruby.network.ext_links1.int_node.msg_count.Control::0 14 system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 -system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 +system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 12 system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 -system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 +system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 112 system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 -system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 96 system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads +system.tcp_cntrl0.L1cache.num_data_array_reads 8 # number of data array reads system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes -system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array -system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array +system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP -system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_st_misses 5 # stores that miss in the GPU system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -2735,46 +2779,46 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000716 +system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000708 system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 -system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 -system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 -system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 -system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 14 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 17 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 24 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 31 system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 -system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16 -system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 14 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 17 system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 system.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 -system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128 -system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152 -system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872 -system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 112 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 136 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1728 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2232 system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 -system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128 -system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 112 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 136 system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads +system.tcp_cntrl1.L1cache.num_data_array_reads 8 # number of data array reads system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array -system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array -system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array +system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP -system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU +system.tcp_cntrl1.coalescer.gpu_st_misses 4 # stores that miss in the GPU system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -2783,98 +2827,98 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses -system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads -system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes -system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads -system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes -system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array -system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load -system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.L1cache.num_data_array_reads 70 # number of data array reads +system.sqc_cntrl0.L1cache.num_data_array_writes 3 # number of data array writes +system.sqc_cntrl0.L1cache.num_tag_array_reads 70 # number of tag array reads +system.sqc_cntrl0.L1cache.num_tag_array_writes 3 # number of tag array writes +system.sqc_cntrl0.L1cache.num_data_array_stalls 28 # number of stalls caused by data array +system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.sequencer.load_waiting_on_load 75 # Number of times a load aliased with a pending load +system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses -system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses -system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads -system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes -system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 3116 -system.ruby.network.msg_count.Request_Control 3121 -system.ruby.network.msg_count.Response_Data 3159 -system.ruby.network.msg_count.Response_Control 3078 -system.ruby.network.msg_count.Unblock_Control 3121 -system.ruby.network.msg_byte.Control 24928 -system.ruby.network.msg_byte.Request_Control 24968 -system.ruby.network.msg_byte.Response_Data 227448 -system.ruby.network.msg_byte.Response_Control 24624 -system.ruby.network.msg_byte.Unblock_Control 24968 +system.tccdir_cntrl0.directory.num_tag_array_reads 1552 # number of tag array reads +system.tccdir_cntrl0.directory.num_tag_array_writes 25 # number of tag array writes +system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 3112 +system.ruby.network.msg_count.Request_Control 3115 +system.ruby.network.msg_count.Response_Data 3153 +system.ruby.network.msg_count.Response_Control 3074 +system.ruby.network.msg_count.Unblock_Control 3115 +system.ruby.network.msg_byte.Control 24896 +system.ruby.network.msg_byte.Request_Control 24920 +system.ruby.network.msg_byte.Response_Data 227016 +system.ruby.network.msg_byte.Response_Control 24592 +system.ruby.network.msg_byte.Unblock_Control 24920 system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses -system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses -system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue -system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs -system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts +system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.sqc_coalescer.uncoalesced_accesses 70 # Number of uncoalesced TLB accesses +system.sqc_coalescer.coalesced_accesses 50 # Number of coalesced TLB accesses +system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue +system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs +system.sqc_coalescer.local_latency 1428.571429 # Avg. latency over all incoming pkts system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks -system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses -system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits +system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.sqc_tlb.local_TLB_accesses 50 # Number of TLB accesses +system.sqc_tlb.local_TLB_hits 49 # Number of TLB hits system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses -system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate -system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses -system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits +system.sqc_tlb.local_TLB_miss_rate 2 # TLB miss rate +system.sqc_tlb.global_TLB_accesses 70 # Number of TLB accesses +system.sqc_tlb.global_TLB_hits 62 # Number of TLB hits system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses -system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate -system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level +system.sqc_tlb.global_TLB_miss_rate 11.428571 # TLB miss rate +system.sqc_tlb.access_cycles 70008 # Cycles spent accessing this TLB level system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table system.sqc_tlb.unique_pages 1 # Number of unique pages touched -system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs -system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs +system.sqc_tlb.local_cycles 50001 # Number of cycles spent in queue for all incoming reqs +system.sqc_tlb.local_latency 1000.020000 # Avg. latency over incoming coalesced reqs system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005553 -system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005552 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1549 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 -system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 -system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 -system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1537 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1549 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12392 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 -system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 -system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 -system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016173 -system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12296 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12392 +system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016188 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 14 system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 -system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 112 system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 -system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001963 +system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001944 system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 -system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 14 system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 -system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 -system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016173 -system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1008 +system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016188 +system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 14 system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 -system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 +system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 112 system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 -system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003627 +system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003629 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 -system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 12 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 -system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 96 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 @@ -2887,29 +2931,29 @@ system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 -system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002155 +system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002132 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 -system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19 -system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 17 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 14 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 -system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 17 system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 -system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152 -system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 136 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1008 system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 -system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152 -system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053 -system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5 -system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360 -system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001926 -system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 136 +system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000032 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 3 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001923 +system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 14 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 -system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16 -system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128 +system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 14 +system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 112 system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 -system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128 +system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 112 system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% @@ -2924,12 +2968,12 @@ system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% system.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% -system.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00% +system.ruby.CorePair_Controller.PrbShrData 5 0.00% 0.00% system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% system.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% -system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% +system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00% system.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% @@ -2955,35 +2999,35 @@ system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% -system.ruby.Directory_Controller.RdBlkS 1039 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkS 1037 0.00% 0.00% system.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% -system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00% -system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00% -system.ruby.Directory_Controller.MemData 1551 0.00% 0.00% -system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00% -system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00% +system.ruby.Directory_Controller.CPUPrbResp 1549 0.00% 0.00% +system.ruby.Directory_Controller.ProbeAcksComplete 1549 0.00% 0.00% +system.ruby.Directory_Controller.MemData 1549 0.00% 0.00% +system.ruby.Directory_Controller.CoreUnblock 1549 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkS 1037 0.00% 0.00% system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% -system.ruby.Directory_Controller.BS_M.MemData 36 0.00% 0.00% -system.ruby.Directory_Controller.BM_M.MemData 13 0.00% 0.00% -system.ruby.Directory_Controller.B_M.MemData 12 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.CPUPrbResp 36 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 36 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.MemData 1003 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.CPUPrbResp 14 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 13 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.MemData 322 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.CPUPrbResp 12 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 12 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.MemData 165 0.00% 0.00% -system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1003 0.00% 0.00% -system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1003 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 321 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 322 0.00% 0.00% -system.ruby.Directory_Controller.B_Pm.CPUPrbResp 165 0.00% 0.00% -system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 165 0.00% 0.00% -system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% +system.ruby.Directory_Controller.BS_M.MemData 35 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 18 0.00% 0.00% +system.ruby.Directory_Controller.B_M.MemData 11 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.CPUPrbResp 35 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 35 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.MemData 1002 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.CPUPrbResp 18 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 18 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.MemData 317 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.CPUPrbResp 11 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 11 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.MemData 166 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1002 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1002 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 317 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 317 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.CPUPrbResp 166 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 166 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 1549 0.00% 0.00% system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 16335 @@ -2995,10 +3039,10 @@ system.ruby.LD.latency_hist_seqr::total 16335 system.ruby.LD.latency_hist_coalsr::bucket_size 64 system.ruby.LD.latency_hist_coalsr::max_bucket 639 system.ruby.LD.latency_hist_coalsr::samples 9 -system.ruby.LD.latency_hist_coalsr::mean 219.555556 -system.ruby.LD.latency_hist_coalsr::gmean 24.880500 -system.ruby.LD.latency_hist_coalsr::stdev 259.591078 -system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_coalsr::mean 133.666667 +system.ruby.LD.latency_hist_coalsr::gmean 19.860866 +system.ruby.LD.latency_hist_coalsr::stdev 158.801763 +system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_coalsr::total 9 system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 @@ -3019,10 +3063,10 @@ system.ruby.LD.miss_latency_hist_seqr::total 16160 system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 system.ruby.LD.miss_latency_hist_coalsr::samples 9 -system.ruby.LD.miss_latency_hist_coalsr::mean 219.555556 -system.ruby.LD.miss_latency_hist_coalsr::gmean 24.880500 -system.ruby.LD.miss_latency_hist_coalsr::stdev 259.591078 -system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_coalsr::mean 133.666667 +system.ruby.LD.miss_latency_hist_coalsr::gmean 19.860866 +system.ruby.LD.miss_latency_hist_coalsr::stdev 158.801763 +system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_coalsr::total 9 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 @@ -3032,13 +3076,13 @@ system.ruby.ST.latency_hist_seqr::gmean 2.309412 system.ruby.ST.latency_hist_seqr::stdev 36.833690 system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 314 3.02% 99.92% | 1 0.01% 99.93% | 5 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% system.ruby.ST.latency_hist_seqr::total 10412 -system.ruby.ST.latency_hist_coalsr::bucket_size 32 -system.ruby.ST.latency_hist_coalsr::max_bucket 319 +system.ruby.ST.latency_hist_coalsr::bucket_size 64 +system.ruby.ST.latency_hist_coalsr::max_bucket 639 system.ruby.ST.latency_hist_coalsr::samples 16 -system.ruby.ST.latency_hist_coalsr::mean 125.375000 -system.ruby.ST.latency_hist_coalsr::gmean 15.802815 -system.ruby.ST.latency_hist_coalsr::stdev 128.476133 -system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_coalsr::mean 184.500000 +system.ruby.ST.latency_hist_coalsr::gmean 27.004823 +system.ruby.ST.latency_hist_coalsr::stdev 190.921974 +system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_coalsr::total 16 system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 @@ -3055,28 +3099,28 @@ system.ruby.ST.miss_latency_hist_seqr::mean 2 system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 10090 -system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 -system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 +system.ruby.ST.miss_latency_hist_coalsr::bucket_size 64 +system.ruby.ST.miss_latency_hist_coalsr::max_bucket 639 system.ruby.ST.miss_latency_hist_coalsr::samples 16 -system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 -system.ruby.ST.miss_latency_hist_coalsr::gmean 15.802815 -system.ruby.ST.miss_latency_hist_coalsr::stdev 128.476133 -system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_coalsr::mean 184.500000 +system.ruby.ST.miss_latency_hist_coalsr::gmean 27.004823 +system.ruby.ST.miss_latency_hist_coalsr::stdev 190.921974 +system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_coalsr::total 16 system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.latency_hist_coalsr::samples 2 -system.ruby.ATOMIC.latency_hist_coalsr::mean 317.500000 -system.ruby.ATOMIC.latency_hist_coalsr::gmean 314.366029 -system.ruby.ATOMIC.latency_hist_coalsr::stdev 62.932504 +system.ruby.ATOMIC.latency_hist_coalsr::mean 295.500000 +system.ruby.ATOMIC.latency_hist_coalsr::gmean 293.237105 +system.ruby.ATOMIC.latency_hist_coalsr::stdev 51.618795 system.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.latency_hist_coalsr::total 2 system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 -system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 317.500000 -system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 314.366029 -system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 62.932504 +system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 295.500000 +system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 293.237105 +system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 51.618795 system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 @@ -3178,26 +3222,26 @@ system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 478.666667 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 470.839796 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 101.159939 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 338.666667 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 338.633640 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13 -system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462 -system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009 -system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058 -system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 2.153846 +system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 2.109532 +system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.554700 +system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 12 92.31% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 287.363636 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 279.637814 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 78.345737 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 63.64% 63.64% | 2 18.18% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 336.545455 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 330.845159 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 64.151950 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 2 18.18% 27.27% | 4 36.36% 63.64% | 4 36.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 @@ -3224,10 +3268,9 @@ system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 537 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 536.976722 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 @@ -3237,13 +3280,13 @@ system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 445 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 444.959549 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 8.485281 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 253.500000 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 253.440328 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 7.778175 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 @@ -3263,31 +3306,31 @@ system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 2 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 2 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.728954 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.494894 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 87.50% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 367 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 364.630235 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 44.510031 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 50.00% 50.00% | 4 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 -system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 362 -system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 362.000000 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 332 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 332.000000 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 -system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 273 -system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 259 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 259.000000 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 @@ -3341,25 +3384,25 @@ system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 -system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% -system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% -system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% -system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00% -system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlk 93 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlkM 37 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00% +system.ruby.SQC_Controller.Fetch 70 0.00% 0.00% +system.ruby.SQC_Controller.TCC_AckS 3 0.00% 0.00% +system.ruby.SQC_Controller.I.Fetch 3 0.00% 0.00% +system.ruby.SQC_Controller.S.Fetch 67 0.00% 0.00% +system.ruby.SQC_Controller.I_S.TCC_AckS 3 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkM 34 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkS 3 0.00% 0.00% system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% -system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00% +system.ruby.TCCdir_Controller.CoreUnblock 15 0.00% 0.00% system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% -system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckS 5 0.00% 0.00% system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% -system.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlkS 3 0.00% 0.00% system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% @@ -3370,20 +3413,20 @@ system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% -system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.RdBlkM 20 0.00% 0.00% system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% -system.ruby.TCCdir_Controller.I_ES.RdBlk 79 0.00% 0.00% +system.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00% system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% -system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.I_S.NB_AckS 3 0.00% 0.00% system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.RdBlk 10 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_M.RdBlkM 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00% system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00% system.ruby.TCP_Controller.Load::total 9 @@ -3393,9 +3436,9 @@ system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | system.ruby.TCP_Controller.TCC_AckS::total 4 system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% system.ruby.TCP_Controller.TCC_AckM::total 10 -system.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00% +system.ruby.TCP_Controller.PrbInvData | 2 66.67% 66.67% | 1 33.33% 100.00% system.ruby.TCP_Controller.PrbInvData::total 3 -system.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00% +system.ruby.TCP_Controller.PrbShrData | 6 54.55% 54.55% | 5 45.45% 100.00% system.ruby.TCP_Controller.PrbShrData::total 11 system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% system.ruby.TCP_Controller.I.Load::total 4 @@ -3409,9 +3452,9 @@ system.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | system.ruby.TCP_Controller.S.PrbShrData::total 2 system.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00% system.ruby.TCP_Controller.M.Store::total 8 -system.ruby.TCP_Controller.M.PrbInvData | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.TCP_Controller.M.PrbInvData | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP_Controller.M.PrbInvData::total 1 -system.ruby.TCP_Controller.M.PrbShrData | 5 55.56% 55.56% | 4 44.44% 100.00% +system.ruby.TCP_Controller.M.PrbShrData | 4 44.44% 44.44% | 5 55.56% 100.00% system.ruby.TCP_Controller.M.PrbShrData::total 9 system.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% system.ruby.TCP_Controller.I_M.TCC_AckM::total 10 |