diff options
Diffstat (limited to 'tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt | 156 |
1 files changed, 81 insertions, 75 deletions
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index bc3ca9120..81d1f8ac8 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041221500 # Number of ticks simulated -final_tick 147041221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041346500 # Number of ticks simulated +final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1077194 # Simulator instruction rate (inst/s) -host_op_rate 1082547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1748701394 # Simulator tick rate (ticks/s) -host_mem_usage 444972 # Number of bytes of host memory used -host_seconds 84.09 # Real time elapsed on the host +host_inst_rate 870528 # Simulator instruction rate (inst/s) +host_op_rate 874854 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1413203999 # Simulator tick rate (ticks/s) +host_mem_usage 449664 # Number of bytes of host memory used +host_seconds 104.05 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -22,13 +22,13 @@ system.physmem.num_reads::cpu.inst 577 # Nu system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082443 # number of cpu cycles simulated +system.cpu.numCycles 294082693 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576862 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082442.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732305 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593910 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410415500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593910 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -248,14 +248,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -280,14 +280,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1170574500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1170574500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 120000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 120000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981754500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11981754500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981874500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11981874500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 40000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 40000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120565 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32034000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32034000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32034000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32034000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32034000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32034000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53479.131886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53479.131886 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31435000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31435000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31435000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31435000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31435000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31435000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52479.131886 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52479.131886 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852238 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446176 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005928 # Average percentage of cache occupancy @@ -586,6 +586,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution @@ -601,14 +607,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1890101 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1890101 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887384500 # Layer occupancy (ticks) |