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-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini29
-rwxr-xr-xtests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout11
-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt516
-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini53
-rwxr-xr-xtests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout11
-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt1338
-rw-r--r--tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini25
-rwxr-xr-xtests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout11
-rw-r--r--tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt270
-rw-r--r--tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini26
-rwxr-xr-xtests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout11
-rw-r--r--tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt282
16 files changed, 1315 insertions, 1272 deletions
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 01ff6a1ab..ac0dae266 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
index fcb337fda..5142942fc 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:23
-gem5 executing on e108600-lin, pid 23089
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-atomic
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:13
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54233
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 54141000500 because target called exit()
+Exiting @ tick 54141000500 because exiting with last active thread context
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index c0847e153..5844293a7 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.054141 # Number of seconds simulated
-sim_ticks 54141000500 # Number of ticks simulated
-final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2113722 # Simulator instruction rate (inst/s)
-host_op_rate 2124249 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1263089948 # Simulator tick rate (ticks/s)
-host_mem_usage 393096 # Number of bytes of host memory used
-host_seconds 42.86 # Real time elapsed on the host
-sim_insts 90602408 # Number of instructions simulated
-sim_ops 91053639 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
-system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 442 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 54141000500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 108282002 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 90602408 # Number of instructions committed
-system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_func_calls 112245 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
-system.cpu.num_int_insts 72326352 # number of integer instructions
-system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 124257600 # number of times the integer registers were read
-system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
-system.cpu.num_mem_refs 27220755 # number of memory refs
-system.cpu.num_load_insts 22475911 # Number of load instructions
-system.cpu.num_store_insts 4744844 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 18732305 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
-system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction
-system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 91054081 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 130287906 # Transaction distribution
-system.membus.trans_dist::ReadResp 130291793 # Transaction distribution
-system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
-system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
-system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
-system.membus.trans_dist::SoftPFResp 510 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 135031171 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 135031171 # Request fanout histogram
+sim_seconds 0.054141
+sim_ticks 54141000500
+final_tick 54141000500
+sim_freq 1000000000000
+host_inst_rate 903691
+host_op_rate 908191
+host_tick_rate 540015581
+host_mem_usage 404604
+host_seconds 100.26
+sim_insts 90602408
+sim_ops 91053639
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500
+system.physmem.bytes_read::cpu.inst 431323084
+system.physmem.bytes_read::cpu.data 90016598
+system.physmem.bytes_read::total 521339682
+system.physmem.bytes_inst_read::cpu.inst 431323084
+system.physmem.bytes_inst_read::total 431323084
+system.physmem.bytes_written::cpu.data 18908138
+system.physmem.bytes_written::total 18908138
+system.physmem.num_reads::cpu.inst 107830771
+system.physmem.num_reads::cpu.data 22461532
+system.physmem.num_reads::total 130292303
+system.physmem.num_writes::cpu.data 4738868
+system.physmem.num_writes::total 4738868
+system.physmem.bw_read::cpu.inst 7966662604
+system.physmem.bw_read::cpu.data 1662632703
+system.physmem.bw_read::total 9629295306
+system.physmem.bw_inst_read::cpu.inst 7966662604
+system.physmem.bw_inst_read::total 7966662604
+system.physmem.bw_write::cpu.data 349238799
+system.physmem.bw_write::total 349238799
+system.physmem.bw_total::cpu.inst 7966662604
+system.physmem.bw_total::cpu.data 2011871502
+system.physmem.bw_total::total 9978534106
+system.pwrStateResidencyTicks::UNDEFINED 54141000500
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500
+system.cpu.dtb.walker.walks 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dtb.walker.walkRequestOrigin::total 0
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.flush_tlb 0
+system.cpu.dtb.flush_tlb_mva 0
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 0
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 0
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500
+system.cpu.itb.walker.walks 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.itb.walker.walkRequestOrigin::total 0
+system.cpu.itb.inst_hits 0
+system.cpu.itb.inst_misses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 0
+system.cpu.itb.flush_tlb_mva 0
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 0
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 442
+system.cpu.pwrStateResidencyTicks::ON 54141000500
+system.cpu.numCycles 108282002
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 90602408
+system.cpu.committedOps 91053639
+system.cpu.num_int_alu_accesses 72326352
+system.cpu.num_fp_alu_accesses 48
+system.cpu.num_func_calls 112245
+system.cpu.num_conditional_control_insts 15520157
+system.cpu.num_int_insts 72326352
+system.cpu.num_fp_insts 48
+system.cpu.num_int_register_reads 124257600
+system.cpu.num_int_register_writes 52782988
+system.cpu.num_fp_register_reads 54
+system.cpu.num_fp_register_writes 30
+system.cpu.num_cc_register_reads 271814243
+system.cpu.num_cc_register_writes 53956115
+system.cpu.num_mem_refs 27220755
+system.cpu.num_load_insts 22475911
+system.cpu.num_store_insts 4744844
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 108282002
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 18732305
+system.cpu.op_class::No_OpClass 0 0.00% 0.00%
+system.cpu.op_class::IntAlu 63822829 70.09% 70.09%
+system.cpu.op_class::IntMult 10474 0.01% 70.10%
+system.cpu.op_class::IntDiv 0 0.00% 70.10%
+system.cpu.op_class::FloatAdd 0 0.00% 70.10%
+system.cpu.op_class::FloatCmp 0 0.00% 70.10%
+system.cpu.op_class::FloatCvt 0 0.00% 70.10%
+system.cpu.op_class::FloatMult 0 0.00% 70.10%
+system.cpu.op_class::FloatMultAcc 0 0.00% 70.10%
+system.cpu.op_class::FloatDiv 0 0.00% 70.10%
+system.cpu.op_class::FloatMisc 0 0.00% 70.10%
+system.cpu.op_class::FloatSqrt 0 0.00% 70.10%
+system.cpu.op_class::SimdAdd 0 0.00% 70.10%
+system.cpu.op_class::SimdAddAcc 0 0.00% 70.10%
+system.cpu.op_class::SimdAlu 0 0.00% 70.10%
+system.cpu.op_class::SimdCmp 0 0.00% 70.10%
+system.cpu.op_class::SimdCvt 0 0.00% 70.10%
+system.cpu.op_class::SimdMisc 0 0.00% 70.10%
+system.cpu.op_class::SimdMult 0 0.00% 70.10%
+system.cpu.op_class::SimdMultAcc 0 0.00% 70.10%
+system.cpu.op_class::SimdShift 0 0.00% 70.10%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10%
+system.cpu.op_class::SimdSqrt 0 0.00% 70.10%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10%
+system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10%
+system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10%
+system.cpu.op_class::SimdFloatMult 0 0.00% 70.10%
+system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10%
+system.cpu.op_class::MemRead 22475905 24.68% 94.79%
+system.cpu.op_class::MemWrite 4744822 5.21% 100.00%
+system.cpu.op_class::FloatMemRead 6 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 22 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 91054081
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500
+system.membus.trans_dist::ReadReq 130287906
+system.membus.trans_dist::ReadResp 130291793
+system.membus.trans_dist::WriteReq 4734981
+system.membus.trans_dist::WriteResp 4734981
+system.membus.trans_dist::SoftPFReq 510
+system.membus.trans_dist::SoftPFResp 510
+system.membus.trans_dist::LoadLockedReq 3887
+system.membus.trans_dist::StoreCondReq 3887
+system.membus.trans_dist::StoreCondResp 3887
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800
+system.membus.pkt_count::total 270062342
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736
+system.membus.pkt_size::total 540247820
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 135031171
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 135031171 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 135031171
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 8e2469e68..65ada4bb2 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
index 70c7c951b..b4d1d6fbf 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timin
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:58:41
-gem5 executing on e108600-lin, pid 24094
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:13
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54228
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 147148719500 because target called exit()
+Exiting @ tick 147164058500 because exiting with last active thread context
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 208468615..54d266736 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,673 +1,673 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.147164 # Number of seconds simulated
-sim_ticks 147164058500 # Number of ticks simulated
-final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1482184 # Simulator instruction rate (inst/s)
-host_op_rate 1489549 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2408165715 # Simulator tick rate (ticks/s)
-host_mem_usage 404112 # Number of bytes of host memory used
-host_seconds 61.11 # Real time elapsed on the host
-sim_insts 90576862 # Number of instructions simulated
-sim_ops 91026991 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 442 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 294328117 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 90576862 # Number of instructions committed
-system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_func_calls 112245 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
-system.cpu.num_int_insts 72326352 # number of integer instructions
-system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 124236934 # number of times the integer registers were read
-system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
-system.cpu.num_mem_refs 27220755 # number of memory refs
-system.cpu.num_load_insts 22475911 # Number of load instructions
-system.cpu.num_store_insts 4744844 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 18732305 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
-system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
-system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction
-system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 91054081 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 942702 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits
-system.cpu.dcache.overall_hits::total 26245827 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 946799 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses
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-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency
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-system.cpu.dcache.writebacks::total 942334 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses
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-system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 # number of SoftPFReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 2 # number of replacements
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-system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
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-system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 # Average occupied blocks per requestor
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-system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
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-system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses
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-system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 107830173 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 599 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency
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-system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id
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-system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses
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-system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
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-system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 # average ReadCleanReq miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 # average ReadSharedReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency
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-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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-system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
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+system.membus.trans_dist::ReadSharedReq 792
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680
+system.membus.pkt_count::total 30680
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760
+system.membus.pkt_size::total 981760
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 15340
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 15340 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 15340
+system.membus.reqLayer0.occupancy 15604500
+system.membus.reqLayer0.utilization 0.0
+system.membus.respLayer1.occupancy 76700000
+system.membus.respLayer1.utilization 0.1
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index c9c77a327..37e37c5a9 100644
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -88,6 +88,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -118,7 +119,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic
drivers=
@@ -127,14 +128,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -158,6 +160,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -169,7 +172,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -177,6 +180,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -185,6 +195,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -192,7 +203,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
index 99db763e0..bfb274bdd 100755
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-a
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:30:06
-gem5 started Jul 21 2016 14:30:35
-gem5 executing on e108600-lin, pid 38668
-command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/sparc/linux/simple-atomic
+gem5 compiled Apr 3 2017 18:41:19
+gem5 started Apr 3 2017 18:41:41
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64903
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 122215823500 because target called exit()
+Exiting @ tick 122215823500 because exiting with last active thread context
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 735a3d4df..505667cfa 100644
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,139 +1,139 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.122216 # Number of seconds simulated
-sim_ticks 122215823500 # Number of ticks simulated
-final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2760120 # Simulator instruction rate (inst/s)
-host_op_rate 2760234 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1383492525 # Simulator tick rate (ticks/s)
-host_mem_usage 373928 # Number of bytes of host memory used
-host_seconds 88.34 # Real time elapsed on the host
-sim_insts 243825150 # Number of instructions simulated
-sim_ops 243835265 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory
-system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory
-system.physmem.num_other::total 3886 # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.workload.numSyscalls 443 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 122215823500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 244431648 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 243825150 # Number of instructions committed
-system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
-system.cpu.num_func_calls 4252956 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
-system.cpu.num_int_insts 194726494 # number of integer instructions
-system.cpu.num_fp_insts 11630 # number of float instructions
-system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
-system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
-system.cpu.num_mem_refs 105711441 # number of memory refs
-system.cpu.num_load_insts 82803521 # Number of load instructions
-system.cpu.num_store_insts 22907920 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 29302884 # Number of branches fetched
-system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
-system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction
-system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 244431613 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
-system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
-system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
-system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
-system.membus.trans_dist::SwapReq 3886 # Transaction distribution
-system.membus.trans_dist::SwapResp 3886 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 349547768 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 349547768 # Request fanout histogram
+sim_seconds 0.122216
+sim_ticks 122215823500
+final_tick 122215823500
+sim_freq 1000000000000
+host_inst_rate 1246885
+host_op_rate 1246936
+host_tick_rate 624993047
+host_mem_usage 386196
+host_seconds 195.55
+sim_insts 243825150
+sim_ops 243835265
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500
+system.physmem.bytes_read::cpu.inst 977685992
+system.physmem.bytes_read::cpu.data 328674008
+system.physmem.bytes_read::total 1306360000
+system.physmem.bytes_inst_read::cpu.inst 977685992
+system.physmem.bytes_inst_read::total 977685992
+system.physmem.bytes_written::cpu.data 91606089
+system.physmem.bytes_written::total 91606089
+system.physmem.num_reads::cpu.inst 244421498
+system.physmem.num_reads::cpu.data 82220433
+system.physmem.num_reads::total 326641931
+system.physmem.num_writes::cpu.data 22901951
+system.physmem.num_writes::total 22901951
+system.physmem.num_other::cpu.data 3886
+system.physmem.num_other::total 3886
+system.physmem.bw_read::cpu.inst 7999667834
+system.physmem.bw_read::cpu.data 2689291768
+system.physmem.bw_read::total 10688959601
+system.physmem.bw_inst_read::cpu.inst 7999667834
+system.physmem.bw_inst_read::total 7999667834
+system.physmem.bw_write::cpu.data 749543606
+system.physmem.bw_write::total 749543606
+system.physmem.bw_total::cpu.inst 7999667834
+system.physmem.bw_total::cpu.data 3438835373
+system.physmem.bw_total::total 11438503207
+system.pwrStateResidencyTicks::UNDEFINED 122215823500
+system.cpu_clk_domain.clock 500
+system.cpu.workload.numSyscalls 443
+system.cpu.pwrStateResidencyTicks::ON 122215823500
+system.cpu.numCycles 244431648
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 243825150
+system.cpu.committedOps 243835265
+system.cpu.num_int_alu_accesses 194726494
+system.cpu.num_fp_alu_accesses 11630
+system.cpu.num_func_calls 4252956
+system.cpu.num_conditional_control_insts 18619959
+system.cpu.num_int_insts 194726494
+system.cpu.num_fp_insts 11630
+system.cpu.num_int_register_reads 456818988
+system.cpu.num_int_register_writes 215451554
+system.cpu.num_fp_register_reads 23256
+system.cpu.num_fp_register_writes 90
+system.cpu.num_mem_refs 105711441
+system.cpu.num_load_insts 82803521
+system.cpu.num_store_insts 22907920
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 244431648
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 29302884
+system.cpu.op_class::No_OpClass 28877736 11.81% 11.81%
+system.cpu.op_class::IntAlu 109842388 44.94% 56.75%
+system.cpu.op_class::IntMult 0 0.00% 56.75%
+system.cpu.op_class::IntDiv 0 0.00% 56.75%
+system.cpu.op_class::FloatAdd 42 0.00% 56.75%
+system.cpu.op_class::FloatCmp 0 0.00% 56.75%
+system.cpu.op_class::FloatCvt 0 0.00% 56.75%
+system.cpu.op_class::FloatMult 0 0.00% 56.75%
+system.cpu.op_class::FloatMultAcc 0 0.00% 56.75%
+system.cpu.op_class::FloatDiv 0 0.00% 56.75%
+system.cpu.op_class::FloatMisc 0 0.00% 56.75%
+system.cpu.op_class::FloatSqrt 0 0.00% 56.75%
+system.cpu.op_class::SimdAdd 0 0.00% 56.75%
+system.cpu.op_class::SimdAddAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdAlu 0 0.00% 56.75%
+system.cpu.op_class::SimdCmp 0 0.00% 56.75%
+system.cpu.op_class::SimdCvt 0 0.00% 56.75%
+system.cpu.op_class::SimdMisc 0 0.00% 56.75%
+system.cpu.op_class::SimdMult 0 0.00% 56.75%
+system.cpu.op_class::SimdMultAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdShift 0 0.00% 56.75%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdSqrt 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatMult 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75%
+system.cpu.op_class::MemRead 82803516 33.88% 90.63%
+system.cpu.op_class::MemWrite 22896343 9.37% 100.00%
+system.cpu.op_class::FloatMemRead 11 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 244431613
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500
+system.membus.trans_dist::ReadReq 326641931
+system.membus.trans_dist::ReadResp 326641931
+system.membus.trans_dist::WriteReq 22901951
+system.membus.trans_dist::WriteResp 22901951
+system.membus.trans_dist::SwapReq 3886
+system.membus.trans_dist::SwapResp 3886
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540
+system.membus.pkt_count::total 699095536
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185
+system.membus.pkt_size::total 1397997177
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 349547768
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 349547768 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 349547768
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index b442fbc66..92c3012b0 100644
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
@@ -88,6 +89,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -167,7 +169,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic
drivers=
@@ -176,14 +178,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -207,6 +210,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -218,7 +222,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -226,6 +230,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -234,6 +245,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -241,7 +253,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout
index 42e1355e1..9dc643081 100755
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:17
-gem5 executing on e108600-lin, pid 18547
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/x86/linux/simple-atomic
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:21
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87179
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 168950040000 because target called exit()
+Exiting @ tick 168950040000 because exiting with last active thread context
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index e47781d66..eabb3db7d 100644
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,145 +1,145 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.168950 # Number of seconds simulated
-sim_ticks 168950040000 # Number of ticks simulated
-final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1482871 # Simulator instruction rate (inst/s)
-host_op_rate 2611098 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1585754680 # Simulator tick rate (ticks/s)
-host_mem_usage 400496 # Number of bytes of host memory used
-host_seconds 106.54 # Real time elapsed on the host
-sim_insts 157988548 # Number of instructions simulated
-sim_ops 278192465 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory
-system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory
-system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 444 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 168950040000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 337900081 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 157988548 # Number of instructions committed
-system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
-system.cpu.num_func_calls 8475189 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278169482 # number of integer instructions
-system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
-system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
-system.cpu.num_mem_refs 122219137 # number of memory refs
-system.cpu.num_load_insts 90779385 # Number of load instructions
-system.cpu.num_store_insts 31439752 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 29309705 # Number of branches fetched
-system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
-system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
-system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction
-system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 278192465 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
-system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
-system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
-system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 339915363 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 339915363 # Request fanout histogram
+sim_seconds 0.168950
+sim_ticks 168950040000
+final_tick 168950040000
+sim_freq 1000000000000
+host_inst_rate 689046
+host_op_rate 1213300
+host_tick_rate 736853372
+host_mem_usage 412400
+host_seconds 229.29
+sim_insts 157988548
+sim_ops 278192465
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000
+system.physmem.bytes_read::cpu.inst 1741569312
+system.physmem.bytes_read::cpu.data 717246013
+system.physmem.bytes_read::total 2458815325
+system.physmem.bytes_inst_read::cpu.inst 1741569312
+system.physmem.bytes_inst_read::total 1741569312
+system.physmem.bytes_written::cpu.data 243173117
+system.physmem.bytes_written::total 243173117
+system.physmem.num_reads::cpu.inst 217696164
+system.physmem.num_reads::cpu.data 90779447
+system.physmem.num_reads::total 308475611
+system.physmem.num_writes::cpu.data 31439752
+system.physmem.num_writes::total 31439752
+system.physmem.bw_read::cpu.inst 10308191179
+system.physmem.bw_read::cpu.data 4245314254
+system.physmem.bw_read::total 14553505433
+system.physmem.bw_inst_read::cpu.inst 10308191179
+system.physmem.bw_inst_read::total 10308191179
+system.physmem.bw_write::cpu.data 1439319677
+system.physmem.bw_write::total 1439319677
+system.physmem.bw_total::cpu.inst 10308191179
+system.physmem.bw_total::cpu.data 5684633931
+system.physmem.bw_total::total 15992825110
+system.pwrStateResidencyTicks::UNDEFINED 168950040000
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000
+system.cpu.apic_clk_domain.clock 8000
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000
+system.cpu.workload.numSyscalls 444
+system.cpu.pwrStateResidencyTicks::ON 168950040000
+system.cpu.numCycles 337900081
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 157988548
+system.cpu.committedOps 278192465
+system.cpu.num_int_alu_accesses 278169482
+system.cpu.num_fp_alu_accesses 40
+system.cpu.num_func_calls 8475189
+system.cpu.num_conditional_control_insts 18628007
+system.cpu.num_int_insts 278169482
+system.cpu.num_fp_insts 40
+system.cpu.num_int_register_reads 635379407
+system.cpu.num_int_register_writes 217447860
+system.cpu.num_fp_register_reads 40
+system.cpu.num_fp_register_writes 26
+system.cpu.num_cc_register_reads 104140596
+system.cpu.num_cc_register_writes 61764861
+system.cpu.num_mem_refs 122219137
+system.cpu.num_load_insts 90779385
+system.cpu.num_store_insts 31439752
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 337900081
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 29309705
+system.cpu.op_class::No_OpClass 16695 0.01% 0.01%
+system.cpu.op_class::IntAlu 155945354 56.06% 56.06%
+system.cpu.op_class::IntMult 10938 0.00% 56.07%
+system.cpu.op_class::IntDiv 329 0.00% 56.07%
+system.cpu.op_class::FloatAdd 12 0.00% 56.07%
+system.cpu.op_class::FloatCmp 0 0.00% 56.07%
+system.cpu.op_class::FloatCvt 0 0.00% 56.07%
+system.cpu.op_class::FloatMult 0 0.00% 56.07%
+system.cpu.op_class::FloatMultAcc 0 0.00% 56.07%
+system.cpu.op_class::FloatDiv 0 0.00% 56.07%
+system.cpu.op_class::FloatMisc 0 0.00% 56.07%
+system.cpu.op_class::FloatSqrt 0 0.00% 56.07%
+system.cpu.op_class::SimdAdd 0 0.00% 56.07%
+system.cpu.op_class::SimdAddAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdAlu 0 0.00% 56.07%
+system.cpu.op_class::SimdCmp 0 0.00% 56.07%
+system.cpu.op_class::SimdCvt 0 0.00% 56.07%
+system.cpu.op_class::SimdMisc 0 0.00% 56.07%
+system.cpu.op_class::SimdMult 0 0.00% 56.07%
+system.cpu.op_class::SimdMultAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdShift 0 0.00% 56.07%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdSqrt 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatMult 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07%
+system.cpu.op_class::MemRead 90779371 32.63% 88.70%
+system.cpu.op_class::MemWrite 31439738 11.30% 100.00%
+system.cpu.op_class::FloatMemRead 14 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 14 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 278192465
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000
+system.membus.trans_dist::ReadReq 308475611
+system.membus.trans_dist::ReadResp 308475611
+system.membus.trans_dist::WriteReq 31439752
+system.membus.trans_dist::WriteResp 31439752
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328
+system.membus.pkt_count_system.cpu.icache_port::total 435392328
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398
+system.membus.pkt_count_system.cpu.dcache_port::total 244438398
+system.membus.pkt_count::total 679830726
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312
+system.membus.pkt_size_system.cpu.icache_port::total 1741569312
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130
+system.membus.pkt_size_system.cpu.dcache_port::total 960419130
+system.membus.pkt_size::total 2701988442
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 339915363
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 339915363 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 339915363
---------- End Simulation Statistics ----------