1 files changed, 32 insertions, 35 deletions

diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 5293d87cb..4fea94adf 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,8 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -17,19 +26,22 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=500000
@@ -37,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -55,26 +68,19 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -91,26 +97,22 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -127,26 +129,19 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -156,7 +151,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -179,7 +175,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -189,5 +186,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.master[0]