diff options
Diffstat (limited to 'tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json')
| -rw-r--r-- | tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json | 322 |
1 files changed, 322 insertions, 0 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json new file mode 100644 index 000000000..32695de47 --- /dev/null +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json @@ -0,0 +1,322 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "name": "membus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.membus", + "type": "CoherentBus", + "use_default_range": false + }, + "voltage_domain": { + "eventq_index": 0, + "path": "system.voltage_domain", + "type": "VoltageDomain", + "name": "voltage_domain", + "cxx_class": "VoltageDomain" + }, + "physmem": { + "latency": 3.0000000000000004e-08, + "name": "physmem", + "eventq_index": 0, + "latency_var": 0.0, + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "cxx_class": "System", + "load_offset": 0, + "work_end_ckpt_count": 0, + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": 1e-09, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain" + }, + "eventq_index": 0, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": 5e-10, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain" + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "load_addr_mask": 1099511627775, + "work_item_id": -1, + "num_work_ids": 16, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.itb", + "type": "AlphaTLB", + "size": 48 + }, + "dcache": { + "assoc": 2, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 262144 + }, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "function_trace_start": 0, + "cpu_id": 0, + "eventq_index": 0, + "toL2Bus": { + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "name": "toL2Bus", + "header_cycles": 1, + "width": 32, + "eventq_index": 0, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.cpu.toL2Bus", + "type": "CoherentBus", + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0.0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 2, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 131072 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "l2cache": { + "assoc": 8, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "name": "l2cache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 20, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "size": 2097152 + }, + "hit_latency": 20, + "mshrs": 20, + "response_latency": 20, + "is_top_level": false, + "tgts_per_mshr": 12, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.l2cache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 2097152 + }, + "path": "system.cpu", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "function_trace": false, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 0.1, + "eventq_index": 0, + "time_sync_spin_threshold": 9.999999999999999e-05, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file |