diff options
Diffstat (limited to 'tests/quick/se/20.eio-short')
| -rw-r--r-- | tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | 184 |
1 files changed, 97 insertions, 87 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 7d45c36b9..bc136f4c7 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu sim_ticks 727072500 # Number of ticks simulated final_tick 727072500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639322 # Simulator instruction rate (inst/s) -host_op_rate 639300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 929601467 # Simulator tick rate (ticks/s) -host_mem_usage 223596 # Number of bytes of host memory used -host_seconds 0.78 # Real time elapsed on the host +host_inst_rate 1010970 # Simulator instruction rate (inst/s) +host_op_rate 1010933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1469988465 # Simulator tick rate (ticks/s) +host_mem_usage 285244 # Number of bytes of host memory used +host_seconds 0.49 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 500019 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 287.258890 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 287.258578 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 287.258890 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 287.258578 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.070131 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.070131 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -201,14 +201,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 454 system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16852500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16852500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24289000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24289000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24289000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24289000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17010000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17010000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24516000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24516000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24516000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24516000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses @@ -217,22 +217,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 265.012564 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 265.012287 # Cycle average of tags in use system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 265.012564 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 265.012287 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id @@ -290,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 403 system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21561000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21561000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21561000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21561000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21561000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21561000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21762500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21762500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21762500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21762500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21762500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21762500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53501.240695 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53501.240695 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54001.240695 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54001.240695 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54001.240695 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54001.240695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54001.240695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54001.240695 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 481.541188 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 481.539213 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521972 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.018107 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521106 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy @@ -327,55 +327,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 403 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 315 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 315 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses system.cpu.l2cache.overall_misses::total 857 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21158000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16537500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 37695500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7297500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 7297500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21158000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21158000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16537500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 16537500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 21158000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 23835000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 44993000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 21158000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 23835000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 44993000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 403 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 403 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 315 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.240695 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.696379 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.240695 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.240695 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52500.583431 # average overall miss latency @@ -390,55 +395,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 718 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 315 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 315 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16321500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12757500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29079000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5629500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5629500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16321500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 34708500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16321500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18387000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 34708500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5907500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5907500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19295000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 36423000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17128000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19295000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36423000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.240695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.240695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.240695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.583431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.240695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.583431 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) @@ -463,10 +473,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 604500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 718 # Transaction distribution system.membus.trans_dist::ReadResp 718 # Transaction distribution system.membus.trans_dist::ReadExReq 139 # Transaction distribution system.membus.trans_dist::ReadExResp 139 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes) |