diff options
Diffstat (limited to 'tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 133 |
1 files changed, 101 insertions, 32 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 8880fe952..84894234a 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3384594 # Simulator instruction rate (inst/s) -host_op_rate 3384489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423074550 # Simulator tick rate (ticks/s) -host_mem_usage 1140672 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host +host_inst_rate 2922206 # Simulator instruction rate (inst/s) +host_op_rate 2922133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 365280152 # Simulator tick rate (ticks/s) +host_mem_usage 1149344 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host sim_insts 2000004 # Number of instructions simulated sim_ops 2000004 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 219392 # Number of bytes read from this memory -system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3428 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 877513594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 412646416 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 877513594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory +system.physmem.bytes_read::total 219392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s) system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -103,14 +140,17 @@ system.cpu0.icache.demand_accesses::total 500019 # n system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -148,15 +188,19 @@ system.cpu0.dcache.demand_accesses::total 180775 # n system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks @@ -245,14 +289,17 @@ system.cpu1.icache.demand_accesses::total 500019 # n system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -290,15 +337,19 @@ system.cpu1.dcache.demand_accesses::total 180775 # n system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks @@ -387,14 +438,17 @@ system.cpu2.icache.demand_accesses::total 500019 # n system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -432,15 +486,19 @@ system.cpu2.dcache.demand_accesses::total 180775 # n system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks @@ -529,14 +587,17 @@ system.cpu3.icache.demand_accesses::total 500019 # n system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -574,15 +635,19 @@ system.cpu3.dcache.demand_accesses::total 180775 # n system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks @@ -716,10 +781,12 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses @@ -728,6 +795,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.870410 # mi system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses @@ -736,12 +804,13 @@ system.l2c.overall_miss_rate::cpu2.inst 0.870410 # mi system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |