diff options
Diffstat (limited to 'tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | 872 |
1 files changed, 436 insertions, 436 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 201c425a7..1f00329e8 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000729 # Nu sim_ticks 729024000 # Number of ticks simulated final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1420709 # Simulator instruction rate (inst/s) -host_op_rate 1420692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 517863701 # Simulator tick rate (ticks/s) -host_mem_usage 236964 # Number of bytes of host memory used -host_seconds 1.41 # Real time elapsed on the host +host_inst_rate 1392779 # Simulator instruction rate (inst/s) +host_op_rate 1392763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 507683499 # Simulator tick rate (ticks/s) +host_mem_usage 238176 # Number of bytes of host memory used +host_seconds 1.44 # Real time elapsed on the host sim_insts 1999959 # Number of instructions simulated sim_ops 1999959 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory @@ -62,40 +62,393 @@ system.membus.trans_dist::ReadReq 2872 # Tr system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 6856 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 219392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 219392 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) system.membus.respLayer1.occupancy 31051500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.3 # Layer utilization (%) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use +system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 60 # 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number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 276 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 60 # number of overall hits +system.l2c.overall_hits::cpu0.data 9 # number of overall hits +system.l2c.overall_hits::cpu1.inst 60 # number of overall hits +system.l2c.overall_hits::cpu1.data 9 # number of overall hits +system.l2c.overall_hits::cpu2.inst 60 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 60 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 276 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 315 # 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number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5584500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5584500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5584500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 22313500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 16120000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 18160000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 16274000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 18214000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 16282500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 18214000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 16293500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 18216500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 137774500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 16120000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 18160000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 16274000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 18214000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 16282500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 18214000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 16293500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 18216500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 137774500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050 # average ReadReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 335352471 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7524 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 244480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 244480 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 2374000 # Layer occupancy (ticks) @@ -171,15 +524,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 1458048 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 152 # number of replacements +system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits @@ -249,15 +602,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 61 # number of replacements +system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -404,15 +757,15 @@ system.cpu1.num_idle_cycles 0 # Nu system.cpu1.num_busy_cycles 1458048 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 152 # number of replacements +system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits @@ -482,15 +835,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 61 # number of replacements +system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits @@ -637,15 +990,15 @@ system.cpu2.num_idle_cycles 0 # Nu system.cpu2.num_busy_cycles 1458048 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 152 # number of replacements +system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits @@ -715,15 +1068,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 61 # number of replacements +system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits @@ -870,15 +1223,15 @@ system.cpu3.num_idle_cycles 0 # Nu system.cpu3.num_busy_cycles 1458048 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 152 # number of replacements -system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 152 # number of replacements +system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits @@ -948,15 +1301,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 61 # number of replacements +system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits @@ -1048,358 +1401,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use -system.l2c.tags.total_refs 332 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits -system.l2c.Writeback_hits::total 116 # number of Writeback hits -system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 276 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 60 # number of overall hits -system.l2c.overall_hits::cpu0.data 9 # number of overall hits -system.l2c.overall_hits::cpu1.inst 60 # number of overall hits -system.l2c.overall_hits::cpu1.data 9 # number of overall hits -system.l2c.overall_hits::cpu2.inst 60 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 60 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses -system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::total 3428 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 403 # number of overall misses -system.l2c.overall_misses::cpu0.data 454 # number of overall misses -system.l2c.overall_misses::cpu1.inst 403 # number of overall misses -system.l2c.overall_misses::cpu1.data 454 # number of overall misses -system.l2c.overall_misses::cpu2.inst 403 # number of overall misses -system.l2c.overall_misses::cpu2.data 454 # number of overall misses -system.l2c.overall_misses::cpu3.inst 403 # number of overall misses -system.l2c.overall_misses::cpu3.data 454 # number of overall misses -system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 21101500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 21110000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 16409500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 21118500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 16409500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 21129500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 16412000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 150100000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7252500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 7252500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 7252500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 7252500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 29010000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 21101500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 21110000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 23662000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 21118500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 23662000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 21129500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 23664500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 179110000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 21101500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23662000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 21110000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 23662000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 21118500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 23662000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 21129500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 23664500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 179110000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 139 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050 # average ReadReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |