diff options
Diffstat (limited to 'tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp')
5 files changed, 451 insertions, 165 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index e973b978e..1a6fc47f9 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus p boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -112,8 +127,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -153,8 +178,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -196,6 +226,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -211,6 +242,10 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -229,12 +264,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -253,8 +293,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -270,12 +315,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -294,8 +344,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -337,6 +392,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=2 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -352,6 +408,10 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -370,12 +430,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -394,8 +459,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -411,12 +481,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -435,8 +510,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -478,6 +558,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=3 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -493,6 +574,10 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -511,12 +596,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -535,8 +625,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -552,12 +647,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -576,8 +676,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -635,12 +740,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -659,8 +769,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -668,10 +783,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 @@ -693,11 +813,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] @@ -705,10 +830,15 @@ port=system.membus.master[0] type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json index 77968a744..c402eaa8e 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json @@ -6,6 +6,24 @@ "mmap_using_noreserve": false, "kernel_addr_check": true, "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, "slave": { "peer": [ "system.system_port", @@ -13,8 +31,7 @@ ], "role": "SLAVE" }, - "name": "membus", - "point_of_coherency": true, + "p_state_clk_gate_min": 1000, "snoop_filter": { "name": "snoop_filter", "system": "system", @@ -25,24 +42,12 @@ "type": "SnoopFilter", "lookup_latency": 1 }, - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "system": "system", - "width": 16, - "eventq_index": 0, - "master": { - "peer": [ - "system.physmem.port" - ], - "role": "MASTER" - }, - "response_latency": 2, - "cxx_class": "CoherentXBar", + "power_model": null, "path": "system.membus", "snoop_response_latency": 4, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 3 + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false }, "symbolfile": "", "l2c": { @@ -52,53 +57,64 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 20, "cxx_class": "Cache", "size": 4194304, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 20, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 8, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.l2c.tags", + "hit_latency": 20, "block_size": 64, "type": "LRU", "size": 4194304 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.membus.slave[1]", "role": "MASTER" }, "type": "Cache", "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 20, - "demand_mshr_reserve": 1, "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.l2c", - "name": "l2c", "mshrs": 20, + "name": "l2c", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 8 }, "readfile": "", "thermal_model": null, "cxx_class": "System", + "work_begin_cpu_id_exit": -1, "load_offset": 0, "work_begin_exit_count": 0, - "work_end_ckpt_count": 0, + "p_state_clk_gate_min": 1000, "memories": [ "system.physmem" ], @@ -118,7 +134,8 @@ }, "mem_ranges": [], "eventq_index": 0, - "work_begin_cpu_id_exit": -1, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "dvfs_handler": { "enable": false, "name": "dvfs_handler", @@ -144,16 +161,25 @@ }, "cache_line_size": 64, "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, "physmem": { "range": "0:134217727", "latency": 30000, "name": "physmem", + "p_state_clk_gate_min": 1000, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "73.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, "path": "system.physmem", "null": false, "type": "SimpleMemory", @@ -163,6 +189,7 @@ }, "in_addr_map": true }, + "power_model": null, "work_cpus_ckpt_count": 0, "thermal_components": [], "path": "system", @@ -180,6 +207,24 @@ "domain_id": -1 }, "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.l2c.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, "slave": { "peer": [ "system.cpu0.icache.mem_side", @@ -193,8 +238,7 @@ ], "role": "SLAVE" }, - "name": "toL2Bus", - "point_of_coherency": false, + "p_state_clk_gate_min": 1000, "snoop_filter": { "name": "snoop_filter", "system": "system", @@ -205,32 +249,18 @@ "type": "SnoopFilter", "lookup_latency": 0 }, - "forward_latency": 0, - "clk_domain": "system.cpu_clk_domain", - "system": "system", - "width": 32, - "eventq_index": 0, - "master": { - "peer": [ - "system.l2c.cpu_side" - ], - "role": "MASTER" - }, - "response_latency": 1, - "cxx_class": "CoherentXBar", + "power_model": null, "path": "system.toL2Bus", "snoop_response_latency": 1, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 1 + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false }, + "work_end_ckpt_count": 0, "mem_mode": "timing", "name": "system", "init_param": 0, - "system_port": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, + "p_state_clk_gate_bins": 20, "load_addr_mask": 1099511627775, "cpu": [ { @@ -245,22 +275,6 @@ "size": 48 }, "system": "system", - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "checker": null, - "eventq_index": 0, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.cpu0.icache.cpu_side", - "role": "MASTER" - }, "icache": { "cpu_side": { "peer": "system.cpu0.icache_port", @@ -268,47 +282,77 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 1, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu0.icache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[0]", "role": "MASTER" }, "type": "Cache", "writeback_clean": true, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": true, "prefetch_on_access": false, "path": "system.cpu0.icache", - "name": "icache", "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 1 }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu0.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, "interrupts": [ { "eventq_index": 0, @@ -323,6 +367,7 @@ "role": "MASTER" }, "socket_id": 0, + "power_model": null, "max_insts_all_threads": 0, "path": "system.cpu0", "max_loads_any_thread": 0, @@ -365,44 +410,54 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 4, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu0.dcache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[1]", "role": "MASTER" }, "type": "Cache", "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.cpu0.dcache", - "name": "dcache", "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 4 }, @@ -436,22 +491,6 @@ "size": 48 }, "system": "system", - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 1, - "checker": null, - "eventq_index": 0, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.cpu1.icache.cpu_side", - "role": "MASTER" - }, "icache": { "cpu_side": { "peer": "system.cpu1.icache_port", @@ -459,47 +498,77 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 1, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu1.icache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[2]", "role": "MASTER" }, "type": "Cache", "writeback_clean": true, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": true, "prefetch_on_access": false, "path": "system.cpu1.icache", - "name": "icache", "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 1 }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu1.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, "interrupts": [ { "eventq_index": 0, @@ -514,6 +583,7 @@ "role": "MASTER" }, "socket_id": 0, + "power_model": null, "max_insts_all_threads": 0, "path": "system.cpu1", "max_loads_any_thread": 0, @@ -556,44 +626,54 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 4, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu1.dcache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[3]", "role": "MASTER" }, "type": "Cache", "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.cpu1.dcache", - "name": "dcache", "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 4 }, @@ -627,22 +707,6 @@ "size": 48 }, "system": "system", - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 2, - "checker": null, - "eventq_index": 0, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.cpu2.icache.cpu_side", - "role": "MASTER" - }, "icache": { "cpu_side": { "peer": "system.cpu2.icache_port", @@ -650,47 +714,77 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 1, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu2.icache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[4]", "role": "MASTER" }, "type": "Cache", "writeback_clean": true, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": true, "prefetch_on_access": false, "path": "system.cpu2.icache", - "name": "icache", "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 1 }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 2, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu2.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, "interrupts": [ { "eventq_index": 0, @@ -705,6 +799,7 @@ "role": "MASTER" }, "socket_id": 0, + "power_model": null, "max_insts_all_threads": 0, "path": "system.cpu2", "max_loads_any_thread": 0, @@ -747,44 +842,54 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 4, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu2.dcache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[5]", "role": "MASTER" }, "type": "Cache", "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.cpu2.dcache", - "name": "dcache", "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 4 }, @@ -818,22 +923,6 @@ "size": 48 }, "system": "system", - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 3, - "checker": null, - "eventq_index": 0, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.cpu3.icache.cpu_side", - "role": "MASTER" - }, "icache": { "cpu_side": { "peer": "system.cpu3.icache_port", @@ -841,47 +930,77 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 1, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu3.icache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[6]", "role": "MASTER" }, "type": "Cache", "writeback_clean": true, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": true, "prefetch_on_access": false, "path": "system.cpu3.icache", - "name": "icache", "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 1 }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 3, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu3.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, "interrupts": [ { "eventq_index": 0, @@ -896,6 +1015,7 @@ "role": "MASTER" }, "socket_id": 0, + "power_model": null, "max_insts_all_threads": 0, "path": "system.cpu3", "max_loads_any_thread": 0, @@ -938,44 +1058,54 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 4, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu3.dcache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.toL2Bus.slave[7]", "role": "MASTER" }, "type": "Cache", "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.cpu3.dcache", - "name": "dcache", "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 4 }, diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 7bec60132..354ec7ef4 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -1,11 +1,11 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything +gzip: stdout: gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe +stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 2e09f130f..2d43e9e24 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 5 2016 19:50:43 -gem5 started Jun 5 2016 20:00:38 -gem5 executing on zizzer, pid 54353 +gem5 compiled Jun 12 2016 19:14:13 +gem5 started Jun 12 2016 19:14:35 +gem5 executing on zizzer, pid 29705 command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index eca0d7cd6..c6939ea54 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000735 # Nu sim_ticks 734771500 # Number of ticks simulated final_tick 734771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 460544 # Simulator instruction rate (inst/s) -host_op_rate 460541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 169197253 # Simulator tick rate (ticks/s) -host_mem_usage 245584 # Number of bytes of host memory used -host_seconds 4.34 # Real time elapsed on the host +host_inst_rate 583455 # Simulator instruction rate (inst/s) +host_op_rate 583451 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 214352932 # Simulator tick rate (ticks/s) +host_mem_usage 246584 # Number of bytes of host memory used +host_seconds 3.43 # Real time elapsed on the host sim_insts 1999973 # Number of instructions simulated sim_ops 1999973 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory @@ -59,6 +60,7 @@ system.physmem.bw_total::cpu2.data 39544266 # To system.physmem.bw_total::cpu3.inst 35102069 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 39544266 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 298585343 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -93,6 +95,7 @@ system.cpu0.itb.data_misses 0 # DT system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.workload.num_syscalls 18 # Number of system calls +system.cpu0.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 1469543 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -151,6 +154,7 @@ system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 500019 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 61 # number of replacements system.cpu0.dcache.tags.tagsinuse 272.993368 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. @@ -167,6 +171,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -255,6 +260,7 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 61038.876890 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 61038.876890 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 152 # number of replacements system.cpu0.icache.tags.tagsinuse 216.071308 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. @@ -269,6 +275,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits @@ -370,6 +377,7 @@ system.cpu1.itb.data_misses 0 # DT system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.workload.num_syscalls 18 # Number of system calls +system.cpu1.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 1469543 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -428,6 +436,7 @@ system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 500013 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 61 # number of replacements system.cpu1.dcache.tags.tagsinuse 272.990534 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. @@ -444,6 +453,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 367 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 723559 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 723559 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits @@ -532,6 +542,7 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 61039.956803 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 61039.956803 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 152 # number of replacements system.cpu1.icache.tags.tagsinuse 216.069189 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks. @@ -546,6 +557,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 500477 # Number of tag accesses system.cpu1.icache.tags.data_accesses 500477 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 499551 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499551 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499551 # number of demand (read+write) hits @@ -647,6 +659,7 @@ system.cpu2.itb.data_misses 0 # DT system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.workload.num_syscalls 18 # Number of system calls +system.cpu2.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states system.cpu2.numCycles 1469543 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -705,6 +718,7 @@ system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Cl system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 500008 # Class of executed instruction +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 61 # number of replacements system.cpu2.dcache.tags.tagsinuse 272.987788 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks. @@ -721,6 +735,7 @@ system.cpu2.dcache.tags.age_task_id_blocks_1024::2 367 system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits @@ -809,6 +824,7 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 61038.876890 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 61038.876890 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu2.icache.tags.replacements 152 # number of replacements system.cpu2.icache.tags.tagsinuse 216.067062 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks. @@ -823,6 +839,7 @@ system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu2.icache.tags.tag_accesses 500472 # Number of tag accesses system.cpu2.icache.tags.data_accesses 500472 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu2.icache.ReadReq_hits::cpu2.inst 499546 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499546 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499546 # number of demand (read+write) hits @@ -924,6 +941,7 @@ system.cpu3.itb.data_misses 0 # DT system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_accesses 0 # DTB accesses system.cpu3.workload.num_syscalls 18 # Number of system calls +system.cpu3.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states system.cpu3.numCycles 1469543 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -982,6 +1000,7 @@ system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Cl system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 500005 # Class of executed instruction +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 61 # number of replacements system.cpu3.dcache.tags.tagsinuse 272.985038 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks. @@ -998,6 +1017,7 @@ system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367 system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits @@ -1086,6 +1106,7 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 61039.956803 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 61039.956803 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu3.icache.tags.replacements 152 # number of replacements system.cpu3.icache.tags.tagsinuse 216.064909 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks. @@ -1100,6 +1121,7 @@ system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu3.icache.tags.tag_accesses 500469 # Number of tag accesses system.cpu3.icache.tags.data_accesses 500469 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.cpu3.icache.ReadReq_hits::cpu3.inst 499543 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499543 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499543 # number of demand (read+write) hits @@ -1168,6 +1190,7 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 55578.833693 system.cpu3.icache.demand_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 55578.833693 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 1939.822021 # Cycle average of tags in use system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. @@ -1200,6 +1223,7 @@ system.l2c.tags.age_task_id_blocks_1024::2 2904 # system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 39936 # Number of tag accesses system.l2c.tags.data_accesses 39936 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits @@ -1545,6 +1569,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution @@ -1574,6 +1599,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 0 system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution |