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-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr10
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout22
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt45
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr7
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout22
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt1117
6 files changed, 608 insertions, 615 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 052b7de6e..e69de29bb 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -1,10 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-
-gzip: stdout: Broken pipe
-stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index c513854ed..9f538851a 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -1,19 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 1 2015 18:05:22
-gem5 started Oct 1 2015 18:06:58
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
+gem5 compiled Nov 15 2015 14:28:00
+gem5 started Nov 15 2015 14:28:26
+gem5 executing on ribera.cs.wisc.edu, pid 29051
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 250015500 because a thread reached the max instruction count
+Skipping test: Test requires the 'EioProcess' SimObject.
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index bc68b43ab..bd6dcf8de 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1088528 # Simulator instruction rate (inst/s)
-host_op_rate 1088500 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 136068763 # Simulator tick rate (ticks/s)
-host_mem_usage 242992 # Number of bytes of host memory used
-host_seconds 1.84 # Real time elapsed on the host
+host_inst_rate 1830318 # Simulator instruction rate (inst/s)
+host_op_rate 1830286 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 228795713 # Simulator tick rate (ticks/s)
+host_mem_usage 302752 # Number of bytes of host memory used
+host_seconds 1.09 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -257,6 +257,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
+system.cpu0.icache.writebacks::total 152 # number of writebacks
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
@@ -455,6 +457,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
+system.cpu1.icache.writebacks::total 152 # number of writebacks
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
@@ -653,6 +657,8 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
+system.cpu2.icache.writebacks::writebacks 152 # number of writebacks
+system.cpu2.icache.writebacks::total 152 # number of writebacks
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
@@ -851,6 +857,8 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
+system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
+system.cpu3.icache.writebacks::total 152 # number of writebacks
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
@@ -884,8 +892,10 @@ system.l2c.tags.age_task_id_blocks_1024::2 1836 #
system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 39936 # Number of tag accesses
system.l2c.tags.data_accesses 39936 # Number of data accesses
-system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
-system.l2c.Writeback_hits::total 116 # number of Writeback hits
+system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits
system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits
@@ -947,8 +957,10 @@ system.l2c.overall_misses::cpu2.data 454 # nu
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks 116 # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total 116 # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks 608 # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total 608 # number of WritebackClean accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
@@ -1050,8 +1062,9 @@ system.toL2Bus.snoop_filter.tot_snoops 0 # To
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 736 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution
@@ -1065,15 +1078,15 @@ system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 0 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 4cbd6189b..e69de29bb 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -1,7 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index 971177aae..3a7fc2856 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,19 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 1 2015 18:05:22
-gem5 started Oct 1 2015 18:06:57
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
+gem5 compiled Nov 15 2015 14:28:00
+gem5 started Nov 15 2015 14:30:20
+gem5 executing on ribera.cs.wisc.edu, pid 29151
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 727902500 because a thread reached the max instruction count
+Skipping test: Test requires the 'EioProcess' SimObject.
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 76ab339df..a0fb70213 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000728 # Number of seconds simulated
-sim_ticks 727902500 # Number of ticks simulated
-final_tick 727902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000734 # Number of seconds simulated
+sim_ticks 733914500 # Number of ticks simulated
+final_tick 733914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 608748 # Simulator instruction rate (inst/s)
-host_op_rate 608744 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 221554150 # Simulator tick rate (ticks/s)
-host_mem_usage 243036 # Number of bytes of host memory used
-host_seconds 3.29 # Real time elapsed on the host
-sim_insts 1999978 # Number of instructions simulated
-sim_ops 1999978 # Number of ops (including micro ops) simulated
+host_inst_rate 992162 # Simulator instruction rate (inst/s)
+host_op_rate 992153 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 364079839 # Simulator tick rate (ticks/s)
+host_mem_usage 302744 # Number of bytes of host memory used
+host_seconds 2.02 # Real time elapsed on the host
+sim_insts 1999973 # Number of instructions simulated
+sim_ops 1999973 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
@@ -36,29 +36,29 @@ system.physmem.num_reads::cpu2.data 454 # Nu
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35433317 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39917434 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35433317 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39917434 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 35433317 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 39917434 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 35433317 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 39917434 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 301403004 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 35433317 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35433317 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 35433317 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 35433317 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 141733268 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 35433317 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39917434 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35433317 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 39917434 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 35433317 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 39917434 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 35433317 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 39917434 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 301403004 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 35143058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39590443 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35143058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 39590443 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 35143058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 39590443 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35143058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 39590443 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 298934004 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 140572233 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39590443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 39590443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 39590443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 39590443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 298934004 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
@@ -93,7 +93,7 @@ system.cpu0.itb.data_misses 0 # DT
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 1455805 # number of cpu cycles simulated
+system.cpu0.numCycles 1467829 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
@@ -112,7 +112,7 @@ system.cpu0.num_mem_refs 180793 # nu
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1455805 # Number of busy cycles
+system.cpu0.num_busy_cycles 1467829 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.Branches 59023 # Number of branches fetched
@@ -152,14 +152,14 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 500019 # Class of executed instruction
system.cpu0.dcache.tags.replacements 61 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 273.597897 # Cycle average of tags in use
+system.cpu0.dcache.tags.tagsinuse 273.068294 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.597897 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534371 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.534371 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.068294 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.533337 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.533337 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
@@ -183,14 +183,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 #
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17442000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7645000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 25087000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 25087000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19649000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8621000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 28270000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 28270000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
@@ -207,14 +207,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561
system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53833.333333 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55000 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54183.585313 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54183.585313 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 60645.061728 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62021.582734 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -233,14 +233,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463
system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17118000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17118000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7506000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24624000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24624000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19325000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8482000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27807000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 27807000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27807000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 27807000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -249,24 +249,24 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52833.333333 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 54000 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 53183.585313 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 53183.585313 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 59645.061728 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 61021.582734 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 216.437309 # Cycle average of tags in use
+system.cpu0.icache.tags.tagsinuse 216.116668 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.437309 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422729 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.422729 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.116668 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422103 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.422103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
@@ -284,12 +284,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 463 #
system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 22947500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 22947500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 22947500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 22947500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 22947500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 22947500 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25776500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 25776500 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 25776500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 25776500 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 25776500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 25776500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
@@ -302,12 +302,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926
system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49562.634989 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 49562.634989 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49562.634989 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 49562.634989 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49562.634989 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 49562.634989 # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 55672.786177 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 55672.786177 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 55672.786177 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 55672.786177 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -316,30 +316,32 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
+system.cpu0.icache.writebacks::total 152 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22484500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 22484500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22484500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 22484500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22484500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 22484500 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 25313500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 25313500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 25313500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 25313500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 25313500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 25313500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48562.634989 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 48562.634989 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 48562.634989 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 54672.786177 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
@@ -357,10 +359,10 @@ system.cpu1.dtb.data_hits 180774 # DT
system.cpu1.dtb.data_misses 18 # DTB misses
system.cpu1.dtb.data_acv 0 # DTB access violations
system.cpu1.dtb.data_accesses 180792 # DTB accesses
-system.cpu1.itb.fetch_hits 500016 # ITB hits
+system.cpu1.itb.fetch_hits 500014 # ITB hits
system.cpu1.itb.fetch_misses 13 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 500029 # ITB accesses
+system.cpu1.itb.fetch_accesses 500027 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -374,31 +376,31 @@ system.cpu1.itb.data_misses 0 # DT
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.numCycles 1455805 # number of cpu cycles simulated
+system.cpu1.numCycles 1467829 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 499997 # Number of instructions committed
-system.cpu1.committedOps 499997 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 474685 # Number of integer alu accesses
+system.cpu1.committedInsts 499995 # Number of instructions committed
+system.cpu1.committedOps 499995 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 474683 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 474685 # number of integer instructions
+system.cpu1.num_int_insts 474683 # number of integer instructions
system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_int_register_reads 654279 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 371540 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 654276 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 371538 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu1.num_mem_refs 180792 # number of memory refs
system.cpu1.num_load_insts 124443 # Number of load instructions
system.cpu1.num_store_insts 56349 # Number of store instructions
system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_busy_cycles 1455805 # Number of busy cycles
+system.cpu1.num_busy_cycles 1467829 # Number of busy cycles
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0 # Percentage of idle cycles
system.cpu1.Branches 59022 # Number of branches fetched
system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu 300385 60.08% 63.84% # Class of executed instruction
+system.cpu1.op_class::IntAlu 300383 60.08% 63.84% # Class of executed instruction
system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
@@ -431,16 +433,16 @@ system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Cl
system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 500015 # Class of executed instruction
+system.cpu1.op_class::total 500013 # Class of executed instruction
system.cpu1.dcache.tags.replacements 61 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 273.595136 # Cycle average of tags in use
+system.cpu1.dcache.tags.tagsinuse 273.065457 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.595136 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534365 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.534365 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.065457 # Average occupied blocks per requestor
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system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
@@ -464,14 +466,14 @@ system.cpu1.dcache.demand_misses::cpu1.data 463 #
system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
system.cpu1.dcache.overall_misses::total 463 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17442000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7645000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 25087000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 25087000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 19649000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles
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+system.cpu1.dcache.WriteReq_miss_latency::total 8621500 # number of WriteReq miss cycles
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+system.cpu1.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 28270500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
@@ -488,14 +490,14 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561
system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53833.333333 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55000 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54183.585313 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 60645.061728 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 62025.179856 # average WriteReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 61059.395248 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -514,14 +516,14 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 463
system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
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-system.cpu1.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24624000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles
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+system.cpu1.dcache.overall_mshr_miss_latency::total 27807500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -530,65 +532,65 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561
system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 216.435172 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499553 # Total number of references to valid blocks.
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system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 500479 # Number of tag accesses
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system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
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-system.cpu1.icache.demand_avg_miss_latency::total 49573.434125 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49573.434125 # average overall miss latency
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+system.cpu1.icache.overall_avg_miss_latency::total 55686.825054 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -597,30 +599,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
+system.cpu1.icache.writebacks::total 152 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
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+system.cpu1.icache.ReadReq_mshr_miss_latency::total 25320000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 25320000 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.icache.overall_mshr_miss_latency::total 25320000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48573.434125 # average ReadReq mshr miss latency
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-system.cpu1.icache.demand_avg_mshr_miss_latency::total 48573.434125 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 48573.434125 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 54686.825054 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
@@ -638,10 +642,10 @@ system.cpu2.dtb.data_hits 180774 # DT
system.cpu2.dtb.data_misses 18 # DTB misses
system.cpu2.dtb.data_acv 0 # DTB access violations
system.cpu2.dtb.data_accesses 180792 # DTB accesses
-system.cpu2.itb.fetch_hits 500011 # ITB hits
+system.cpu2.itb.fetch_hits 500009 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500024 # ITB accesses
+system.cpu2.itb.fetch_accesses 500022 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
@@ -655,31 +659,31 @@ system.cpu2.itb.data_misses 0 # DT
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu2.numCycles 1455805 # number of cpu cycles simulated
+system.cpu2.numCycles 1467829 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 499992 # Number of instructions committed
-system.cpu2.committedOps 499992 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 474680 # Number of integer alu accesses
+system.cpu2.committedInsts 499990 # Number of instructions committed
+system.cpu2.committedOps 499990 # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses 474678 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474680 # number of integer instructions
+system.cpu2.num_int_insts 474678 # number of integer instructions
system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654271 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371535 # number of times the integer registers were written
+system.cpu2.num_int_register_reads 654270 # number of times the integer registers were read
+system.cpu2.num_int_register_writes 371533 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu2.num_mem_refs 180792 # number of memory refs
-system.cpu2.num_load_insts 124443 # Number of load instructions
+system.cpu2.num_mem_refs 180791 # number of memory refs
+system.cpu2.num_load_insts 124442 # Number of load instructions
system.cpu2.num_store_insts 56349 # Number of store instructions
system.cpu2.num_idle_cycles 0 # Number of idle cycles
-system.cpu2.num_busy_cycles 1455805 # Number of busy cycles
+system.cpu2.num_busy_cycles 1467829 # Number of busy cycles
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0 # Percentage of idle cycles
system.cpu2.Branches 59022 # Number of branches fetched
system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu 300380 60.07% 63.84% # Class of executed instruction
+system.cpu2.op_class::IntAlu 300379 60.07% 63.84% # Class of executed instruction
system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
@@ -708,20 +712,20 @@ system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Cl
system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
+system.cpu2.op_class::MemRead 124442 24.89% 88.73% # Class of executed instruction
system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 500010 # Class of executed instruction
+system.cpu2.op_class::total 500008 # Class of executed instruction
system.cpu2.dcache.tags.replacements 61 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 273.592374 # Cycle average of tags in use
+system.cpu2.dcache.tags.tagsinuse 273.062707 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.592374 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534360 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.534360 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.062707 # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data 0.533326 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.533326 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
@@ -745,14 +749,14 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 #
system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
system.cpu2.dcache.overall_misses::total 463 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17442000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7645000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 25087000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 25087000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 19649000 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 8621000 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data 28270000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 28270000 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
@@ -769,14 +773,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561
system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53833.333333 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55000 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
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-system.cpu2.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54183.585313 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency
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+system.cpu2.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency
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+system.cpu2.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency
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+system.cpu2.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 61058.315335 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -795,14 +799,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463
system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
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-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7506000 # number of WriteReq MSHR miss cycles
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system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -811,65 +815,65 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561
system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
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-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency
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-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 53183.585313 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency
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+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 61021.582734 # average WriteReq mshr miss latency
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+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 216.433036 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499548 # Total number of references to valid blocks.
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system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.937365 # Average number of references to valid blocks.
+system.cpu2.icache.tags.avg_refs 1078.933045 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.icache.tags.occ_percent::total 0.422721 # Average percentage of cache occupancy
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system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 500474 # Number of tag accesses
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-system.cpu2.icache.overall_hits::total 499548 # number of overall hits
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system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
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system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
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system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
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+system.cpu2.icache.ReadReq_avg_miss_latency::total 55698.704104 # average ReadReq miss latency
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+system.cpu2.icache.demand_avg_miss_latency::total 55698.704104 # average overall miss latency
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system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -878,30 +882,32 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
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system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
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system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
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system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
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+system.cpu2.icache.ReadReq_mshr_miss_latency::total 25325500 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 25325500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 25325500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 25325500 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 25325500 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48584.233261 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 48584.233261 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 48584.233261 # average overall mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 54698.704104 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
@@ -919,10 +925,10 @@ system.cpu3.dtb.data_hits 180772 # DT
system.cpu3.dtb.data_misses 18 # DTB misses
system.cpu3.dtb.data_acv 0 # DTB access violations
system.cpu3.dtb.data_accesses 180790 # DTB accesses
-system.cpu3.itb.fetch_hits 500007 # ITB hits
+system.cpu3.itb.fetch_hits 500006 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_accesses 500020 # ITB accesses
+system.cpu3.itb.fetch_accesses 500019 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.read_acv 0 # DTB read access violations
@@ -936,31 +942,31 @@ system.cpu3.itb.data_misses 0 # DT
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.numCycles 1455805 # number of cpu cycles simulated
+system.cpu3.numCycles 1467829 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 499988 # Number of instructions committed
-system.cpu3.committedOps 499988 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474676 # Number of integer alu accesses
+system.cpu3.committedInsts 499987 # Number of instructions committed
+system.cpu3.committedOps 499987 # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses 474675 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474676 # number of integer instructions
+system.cpu3.num_int_insts 474675 # number of integer instructions
system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654266 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371531 # number of times the integer registers were written
+system.cpu3.num_int_register_reads 654265 # number of times the integer registers were read
+system.cpu3.num_int_register_writes 371530 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu3.num_mem_refs 180790 # number of memory refs
system.cpu3.num_load_insts 124441 # Number of load instructions
system.cpu3.num_store_insts 56349 # Number of store instructions
system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 1455805 # Number of busy cycles
+system.cpu3.num_busy_cycles 1467829 # Number of busy cycles
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
system.cpu3.Branches 59022 # Number of branches fetched
system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu 300378 60.07% 63.84% # Class of executed instruction
+system.cpu3.op_class::IntAlu 300377 60.07% 63.84% # Class of executed instruction
system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
@@ -993,16 +999,16 @@ system.cpu3.op_class::MemRead 124441 24.89% 88.73% # Cl
system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 500006 # Class of executed instruction
+system.cpu3.op_class::total 500005 # Class of executed instruction
system.cpu3.dcache.tags.replacements 61 # number of replacements
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+system.cpu3.dcache.tags.tagsinuse 273.059955 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.tags.occ_percent::total 0.534355 # Average percentage of cache occupancy
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system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
@@ -1026,14 +1032,14 @@ system.cpu3.dcache.demand_misses::cpu3.data 463 #
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17442500 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 17442500 # number of ReadReq miss cycles
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-system.cpu3.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
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-system.cpu3.dcache.demand_miss_latency::total 25087500 # number of demand (read+write) miss cycles
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-system.cpu3.dcache.overall_miss_latency::total 25087500 # number of overall miss cycles
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+system.cpu3.dcache.ReadReq_miss_latency::total 19649500 # number of ReadReq miss cycles
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+system.cpu3.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles
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+system.cpu3.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles
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+system.cpu3.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
@@ -1050,14 +1056,14 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561
system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53834.876543 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 53834.876543 # average ReadReq miss latency
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-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54184.665227 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 54184.665227 # average overall miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 60646.604938 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 60646.604938 # average ReadReq miss latency
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+system.cpu3.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency
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+system.cpu3.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 61059.395248 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1076,14 +1082,14 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 463
system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
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+system.cpu3.dcache.overall_mshr_miss_latency::total 27807500 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -1092,65 +1098,65 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561
system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
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-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52834.876543 # average ReadReq mshr miss latency
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-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
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-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 53184.665227 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 53184.665227 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 53184.665227 # average overall mshr miss latency
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+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.icache.tags.replacements 152 # number of replacements
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system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
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@@ -1159,56 +1165,58 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1454,39 +1466,39 @@ system.l2c.overall_mshr_misses::cpu2.data 454 # n
system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
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system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
@@ -1520,39 +1532,39 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadExReq mshr miss latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 2872 # Transaction distribution
system.membus.trans_dist::ReadExReq 556 # Transaction distribution
@@ -1563,20 +1575,20 @@ system.membus.pkt_count::total 6856 # Pa
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3433 # Request fanout histogram
+system.membus.snoop_fanout::samples 3442 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3433 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3442 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3433 # Request fanout histogram
-system.membus.reqLayer0.occupancy 3438468 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3442 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3471468 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 17142500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 2.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 17140000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 2.3 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1584,8 +1596,9 @@ system.toL2Bus.snoop_filter.tot_snoops 0 # To
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 736 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution
@@ -1599,21 +1612,21 @@ system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3704 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 4556 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 3704 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
@@ -1625,9 +1638,9 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2394000 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total 3704 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 3002000 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 694500 # Layer occupancy (ticks)