1 files changed, 42 insertions, 6 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index ea05b9577..144007094 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
 dtb=system.cpu0.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
 system=system
 tracer=system.cpu0.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=system.cpu0.workload
 dcache_port=system.cpu0.dcache.cpu_side
@@ -567,6 +567,7 @@ ppid=99
 simpoint=0
 system=system
 uid=100
+useArchPT=false
 
 [system.cpu1]
 type=DerivO3CPU
@@ -599,6 +600,7 @@ do_statistics_insts=true
 dtb=system.cpu1.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -651,7 +653,6 @@ switched_out=false
 system=system
 tracer=system.cpu1.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=system.cpu0.workload
 dcache_port=system.cpu1.dcache.cpu_side
@@ -1104,6 +1105,7 @@ do_statistics_insts=true
 dtb=system.cpu2.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -1156,7 +1158,6 @@ switched_out=false
 system=system
 tracer=system.cpu2.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=system.cpu0.workload
 dcache_port=system.cpu2.dcache.cpu_side
@@ -1609,6 +1610,7 @@ do_statistics_insts=true
 dtb=system.cpu3.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -1661,7 +1663,6 @@ switched_out=false
 system=system
 tracer=system.cpu3.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=system.cpu0.workload
 dcache_port=system.cpu3.dcache.cpu_side
@@ -2135,10 +2136,11 @@ sequential_access=false
 size=4194304
 
 [system.membus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8
@@ -2147,8 +2149,33 @@ slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
 activation_limit=4
 addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -2157,6 +2184,7 @@ conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+dll=true
 eventq_index=0
 in_addr_map=true
 max_accesses_per_row=16
@@ -2170,29 +2198,37 @@ read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCCD_L=0
 tCK=1250
 tCL=13750
+tCS=2500
 tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=260000
 tRP=13750
 tRRD=6000
+tRRD_L=0
 tRTP=7500
 tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
 write_low_thresh_perc=50
 port=system.membus.master[0]
 
 [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8