diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 4766 |
1 files changed, 2379 insertions, 2387 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index e575d4b01..53a74ff2b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,93 +1,93 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000126 # Number of seconds simulated -sim_ticks 125996000 # Number of ticks simulated -final_tick 125996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000124 # Number of seconds simulated +sim_ticks 123756000 # Number of ticks simulated +final_tick 123756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220398 # Simulator instruction rate (inst/s) -host_op_rate 220398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23837880 # Simulator tick rate (ticks/s) -host_mem_usage 265580 # Number of bytes of host memory used -host_seconds 5.29 # Real time elapsed on the host -sim_insts 1164916 # Number of instructions simulated -sim_ops 1164916 # Number of ops (including micro ops) simulated +host_inst_rate 286843 # Simulator instruction rate (inst/s) +host_op_rate 286842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31050897 # Simulator tick rate (ticks/s) +host_mem_usage 266468 # Number of bytes of host memory used +host_seconds 3.99 # Real time elapsed on the host +sim_insts 1143228 # Number of instructions simulated +sim_ops 1143228 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 23872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 23616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 6016 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 45440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 373 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu3.inst 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory +system.physmem.bytes_read::total 45248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 6016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31232 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 369 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 94 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 710 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 189466332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 86351948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46731642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11174958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 7111337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7111337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 5079526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7619290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 360646370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189466332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46731642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 7111337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 5079526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248388838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189466332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 86351948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46731642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11174958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 7111337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7111337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 5079526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7619290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 360646370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 710 # Number of read requests accepted +system.physmem.num_reads::cpu3.inst 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory +system.physmem.num_reads::total 707 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 190827111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 87397783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48611784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11377226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 6205760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7240053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 6722906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7240053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 365622677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190827111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48611784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 6205760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 6722906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252367562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190827111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 87397783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48611784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11377226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 6205760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7240053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 6722906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7240053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 365622677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 707 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 710 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 707 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 45440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 45248 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 45440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 45248 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 120 # Per bank write bursts -system.physmem.perBankRdBursts::1 44 # Per bank write bursts -system.physmem.perBankRdBursts::2 31 # Per bank write bursts -system.physmem.perBankRdBursts::3 62 # Per bank write bursts +system.physmem.perBankRdBursts::0 118 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts +system.physmem.perBankRdBursts::3 63 # Per bank write bursts system.physmem.perBankRdBursts::4 69 # Per bank write bursts -system.physmem.perBankRdBursts::5 28 # Per bank write bursts +system.physmem.perBankRdBursts::5 27 # Per bank write bursts system.physmem.perBankRdBursts::6 19 # Per bank write bursts system.physmem.perBankRdBursts::7 27 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 31 # Per bank write bursts +system.physmem.perBankRdBursts::9 29 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts system.physmem.perBankRdBursts::12 70 # Per bank write bursts system.physmem.perBankRdBursts::13 47 # Per bank write bursts system.physmem.perBankRdBursts::14 18 # Per bank write bursts -system.physmem.perBankRdBursts::15 101 # Per bank write bursts +system.physmem.perBankRdBursts::15 100 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 125756000 # Total gap between requests +system.physmem.totGap 123516000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 710 # Read request sizes (log2) +system.physmem.readPktSize::6 707 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -121,10 +121,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 215 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -217,476 +217,473 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.597701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.475219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.687167 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 66 37.93% 37.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43 24.71% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 29 16.67% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 6.32% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 3.45% 89.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 4.60% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 2.30% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.57% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 3.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 174 # Bytes accessed per row activation -system.physmem.totQLat 13059500 # Total ticks spent queuing -system.physmem.totMemAccLat 26372000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18393.66 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.834320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.411435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.318432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 34.32% 34.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 48 28.40% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 26 15.38% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 7.10% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 4.14% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 4.14% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 2.37% 95.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation +system.physmem.totQLat 11450750 # Total ticks spent queuing +system.physmem.totMemAccLat 24707000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16196.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37143.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34946.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 365.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 360.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 365.62 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.82 # Data bus utilization in percentage -system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.86 # Data bus utilization in percentage +system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 525 # Number of row buffer hits during reads +system.physmem.readRowHits 529 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 177121.13 # Average gap between requests -system.physmem.pageHitRate 73.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 856800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 432630 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 174704.38 # Average gap between requests +system.physmem.pageHitRate 74.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 428835 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2856000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6114390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 284160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 31286160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8898240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 5367840 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 64701180 # Total energy per rank (pJ) -system.physmem_0.averagePower 513.516712 # Core power per rank (mW) -system.physmem_0.totalIdleTime 111273500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 346500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3646000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 20064750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 23172500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 10159750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 68606500 # Time in different power states -system.physmem_1.actEnergy 464100 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 227700 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2213400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6260880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 309600 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 30851820 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 11364960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 3424140 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 65551215 # Total energy per rank (pJ) +system.physmem_0.averagePower 529.680036 # Core power per rank (mW) +system.physmem_0.totalIdleTime 108655750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 358500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3906000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 11965500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 29593750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 10265500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 67666750 # Time in different power states +system.physmem_1.actEnergy 435540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2191980 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4959000 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 596640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 28649910 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9231840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 7511880 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 62459430 # Total energy per rank (pJ) -system.physmem_1.averagePower 495.724516 # Core power per rank (mW) -system.physmem_1.totalIdleTime 113374250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1113500 # Time in different power states -system.physmem_1.memoryStateTime::REF 3652000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 26697750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24040500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7662500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 62829750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 99694 # Number of BP lookups -system.cpu0.branchPred.condPredicted 94929 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1689 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 96632 # Number of BTB lookups +system.physmem_1.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4628970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 469440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 25813590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8390400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8693940 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 58212060 # Total energy per rank (pJ) +system.physmem_1.averagePower 470.376728 # Core power per rank (mW) +system.physmem_1.totalIdleTime 112190500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 843500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3126000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 33923000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 21849000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7402250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 56612250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 96945 # Number of BP lookups +system.cpu0.branchPred.condPredicted 92664 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1460 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 94281 # Number of BTB lookups system.cpu0.branchPred.BTBHits 0 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1210 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.usedRAS 1072 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 96632 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 88884 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 7748 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 1163 # Number of mispredicted indirect branches. +system.cpu0.branchPred.indirectLookups 94281 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 87442 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 6839 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 944 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 251993 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 247513 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 23206 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 587602 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 99694 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 90094 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 195641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3677 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 78 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2245 # Number of stall cycles due to pending traps -system.cpu0.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8355 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 903 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 223034 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.634585 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.272061 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 22810 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 572402 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 96945 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 88514 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 191239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3219 # Number of cycles fetch has spent squashing +system.cpu0.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 2152 # Number of stall cycles due to pending traps +system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7601 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 796 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 217827 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.627783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.257744 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34543 15.49% 15.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 92075 41.28% 56.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 690 0.31% 57.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1016 0.46% 57.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 496 0.22% 57.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 87579 39.27% 97.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 656 0.29% 97.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 548 0.25% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5431 2.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33416 15.34% 15.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 90280 41.45% 56.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 662 0.30% 57.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1022 0.47% 57.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 476 0.22% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 86076 39.52% 97.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 627 0.29% 97.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 458 0.21% 97.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4810 2.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 223034 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.395622 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.331819 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18204 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 19474 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 182674 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 844 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1838 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 568807 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1838 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18897 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2138 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15951 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 182807 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1403 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 563480 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu0.fetch.rateDist::total 217827 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391676 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.312614 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17128 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19348 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 178981 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 761 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1609 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 555305 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1609 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17781 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1772 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16195 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 179089 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1381 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 550438 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 925 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 385856 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1122771 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 848321 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 8 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 365359 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 20497 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1128 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1160 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5339 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 179490 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90635 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 87474 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 87162 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 469651 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1149 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 465284 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 17670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14278 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 590 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 223034 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.086157 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.115238 # Number of insts issued each cycle +system.cpu0.rename.RenamedOperands 376177 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1097223 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 828510 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 359139 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17038 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1047 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1085 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5185 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 175971 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 88955 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 85967 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 85657 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 459427 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1094 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 455664 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 15166 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 12611 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 535 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 217827 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.091862 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.108022 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 37655 16.88% 16.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4554 2.04% 18.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 88787 39.81% 58.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 88368 39.62% 98.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1704 0.76% 99.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1021 0.46% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 603 0.27% 99.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 223 0.10% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 119 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 36217 16.63% 16.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4343 1.99% 18.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 87095 39.98% 58.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 86709 39.81% 98.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1627 0.75% 99.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 960 0.44% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 547 0.25% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 218 0.10% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 111 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 223034 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 217827 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 140 40.46% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 83 23.99% 64.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 123 35.55% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 123 36.94% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 85 25.53% 62.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 125 37.54% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 196646 42.26% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 178800 38.43% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 89838 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 192140 42.17% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 175355 38.48% 80.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88169 19.35% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 465284 # Type of FU issued -system.cpu0.iq.rate 1.846416 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 346 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1154078 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 488506 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 462560 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 455664 # Type of FU issued +system.cpu0.iq.rate 1.840970 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 333 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000731 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1129583 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 475739 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 453318 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 465630 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 455997 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 86875 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 85314 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 3221 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2812 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1994 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1869 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1838 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2137 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 558923 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 171 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 179490 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90635 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1033 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1609 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1760 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 31 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 547045 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 114 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 175971 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 88955 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 969 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1860 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 2078 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 463731 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 178412 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1553 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1555 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1766 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 454327 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 175012 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1337 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 88123 # number of nop insts executed -system.cpu0.iew.exec_refs 268032 # number of memory reference insts executed -system.cpu0.iew.exec_branches 92124 # Number of branches executed -system.cpu0.iew.exec_stores 89620 # Number of stores executed -system.cpu0.iew.exec_rate 1.840253 # Inst execution rate -system.cpu0.iew.wb_sent 463047 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 462560 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 274104 # num instructions producing a value -system.cpu0.iew.wb_consumers 277790 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.835607 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986731 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 18452 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 86524 # number of nop insts executed +system.cpu0.iew.exec_refs 262985 # number of memory reference insts executed +system.cpu0.iew.exec_branches 90247 # Number of branches executed +system.cpu0.iew.exec_stores 87973 # Number of stores executed +system.cpu0.iew.exec_rate 1.835568 # Inst execution rate +system.cpu0.iew.wb_sent 453748 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 453318 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 268984 # num instructions producing a value +system.cpu0.iew.wb_consumers 272473 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.831492 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987195 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 15911 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1689 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 219410 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.462923 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.143392 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1460 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 214699 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.473509 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.143772 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 37598 17.14% 17.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90827 41.40% 58.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2058 0.94% 59.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 592 0.27% 59.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 460 0.21% 59.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 86620 39.48% 99.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 500 0.23% 99.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 309 0.14% 99.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 446 0.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 36174 16.85% 16.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 89113 41.51% 58.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1996 0.93% 59.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 609 0.28% 59.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 464 0.22% 59.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 85076 39.63% 99.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 476 0.22% 99.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 292 0.14% 99.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 499 0.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 219410 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 540390 # Number of instructions committed -system.cpu0.commit.committedOps 540390 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 214699 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 531060 # Number of instructions committed +system.cpu0.commit.committedOps 531060 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 264910 # Number of memory references committed -system.cpu0.commit.loads 176269 # Number of loads committed +system.cpu0.commit.refs 260245 # Number of memory references committed +system.cpu0.commit.loads 173159 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 90528 # Number of branches committed +system.cpu0.commit.branches 88973 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 363690 # Number of committed integer instructions. +system.cpu0.commit.int_insts 357470 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 87260 16.15% 16.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 188136 34.81% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 176353 32.63% 83.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 88641 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 85705 16.14% 16.14% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 185026 34.84% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 173243 32.62% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 87086 16.40% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 540390 # Class of committed instruction -system.cpu0.commit.bw_lim_events 446 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 776645 # The number of ROB reads -system.cpu0.rob.rob_writes 1121369 # The number of ROB writes -system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28959 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 453046 # Number of Instructions Simulated -system.cpu0.committedOps 453046 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.556219 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.556219 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.797852 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.797852 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 828824 # number of integer regfile reads -system.cpu0.int_regfile_writes 373673 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 531060 # Class of committed instruction +system.cpu0.commit.bw_lim_events 499 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 760010 # The number of ROB reads +system.cpu0.rob.rob_writes 1097116 # The number of ROB writes +system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 29686 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 445271 # Number of Instructions Simulated +system.cpu0.committedOps 445271 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.555870 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.555870 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.798980 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.798980 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 812559 # number of integer regfile reads +system.cpu0.int_regfile_writes 366073 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 270178 # number of misc regfile reads +system.cpu0.misc_regfile_reads 265038 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.283862 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 178830 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 1039.709302 # Average number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.111163 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 175455 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1026.052632 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.283862 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277898 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277898 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.111163 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277561 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277561 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 720603 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 720603 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 90862 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90862 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 88053 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 88053 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 24 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 24 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 178915 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 178915 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 178915 # number of overall hits -system.cpu0.dcache.overall_hits::total 178915 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 568 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 568 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 18 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 18 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses -system.cpu0.dcache.overall_misses::total 1114 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16630000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16630000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35665989 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35665989 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 490500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 490500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52295989 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 52295989 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52295989 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 52295989 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 91430 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 91430 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 88599 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 88599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 707079 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 707079 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 89048 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 89048 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 86492 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 86492 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 18 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 18 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 175540 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 175540 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 175540 # number of overall hits +system.cpu0.dcache.overall_hits::total 175540 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 556 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 556 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 552 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 552 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 24 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 24 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses +system.cpu0.dcache.overall_misses::total 1108 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15680500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15680500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35675489 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35675489 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 524500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 524500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 51355989 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 51355989 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 51355989 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 51355989 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89604 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89604 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 87044 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 87044 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 180029 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 180029 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 180029 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 180029 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006212 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006212 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006163 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006163 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.428571 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.428571 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006188 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006188 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006188 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006188 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29278.169014 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29278.169014 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65322.324176 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65322.324176 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27250 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 27250 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46944.334829 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46944.334829 # average overall miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 176648 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 176648 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 176648 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 176648 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006205 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006205 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006342 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006342 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006272 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006272 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006272 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006272 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28202.338129 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28202.338129 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64629.509058 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64629.509058 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21854.166667 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 21854.166667 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46350.170578 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46350.170578 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46350.170578 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46350.170578 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 885 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -695,2236 +692,2231 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 375 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 375 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 18 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 18 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7613500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7613500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8176500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8176500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 472500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 472500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15790000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15790000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15790000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15790000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002166 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001930 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001930 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.428571 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002050 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002050 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38452.020202 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38452.020202 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47815.789474 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47815.789474 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26250 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26250 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 391 # number of replacements -system.cpu0.icache.tags.tagsinuse 249.990139 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7433 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 696 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.679598 # Average number of references to valid blocks. +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 364 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 743 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 743 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 192 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 173 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 173 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 24 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 24 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7301500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7301500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8155500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8155500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 500500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 500500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15457000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15457000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15457000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15457000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001988 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001988 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002066 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002066 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002066 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002066 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38028.645833 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38028.645833 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47141.618497 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47141.618497 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20854.166667 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20854.166667 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42347.945205 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42347.945205 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42347.945205 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42347.945205 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 381 # number of replacements +system.cpu0.icache.tags.tagsinuse 247.076486 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6698 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 681 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.835536 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 249.990139 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488262 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.488262 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9051 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9051 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7433 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7433 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7433 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7433 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7433 # number of overall hits -system.cpu0.icache.overall_hits::total 7433 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 922 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 922 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 922 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 922 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 922 # number of overall misses -system.cpu0.icache.overall_misses::total 922 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48154500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 48154500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 48154500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 48154500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 48154500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 48154500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8355 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8355 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8355 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8355 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8355 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8355 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110353 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110353 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110353 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110353 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110353 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110353 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52228.308026 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 52228.308026 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 52228.308026 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 52228.308026 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 247.076486 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482571 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.482571 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 300 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.585938 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8282 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 6698 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6698 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6698 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6698 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6698 # number of overall hits +system.cpu0.icache.overall_hits::total 6698 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 903 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 903 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 903 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 903 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 903 # number of overall misses +system.cpu0.icache.overall_misses::total 903 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 46390500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 46390500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 46390500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 46390500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 46390500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 46390500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7601 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7601 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7601 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7601 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7601 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7601 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118800 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118800 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118800 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118800 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118800 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118800 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51373.754153 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51373.754153 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51373.754153 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51373.754153 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51373.754153 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51373.754153 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 50.125000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 391 # number of writebacks -system.cpu0.icache.writebacks::total 391 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 225 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 225 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 225 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 225 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 697 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 697 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 697 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 697 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 697 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36741500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 36741500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36741500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 36741500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36741500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 36741500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.083423 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.083423 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.083423 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52713.773314 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency -system.cpu1.branchPred.lookups 67120 # Number of BP lookups -system.cpu1.branchPred.condPredicted 59252 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 2530 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 59078 # Number of BTB lookups +system.cpu0.icache.writebacks::writebacks 381 # number of writebacks +system.cpu0.icache.writebacks::total 381 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 682 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 682 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 682 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 682 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 682 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 682 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 35207000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 35207000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 35207000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 35207000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 35207000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 35207000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089725 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.089725 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.089725 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51623.167155 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51623.167155 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51623.167155 # average overall mshr miss latency +system.cpu1.branchPred.lookups 61334 # Number of BP lookups +system.cpu1.branchPred.condPredicted 54401 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2004 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 54412 # Number of BTB lookups system.cpu1.branchPred.BTBHits 0 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 2033 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.usedRAS 1793 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 59078 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 48199 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 10879 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 1412 # Number of mispredicted indirect branches. -system.cpu1.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 194937 # number of cpu cycles simulated +system.cpu1.branchPred.indirectLookups 54412 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 44729 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 9683 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 984 # Number of mispredicted indirect branches. +system.cpu1.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 189559 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 38450 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 366689 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 67120 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 50232 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 144025 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5215 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.icacheStallCycles 38670 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 332272 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 61334 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46522 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 140422 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4165 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1847 # Number of stall cycles due to pending traps -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 26490 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1009 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 186966 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.961260 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.371242 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 27652 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 879 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 182684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.818835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.303785 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66801 35.73% 35.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 58781 31.44% 67.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7398 3.96% 71.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3358 1.80% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 642 0.34% 73.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 38588 20.64% 93.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1104 0.59% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1446 0.77% 95.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 8848 4.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 70336 38.50% 38.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 55803 30.55% 69.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 8540 4.67% 73.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3408 1.87% 75.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 651 0.36% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 33906 18.56% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 999 0.55% 95.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1291 0.71% 95.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7750 4.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 186966 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.344316 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.881064 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23546 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 62450 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 94215 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4138 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2607 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 335701 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2607 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 24537 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 29865 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13172 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 95090 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 21685 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 329147 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 18681 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 182684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.323562 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.752869 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21125 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 71097 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 83834 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4536 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2082 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 303611 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2082 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22030 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34668 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13321 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84450 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 26123 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 298128 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 22342 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 231661 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 629076 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 489741 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 200931 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 30730 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1664 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1812 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 26977 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 90636 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 43093 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 42743 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 36583 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 268793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7661 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 268125 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 26316 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 21262 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 1168 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 186966 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.434084 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.397924 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 207771 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 563979 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 439786 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 36 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 183614 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24157 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1533 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1680 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 31315 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 81609 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39208 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 31953 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 243349 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 8714 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 245236 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 21657 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1128 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 182684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.342405 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.387446 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71753 38.38% 38.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 24944 13.34% 51.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 41684 22.29% 74.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 41301 22.09% 96.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3557 1.90% 98.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1804 0.96% 98.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1118 0.60% 99.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 486 0.26% 99.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 319 0.17% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74656 40.87% 40.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27751 15.19% 56.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 36635 20.05% 76.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 36634 20.05% 96.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3526 1.93% 98.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1704 0.93% 99.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1046 0.57% 99.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 443 0.24% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 289 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 186966 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 182684 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 231 42.39% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 72 13.21% 55.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 242 44.40% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 163 36.88% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 52 11.76% 48.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 227 51.36% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 130845 48.80% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 95251 35.52% 84.32% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 42029 15.68% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 120474 49.13% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 87542 35.70% 84.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37220 15.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 268125 # Type of FU issued -system.cpu1.iq.rate 1.375444 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 545 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.002033 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 723897 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 302756 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 263753 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 245236 # Type of FU issued +system.cpu1.iq.rate 1.293719 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 442 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001802 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 673674 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 273687 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 241932 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 268670 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 245678 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 36498 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 31875 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4839 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 41 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 2826 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3921 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2368 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2607 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8495 # Number of cycles IEW is blocking +system.cpu1.iew.iewSquashCycles 2082 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 9074 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 320469 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 297 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 90636 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 43093 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1513 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewDispatchedInsts 292335 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 81609 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1451 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 472 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2728 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 265301 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 88817 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2824 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 411 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2165 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2576 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 243135 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 80226 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2101 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 44015 # number of nop insts executed -system.cpu1.iew.exec_refs 130506 # number of memory reference insts executed -system.cpu1.iew.exec_branches 54427 # Number of branches executed -system.cpu1.iew.exec_stores 41689 # Number of stores executed -system.cpu1.iew.exec_rate 1.360958 # Inst execution rate -system.cpu1.iew.wb_sent 264333 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 263753 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 148277 # num instructions producing a value -system.cpu1.iew.wb_consumers 156026 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.353017 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.950335 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 27498 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6493 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 2530 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 181716 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.612048 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.042470 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 40272 # number of nop insts executed +system.cpu1.iew.exec_refs 117151 # number of memory reference insts executed +system.cpu1.iew.exec_branches 50431 # Number of branches executed +system.cpu1.iew.exec_stores 36925 # Number of stores executed +system.cpu1.iew.exec_rate 1.282635 # Inst execution rate +system.cpu1.iew.wb_sent 242358 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 241932 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 135113 # num instructions producing a value +system.cpu1.iew.wb_consumers 142615 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.276289 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.947397 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 22606 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7586 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2004 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 178491 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.510961 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.003537 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77632 42.72% 42.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 50511 27.80% 70.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5466 3.01% 73.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7144 3.93% 77.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1253 0.69% 78.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 36670 20.18% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 792 0.44% 98.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1038 0.57% 99.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1210 0.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 81773 45.81% 45.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 46692 26.16% 71.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5286 2.96% 74.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8258 4.63% 79.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1311 0.73% 80.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 32106 17.99% 98.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 812 0.45% 98.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1015 0.57% 99.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1238 0.69% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 181716 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 292935 # Number of instructions committed -system.cpu1.commit.committedOps 292935 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 178491 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 269693 # Number of instructions committed +system.cpu1.commit.committedOps 269693 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 126064 # Number of memory references committed -system.cpu1.commit.loads 85797 # Number of loads committed -system.cpu1.commit.membars 5779 # Number of memory barriers committed -system.cpu1.commit.branches 52007 # Number of branches committed +system.cpu1.commit.refs 113352 # Number of memory references committed +system.cpu1.commit.loads 77688 # Number of loads committed +system.cpu1.commit.membars 6874 # Number of memory barriers committed +system.cpu1.commit.branches 48495 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 200194 # Number of committed integer instructions. +system.cpu1.commit.int_insts 183974 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 42797 14.61% 14.61% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 118295 40.38% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 91576 31.26% 86.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 40267 13.75% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 39287 14.57% 14.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 110180 40.85% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84562 31.35% 86.78% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 35664 13.22% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 292935 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1210 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 500353 # The number of ROB reads -system.cpu1.rob.rob_writes 646173 # The number of ROB writes -system.cpu1.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 7971 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 49399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 244359 # Number of Instructions Simulated -system.cpu1.committedOps 244359 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.797748 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.797748 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.253528 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.253528 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 456218 # number of integer regfile reads -system.cpu1.int_regfile_writes 213064 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 269693 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1238 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 468966 # The number of ROB reads +system.cpu1.rob.rob_writes 588835 # The number of ROB writes +system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6875 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 49435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 223532 # Number of Instructions Simulated +system.cpu1.committedOps 223532 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.848017 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.848017 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.179221 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.179221 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 414823 # number of integer regfile reads +system.cpu1.int_regfile_writes 193738 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 132445 # number of misc regfile reads +system.cpu1.misc_regfile_reads 118957 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.060700 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 47652 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.585143 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42712 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1537.161290 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1377.806452 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.060700 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052853 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.052853 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.585143 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051924 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051924 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 370474 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 370474 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 51817 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 51817 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 40051 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 40051 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 91868 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 91868 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 91868 # number of overall hits -system.cpu1.dcache.overall_hits::total 91868 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 471 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 471 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 148 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 148 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses -system.cpu1.dcache.overall_misses::total 619 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4841500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4841500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3638000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3638000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 309000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 309000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8479500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8479500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8479500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8479500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 52288 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 52288 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 40199 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 40199 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 92487 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 92487 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 92487 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 92487 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003682 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003682 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.794118 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006693 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006693 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006693 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006693 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10279.193206 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 10279.193206 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24581.081081 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24581.081081 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5722.222222 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 5722.222222 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 13698.707593 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13698.707593 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 336213 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 336213 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 47868 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 47868 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 35447 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 35447 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 83315 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 83315 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 83315 # number of overall hits +system.cpu1.dcache.overall_hits::total 83315 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 458 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 458 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 151 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 151 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 609 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 609 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 609 # number of overall misses +system.cpu1.dcache.overall_misses::total 609 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4693000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4693000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3635500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3635500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 328500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 328500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8328500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8328500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8328500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8328500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 48326 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 48326 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 35598 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 35598 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 83924 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 83924 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 83924 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 83924 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009477 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009477 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004242 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004242 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.757576 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.757576 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007257 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007257 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007257 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007257 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10246.724891 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 10246.724891 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24076.158940 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24076.158940 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6570 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 6570 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13675.697865 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13675.697865 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13675.697865 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13675.697865 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 312 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 44 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 44 # number of WriteReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 1 # number of SwapReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 356 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 356 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 292 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 4 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 339 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 339 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1599000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1599000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1536000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1536000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 255000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 255000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3135000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3135000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3135000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3135000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003041 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003041 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002587 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002587 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.779412 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002844 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002844 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10056.603774 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10056.603774 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14769.230769 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14769.230769 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 4811.320755 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 4811.320755 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 598 # number of replacements -system.cpu1.icache.tags.tagsinuse 99.304712 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25606 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.933151 # Average number of references to valid blocks. +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 46 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 46 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1641000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1641000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1541000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1541000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 278500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 278500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3182000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3182000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3182000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3182000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003435 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003435 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002922 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002922 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.696970 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.696970 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003217 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003217 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003217 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003217 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9885.542169 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9885.542169 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14817.307692 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14817.307692 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6054.347826 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6054.347826 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11785.185185 # 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Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.193955 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.193955 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 27223 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 27223 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 25606 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 25606 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 25606 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 25606 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 25606 # number of overall hits -system.cpu1.icache.overall_hits::total 25606 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 884 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 884 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 884 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 884 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 884 # number of overall misses -system.cpu1.icache.overall_misses::total 884 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 21315000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 21315000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 21315000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 21315000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 21315000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 21315000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 26490 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 26490 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 26490 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 26490 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 26490 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 26490 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033371 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033371 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033371 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033371 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033371 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033371 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24111.990950 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24111.990950 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24111.990950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24111.990950 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 175 # number of cycles access was blocked +system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.467355 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190366 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.190366 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 28295 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 28295 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 26848 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 26848 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 26848 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 26848 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 26848 # number of overall hits +system.cpu1.icache.overall_hits::total 26848 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 804 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 804 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 804 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 804 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 804 # number of overall misses +system.cpu1.icache.overall_misses::total 804 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19785000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 19785000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 19785000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 19785000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 19785000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 19785000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 27652 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 27652 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 27652 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 27652 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 27652 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 27652 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029076 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029076 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029076 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029076 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029076 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029076 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24608.208955 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24608.208955 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24608.208955 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24608.208955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24608.208955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24608.208955 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 598 # number of writebacks -system.cpu1.icache.writebacks::total 598 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 151 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 151 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 151 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 151 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 151 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 151 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 733 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 733 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 733 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 733 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 16848000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 16848000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 16848000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 16848000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027671 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027671 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22984.993179 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency -system.cpu2.branchPred.lookups 65968 # Number of BP lookups -system.cpu2.branchPred.condPredicted 58235 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2375 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 57871 # Number of BTB lookups +system.cpu1.icache.writebacks::writebacks 507 # number of writebacks +system.cpu1.icache.writebacks::total 507 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 161 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 161 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 161 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 161 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 161 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 643 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 643 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 643 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 643 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15397000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 15397000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15397000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 15397000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15397000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 15397000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023253 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023253 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023253 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23945.567652 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23945.567652 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23945.567652 # average overall mshr miss latency +system.cpu2.branchPred.lookups 68293 # Number of BP lookups +system.cpu2.branchPred.condPredicted 60753 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2314 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 60518 # Number of BTB lookups system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1935 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.usedRAS 1899 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 57871 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 47609 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 10262 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 1269 # Number of mispredicted indirect branches. -system.cpu2.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 194536 # number of cpu cycles simulated +system.cpu2.branchPred.indirectLookups 60518 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 50086 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10432 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1220 # Number of mispredicted indirect branches. +system.cpu2.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 189148 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 39274 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 356927 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 65968 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 49544 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 148178 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4907 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 37019 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 374433 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 68293 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 51985 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 146261 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4785 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1834 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 28474 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 909 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 191752 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.861399 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.326800 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 25650 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 889 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 187354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.998532 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.363195 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 72282 37.70% 37.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 59093 30.82% 68.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8567 4.47% 72.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3453 1.80% 74.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 714 0.37% 75.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36701 19.14% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1094 0.57% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 1368 0.71% 95.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 8480 4.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 64471 34.41% 34.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 60026 32.04% 66.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7128 3.80% 70.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3545 1.89% 72.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 670 0.36% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 40604 21.67% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1041 0.56% 94.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1382 0.74% 95.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8487 4.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 191752 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.339104 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.834761 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 22274 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 72146 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 90170 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4699 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2453 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 325978 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2453 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 23346 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 35274 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13410 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90655 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 26604 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 319217 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 22687 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 187354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.361056 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.979577 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 21923 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 61377 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 97674 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3978 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2392 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 343665 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2392 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 22954 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 28666 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13829 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 98633 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20870 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 337053 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18126 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 222060 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 604225 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 470469 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 194795 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 27265 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1650 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1793 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 32366 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 87706 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 41007 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 42125 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34727 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 259651 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8925 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 260809 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 24016 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18768 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 191752 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.360137 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.380681 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 236414 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 645955 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 501894 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 22 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 208648 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 27766 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1626 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1738 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 26523 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 93867 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 44893 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 44587 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 38578 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275945 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7527 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 275850 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 23937 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18592 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1173 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 187354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.472346 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.381832 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 77057 40.19% 40.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 28387 14.80% 54.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39839 20.78% 75.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 39454 20.58% 96.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3531 1.84% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1665 0.87% 99.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1093 0.57% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 433 0.23% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 293 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68951 36.80% 36.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 24397 13.02% 49.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 43633 23.29% 73.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 43435 23.18% 96.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3472 1.85% 98.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1779 0.95% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1003 0.54% 99.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 391 0.21% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 293 0.16% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 191752 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 187354 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 214 43.32% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMisc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 44 8.91% 52.23% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 236 47.77% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 191 39.71% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMisc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 64 13.31% 53.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 226 46.99% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 127216 48.78% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 93561 35.87% 84.65% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 40032 15.35% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 133523 48.40% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 98433 35.68% 84.09% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 43894 15.91% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 260809 # Type of FU issued -system.cpu2.iq.rate 1.340672 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 494 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001894 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713946 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 292577 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 257120 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 275850 # Type of FU issued +system.cpu2.iq.rate 1.458382 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 481 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001744 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 739606 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 307404 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272120 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_writes 44 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 261303 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 276331 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34638 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 38492 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 4387 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 2568 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 4293 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 47 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2655 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2453 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9291 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 312015 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 352 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 87706 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 41007 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1521 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2392 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 7918 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 329268 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 414 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 93867 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 44893 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1518 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 454 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 2525 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 2979 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 258429 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 86072 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 2380 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2459 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 2902 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273426 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 92301 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2424 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 43439 # number of nop insts executed -system.cpu2.iew.exec_refs 125830 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53606 # Number of branches executed -system.cpu2.iew.exec_stores 39758 # Number of stores executed -system.cpu2.iew.exec_rate 1.328438 # Inst execution rate -system.cpu2.iew.wb_sent 257596 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 257120 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 143610 # num instructions producing a value -system.cpu2.iew.wb_consumers 151220 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.321709 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.949676 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 25270 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7691 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 2375 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 186904 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.534044 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.009689 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 45796 # number of nop insts executed +system.cpu2.iew.exec_refs 135892 # number of memory reference insts executed +system.cpu2.iew.exec_branches 56020 # Number of branches executed +system.cpu2.iew.exec_stores 43591 # Number of stores executed +system.cpu2.iew.exec_rate 1.445566 # Inst execution rate +system.cpu2.iew.wb_sent 272582 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272120 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 153730 # num instructions producing a value +system.cpu2.iew.wb_consumers 161299 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.438662 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.953075 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 25088 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6354 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2314 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 182587 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.665803 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.057645 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 84130 45.01% 45.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 49844 26.67% 71.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5407 2.89% 74.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8359 4.47% 79.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1323 0.71% 79.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34855 18.65% 98.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 714 0.38% 98.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1043 0.56% 99.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1229 0.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 74839 40.99% 40.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 52317 28.65% 69.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5497 3.01% 72.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6991 3.83% 76.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1341 0.73% 77.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 38632 21.16% 98.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 681 0.37% 98.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1052 0.58% 99.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1237 0.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 186904 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 286719 # Number of instructions committed -system.cpu2.commit.committedOps 286719 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 182587 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 304154 # Number of instructions committed +system.cpu2.commit.committedOps 304154 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 121758 # Number of memory references committed -system.cpu2.commit.loads 83319 # Number of loads committed -system.cpu2.commit.membars 6971 # Number of memory barriers committed -system.cpu2.commit.branches 51375 # Number of branches committed +system.cpu2.commit.refs 131812 # Number of memory references committed +system.cpu2.commit.loads 89574 # Number of loads committed +system.cpu2.commit.membars 5632 # Number of memory barriers committed +system.cpu2.commit.branches 53837 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 195248 # Number of committed integer instructions. +system.cpu2.commit.int_insts 207761 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 42159 14.70% 14.70% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 115831 40.40% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 90290 31.49% 86.59% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38439 13.41% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 44619 14.67% 14.67% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 122091 40.14% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 95206 31.30% 86.11% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 42238 13.89% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 286719 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1229 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 497078 # The number of ROB reads -system.cpu2.rob.rob_writes 628878 # The number of ROB writes -system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 2784 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 49801 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 237589 # Number of Instructions Simulated -system.cpu2.committedOps 237589 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.818792 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.818792 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.221311 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.221311 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 441330 # number of integer regfile reads -system.cpu2.int_regfile_writes 205867 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 304154 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1237 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 510006 # The number of ROB reads +system.cpu2.rob.rob_writes 663292 # The number of ROB writes +system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1794 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 49847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 253903 # Number of Instructions Simulated +system.cpu2.committedOps 253903 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.744962 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.744962 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.342351 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.342351 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 471960 # number of integer regfile reads +system.cpu2.int_regfile_writes 219741 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 127741 # number of misc regfile reads +system.cpu2.misc_regfile_reads 137767 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.326014 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 45457 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 25.074061 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 49166 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1567.482759 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1695.379310 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.326014 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.049465 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.049465 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.074061 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.048973 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.048973 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 359653 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 359653 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 50904 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50904 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 38221 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 38221 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 89125 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 89125 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 89125 # number of overall hits -system.cpu2.dcache.overall_hits::total 89125 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 505 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 505 # number of ReadReq misses +system.cpu2.dcache.tags.tag_accesses 384293 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 384293 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.ReadReq_hits::cpu2.data 53240 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 53240 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 42018 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 42018 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 95258 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 95258 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 95258 # number of overall hits +system.cpu2.dcache.overall_hits::total 95258 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 144 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 144 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 649 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 649 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 649 # number of overall misses -system.cpu2.dcache.overall_misses::total 649 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3857000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3857000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3021500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3021500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 367000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 367000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6878500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6878500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6878500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6878500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 51409 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 51409 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38365 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38365 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 89774 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 89774 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 89774 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 89774 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009823 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009823 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003753 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003753 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.837838 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.837838 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007229 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007229 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007229 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007229 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7637.623762 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 7637.623762 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20982.638889 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20982.638889 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5919.354839 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 5919.354839 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10598.613251 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 10598.613251 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10598.613251 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 10598.613251 # average overall miss latency +system.cpu2.dcache.SwapReq_misses::cpu2.data 65 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 65 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 673 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 673 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 673 # number of overall misses +system.cpu2.dcache.overall_misses::total 673 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 4007500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 4007500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3035500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3035500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 419500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 419500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 7043000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 7043000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 7043000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 7043000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 53769 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 53769 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 42162 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 42162 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 95931 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 95931 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 95931 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 95931 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009838 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009838 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003415 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003415 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.855263 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.855263 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007015 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007015 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007015 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007015 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7575.614367 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 7575.614367 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21079.861111 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 21079.861111 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6453.846154 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 6453.846154 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10465.081724 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 10465.081724 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10465.081724 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 10465.081724 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 337 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 337 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 358 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 378 # 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number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 305000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 305000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2566000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2566000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2566000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2566000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003268 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003268 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002685 # 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average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14082.524272 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 4919.354839 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 4919.354839 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 551 # number of replacements -system.cpu2.icache.tags.tagsinuse 96.895068 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 27659 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 687 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 40.260553 # Average number of references to valid blocks. +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 64 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 64 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1122000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1122000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1473000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1473000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 354500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 354500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2595000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2595000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2595000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2595000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003180 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003180 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002443 # 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average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14300.970874 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5539.062500 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5539.062500 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9470.802920 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9470.802920 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9470.802920 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9470.802920 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.tags.replacements 575 # number of replacements +system.cpu2.icache.tags.tagsinuse 93.413944 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 24822 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 707 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 35.108911 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 96.895068 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.189248 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.189248 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 29161 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 29161 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 27659 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 27659 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 27659 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 27659 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 27659 # number of overall hits -system.cpu2.icache.overall_hits::total 27659 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 815 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 815 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 815 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 815 # 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number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 28474 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 28474 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028623 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.028623 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028623 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.028623 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028623 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.028623 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15806.134969 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15806.134969 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15806.134969 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15806.134969 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu2.icache.tags.occ_blocks::cpu2.inst 93.413944 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.182449 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.182449 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 132 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.257812 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 26357 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 26357 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.ReadReq_hits::cpu2.inst 24822 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 24822 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 24822 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 24822 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 24822 # number of overall hits +system.cpu2.icache.overall_hits::total 24822 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 828 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 828 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 828 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 828 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 828 # number of overall misses +system.cpu2.icache.overall_misses::total 828 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12872000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 12872000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 12872000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 12872000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 12872000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 12872000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 25650 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 25650 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 25650 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 25650 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 25650 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 25650 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.032281 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.032281 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.032281 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.032281 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.032281 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.032281 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15545.893720 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15545.893720 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15545.893720 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15545.893720 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15545.893720 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15545.893720 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 551 # number of writebacks -system.cpu2.icache.writebacks::total 551 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 128 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 128 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 128 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 128 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 687 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 687 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 687 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 687 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10903000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10903000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10903000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10903000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10903000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10903000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.024127 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.024127 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15870.451237 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency -system.cpu3.branchPred.lookups 64271 # Number of BP lookups -system.cpu3.branchPred.condPredicted 56758 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 2271 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 55794 # Number of BTB lookups +system.cpu2.icache.writebacks::writebacks 575 # number of writebacks +system.cpu2.icache.writebacks::total 575 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 121 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 121 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 121 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 121 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 707 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 707 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 707 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 707 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 707 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 707 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 11018000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 11018000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 11018000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 11018000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 11018000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 11018000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.027563 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.027563 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.027563 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15584.158416 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 15584.158416 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 15584.158416 # average overall mshr miss latency +system.cpu3.branchPred.lookups 62938 # Number of BP lookups +system.cpu3.branchPred.condPredicted 55062 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2421 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 53856 # Number of BTB lookups system.cpu3.branchPred.BTBHits 0 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 1884 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.usedRAS 2064 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 55794 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 46245 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 9549 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 1200 # Number of mispredicted indirect branches. -system.cpu3.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 194168 # number of cpu cycles simulated +system.cpu3.branchPred.indirectLookups 53856 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 44056 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 9800 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches. +system.cpu3.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 188742 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 40168 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 346607 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 64271 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 48129 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 146969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4697 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 40214 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 338441 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 62938 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46120 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 142180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4995 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1673 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 29039 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 911 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 191171 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.813073 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.312592 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1755 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 28914 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 967 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 186659 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.813151 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.333247 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 74400 38.92% 38.92% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 57993 30.34% 69.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8887 4.65% 73.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3426 1.79% 75.69% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 613 0.32% 76.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 35081 18.35% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1105 0.58% 94.94% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 1253 0.66% 95.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 8413 4.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 73605 39.43% 39.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55869 29.93% 69.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8647 4.63% 74.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3452 1.85% 75.85% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 624 0.33% 76.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 33274 17.83% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1074 0.58% 94.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1300 0.70% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8814 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 191171 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.331007 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.785088 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 21895 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 75534 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 86562 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4822 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2348 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 316867 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2348 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 22878 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 37474 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13003 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 86814 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 28644 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 310654 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 24310 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full -system.cpu3.rename.RenamedOperands 215725 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 585696 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 456528 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 32 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 188410 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 27315 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1561 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1705 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 33909 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84645 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 39227 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40799 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 33015 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 251387 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9227 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 253114 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 23294 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 18618 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 1117 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 191171 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.324019 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377234 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 186659 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.333460 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.793141 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 22716 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 73421 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 83265 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4750 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2497 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 307410 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2497 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 23704 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 36346 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12933 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 84283 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 26886 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 301080 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 23387 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 210366 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 567874 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 443450 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 24 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 181055 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 29311 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1630 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1783 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 32120 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 81178 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 37704 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 38749 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 31258 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 243640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9008 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 244569 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 25003 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 20491 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1173 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 186659 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.310245 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.388449 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 78925 41.29% 41.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 29485 15.42% 56.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 37890 19.82% 76.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 37772 19.76% 96.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3652 1.91% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1740 0.91% 99.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 1013 0.53% 99.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 405 0.21% 99.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 289 0.15% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 78461 42.03% 42.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28833 15.45% 57.48% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 36126 19.35% 76.84% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 35957 19.26% 96.10% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3664 1.96% 98.06% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1804 0.97% 99.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1069 0.57% 99.60% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 437 0.23% 99.83% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 308 0.17% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 191171 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 186659 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 186 40.88% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMisc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 39 8.57% 49.45% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 230 50.55% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 212 43.80% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMisc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 41 8.47% 52.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 231 47.73% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 123835 48.92% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 91015 35.96% 84.88% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 38264 15.12% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 120712 49.36% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 87244 35.67% 85.03% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 36613 14.97% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 253114 # Type of FU issued -system.cpu3.iq.rate 1.303582 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 455 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001798 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 697933 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 283879 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 249400 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 244569 # Type of FU issued +system.cpu3.iq.rate 1.295785 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 484 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001979 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 676366 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 277636 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 240444 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 253569 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 245053 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 32960 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 31180 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 4297 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 2496 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 4645 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 43 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2744 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 9647 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 302650 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 426 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84645 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 39227 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1449 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2497 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 9575 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 292625 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 421 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 81178 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 37704 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1504 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 408 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 2445 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2853 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 250680 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83030 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 2434 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 434 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2602 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3036 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 241934 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 79457 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2635 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 42036 # number of nop insts executed -system.cpu3.iew.exec_refs 121032 # number of memory reference insts executed -system.cpu3.iew.exec_branches 52206 # Number of branches executed -system.cpu3.iew.exec_stores 38002 # Number of stores executed -system.cpu3.iew.exec_rate 1.291047 # Inst execution rate -system.cpu3.iew.wb_sent 249859 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 249400 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 138774 # num instructions producing a value -system.cpu3.iew.wb_consumers 146167 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.284455 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.949421 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 24422 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8110 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2271 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 186514 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.491588 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.991895 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 39977 # number of nop insts executed +system.cpu3.iew.exec_refs 115781 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50244 # Number of branches executed +system.cpu3.iew.exec_stores 36324 # Number of stores executed +system.cpu3.iew.exec_rate 1.281824 # Inst execution rate +system.cpu3.iew.wb_sent 241008 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 240444 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 133441 # num instructions producing a value +system.cpu3.iew.wb_consumers 140864 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.273929 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.947304 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 26116 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7835 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2421 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 181669 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.466860 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.985223 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 86424 46.34% 46.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48393 25.95% 72.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5395 2.89% 75.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8809 4.72% 79.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1333 0.71% 80.61% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 33156 17.78% 98.39% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 761 0.41% 98.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1030 0.55% 99.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1213 0.65% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 85663 47.15% 47.15% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 46447 25.57% 72.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5344 2.94% 75.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8472 4.66% 80.33% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1289 0.71% 81.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 31374 17.27% 98.30% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 856 0.47% 98.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1022 0.56% 99.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1202 0.66% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 186514 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 278202 # Number of instructions committed -system.cpu3.commit.committedOps 278202 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 181669 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 266483 # Number of instructions committed +system.cpu3.commit.committedOps 266483 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 117079 # Number of memory references committed -system.cpu3.commit.loads 80348 # Number of loads committed -system.cpu3.commit.membars 7398 # Number of memory barriers committed -system.cpu3.commit.branches 50090 # Number of branches committed +system.cpu3.commit.refs 111493 # Number of memory references committed +system.cpu3.commit.loads 76533 # Number of loads committed +system.cpu3.commit.membars 7123 # Number of memory barriers committed +system.cpu3.commit.branches 48046 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 189293 # Number of committed integer instructions. +system.cpu3.commit.int_insts 181662 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 40882 14.70% 14.70% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 112843 40.56% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 87746 31.54% 86.80% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 36731 13.20% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 38838 14.57% 14.57% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 109029 40.91% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 83656 31.39% 86.88% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 34960 13.12% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 278202 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1213 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 487339 # The number of ROB reads -system.cpu3.rob.rob_writes 609957 # The number of ROB writes -system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 50169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 229922 # Number of Instructions Simulated -system.cpu3.committedOps 229922 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.844495 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.844495 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.184140 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.184140 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 426644 # number of integer regfile reads -system.cpu3.int_regfile_writes 199085 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 266483 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1202 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 472480 # The number of ROB reads +system.cpu3.rob.rob_writes 590253 # The number of ROB writes +system.cpu3.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2083 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 50253 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 220522 # Number of Instructions Simulated +system.cpu3.committedOps 220522 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.855887 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.855887 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.168378 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.168378 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 411294 # number of integer regfile reads +system.cpu3.int_regfile_writes 192402 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 122920 # number of misc regfile reads +system.cpu3.misc_regfile_reads 117678 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.889715 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 43728 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1457.600000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.245200 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 42083 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1451.137931 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.889715 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048613 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.048613 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 347346 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 347346 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 49561 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 49561 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 36521 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 36521 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 86082 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 86082 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 86082 # number of overall hits -system.cpu3.dcache.overall_hits::total 86082 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 482 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 144 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 144 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 626 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 626 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 626 # number of overall misses -system.cpu3.dcache.overall_misses::total 626 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4340000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4340000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3297000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3297000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 320500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 320500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7637000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7637000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7637000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7637000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 50043 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 50043 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 36665 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 36665 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.245200 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047354 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047354 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 333051 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 333051 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.ReadReq_hits::cpu3.data 47761 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 47761 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 34756 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 34756 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 82517 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 82517 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 82517 # number of overall hits +system.cpu3.dcache.overall_hits::total 82517 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 480 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 618 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 618 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 618 # number of overall misses +system.cpu3.dcache.overall_misses::total 618 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4264500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4264500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3342000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3342000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 357000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 357000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7606500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7606500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7606500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7606500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48241 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48241 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 34894 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 34894 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 66 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 86708 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 86708 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 86708 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 86708 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009632 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.009632 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003927 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003927 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.787879 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007220 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007220 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007220 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007220 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 9004.149378 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 9004.149378 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22895.833333 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 22895.833333 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6163.461538 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 6163.461538 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 12199.680511 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 12199.680511 # average overall miss latency +system.cpu3.dcache.demand_accesses::cpu3.data 83135 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 83135 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 83135 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 83135 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009950 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009950 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003955 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003955 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.803030 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.803030 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007434 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007434 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007434 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007434 # 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number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 322 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 40 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 362 # 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mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7756.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7756.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15682.692308 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15682.692308 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5264.705882 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5264.705882 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 575 # number of replacements -system.cpu3.icache.tags.tagsinuse 93.289458 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 28201 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 712 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 39.608146 # Average number of references to valid blocks. +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 324 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 324 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 355 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 355 # 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number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1092500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1092500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1676500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1676500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 304000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 304000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2769000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2769000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2769000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2769000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003234 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003234 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003066 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003066 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.803030 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.803030 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003164 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003164 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7003.205128 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7003.205128 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15668.224299 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15668.224299 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5735.849057 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5735.849057 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10528.517110 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10528.517110 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10528.517110 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10528.517110 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.tags.replacements 578 # number of replacements +system.cpu3.icache.tags.tagsinuse 92.244162 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 28072 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 714 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 39.316527 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.289458 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.182206 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.182206 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 92.244162 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.180164 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.180164 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.267578 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 29751 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 29751 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 28201 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 28201 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 28201 # 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Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 29628 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 29628 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.ReadReq_hits::cpu3.inst 28072 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 28072 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 28072 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 28072 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 28072 # number of overall hits +system.cpu3.icache.overall_hits::total 28072 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 842 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 842 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 842 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 842 # 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mshr miss rate for overall accesses -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74707.446809 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75076.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75208.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89958.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76187.022901 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 76750 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 159150 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 78272.448980 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80822.368421 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75222.222222 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 103000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80972.222222 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 961 # Total number of requests made to the snoop filter. +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.018207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.236236 # mshr miss rate for overall accesses +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74457.446809 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73923.076923 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 77750 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 92083.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76320.610687 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72800 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75593.047035 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78100 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 89750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78119.318182 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76073.964497 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78035.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 91750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 76041.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76073.964497 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78035.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 91750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 76041.666667 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 958 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 251 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 579 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193 # Transaction distribution -system.membus.trans_dist::ReadExReq 189 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 576 # Transaction distribution +system.membus.trans_dist::UpgradeReq 200 # Transaction distribution +system.membus.trans_dist::ReadExReq 182 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 579 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1671 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1671 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45440 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1665 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 251 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 961 # Request fanout histogram +system.membus.snoop_fanout::samples 958 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 961 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 958 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 961 # Request fanout histogram -system.membus.reqLayer0.occupancy 879000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 958 # Request fanout histogram +system.membus.reqLayer0.occupancy 881500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3778500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3759250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 6307 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1711 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3247 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 6160 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1652 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3166 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 3510 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadResp 3429 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2115 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2041 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 399 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 399 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2829 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 685 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1784 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 594 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1925 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1999 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2746 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 686 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1744 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1793 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1989 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 384 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2006 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9472 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9243 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 67968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 73600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 79232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82048 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 332608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1024 # Total snoops (count) -system.toL2Bus.snoopTraffic 53184 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4190 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.302625 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.130775 # Request fanout histogram +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 322432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1033 # Total snoops (count) +system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4117 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.305805 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.138383 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1349 32.20% 32.20% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1111 26.52% 58.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 843 20.12% 78.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 887 21.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1342 32.60% 32.60% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1062 25.80% 58.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 825 20.04% 78.43% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 888 21.57% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2933,24 +2925,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4190 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5284470 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1044996 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4117 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5135473 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1023494 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 522995 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 524487 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1103492 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 425474 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 967494 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 424479 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1034985 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 441461 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1065487 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 451954 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1070994 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1072994 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 421970 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 419968 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |