diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 4528 |
1 files changed, 2269 insertions, 2259 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 10d3d1f6f..d8e803150 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000124 # Number of seconds simulated -sim_ticks 123936000 # Number of ticks simulated -final_tick 123936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000125 # Number of seconds simulated +sim_ticks 124830000 # Number of ticks simulated +final_tick 124830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188054 # Simulator instruction rate (inst/s) -host_op_rate 188053 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20091950 # Simulator tick rate (ticks/s) -host_mem_usage 268856 # Number of bytes of host memory used -host_seconds 6.17 # Real time elapsed on the host -sim_insts 1159992 # Number of instructions simulated -sim_ops 1159992 # Number of ops (including micro ops) simulated +host_inst_rate 147575 # Simulator instruction rate (inst/s) +host_op_rate 147575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15906234 # Simulator tick rate (ticks/s) +host_mem_usage 266768 # Number of bytes of host memory used +host_seconds 7.85 # Real time elapsed on the host +sim_insts 1158143 # Number of instructions simulated +sim_ops 1158143 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 24064 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory -system.physmem.bytes_read::total 45376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 24064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5696 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 45824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 376 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu3.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31680 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 89 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory -system.physmem.num_reads::total 709 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 194164730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 87787245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45959205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10844307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 7229538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7745933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 5163956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7229538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 366124451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 194164730 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45959205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 7229538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 5163956 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 252517428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 194164730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 87787245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45959205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 10844307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 7229538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7745933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 5163956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7229538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 366124451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 709 # Number of read requests accepted +system.physmem.num_reads::total 716 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 192261476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 87158536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47168149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11279340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 7177762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7690459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 7177762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7177762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 367091244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192261476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47168149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 7177762 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 7177762 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253785148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192261476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 87158536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47168149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11279340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 7177762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7690459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 7177762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7177762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 367091244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 716 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 709 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 716 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 45376 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 45824 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 45376 # Total read bytes from the system interface side +system.physmem.bytesReadSys 45824 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 120 # Per bank write bursts system.physmem.perBankRdBursts::1 44 # Per bank write bursts -system.physmem.perBankRdBursts::2 31 # Per bank write bursts -system.physmem.perBankRdBursts::3 62 # Per bank write bursts +system.physmem.perBankRdBursts::2 33 # Per bank write bursts +system.physmem.perBankRdBursts::3 63 # Per bank write bursts system.physmem.perBankRdBursts::4 69 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts system.physmem.perBankRdBursts::6 19 # Per bank write bursts -system.physmem.perBankRdBursts::7 28 # Per bank write bursts +system.physmem.perBankRdBursts::7 27 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts system.physmem.perBankRdBursts::9 31 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts -system.physmem.perBankRdBursts::12 69 # Per bank write bursts -system.physmem.perBankRdBursts::13 45 # Per bank write bursts +system.physmem.perBankRdBursts::12 72 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts system.physmem.perBankRdBursts::14 19 # Per bank write bursts system.physmem.perBankRdBursts::15 101 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 123701000 # Total gap between requests +system.physmem.totGap 124590000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 709 # Read request sizes (log2) +system.physmem.readPktSize::6 716 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -121,10 +121,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -217,211 +217,221 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.076923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.451829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.101340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 63 37.28% 37.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 23.08% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 16.57% 76.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 7.69% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 4.73% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 4.73% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.78% 95.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation -system.physmem.totQLat 6766000 # Total ticks spent queuing -system.physmem.totMemAccLat 20059750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9543.02 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.758718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 247.924177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 67 38.51% 38.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43 24.71% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 26 14.94% 78.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 6.90% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 4.02% 89.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 4.60% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.72% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.15% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 3.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 174 # Bytes accessed per row activation +system.physmem.totQLat 12446750 # Total ticks spent queuing +system.physmem.totMemAccLat 25871750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17383.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28293.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 366.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36133.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 367.09 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 366.12 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 367.09 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.86 # Data bus utilization in percentage -system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.87 # Data bus utilization in percentage +system.physmem.busUtilRead 2.87 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 528 # Number of row buffer hits during reads +system.physmem.readRowHits 530 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.47 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.02 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 174472.50 # Average gap between requests -system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 831600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 453750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2925000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 174008.38 # Average gap between requests +system.physmem.pageHitRate 74.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 856800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 432630 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 49377960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 26918250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88134960 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.944352 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47288500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3900000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 68692500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 408240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 222750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6410790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 304320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 34392090 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 13115040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 649140.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 68872470 # Total energy per rank (pJ) +system.physmem_0.averagePower 551.730113 # Core power per rank (mW) +system.physmem_0.totalIdleTime 109416750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 358500 # Time in different power states +system.physmem_0.memoryStateTime::REF 4166000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 403000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 34152000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 10318500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 75432000 # Time in different power states +system.physmem_1.actEnergy 471240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 227700 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2234820 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 42901335 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32591250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 85935975 # Total energy per rank (pJ) -system.physmem_1.averagePower 734.244489 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54352750 # Time in different power states -system.physmem_1.memoryStateTime::REF 3900000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 59251250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 98531 # Number of BP lookups -system.cpu0.branchPred.condPredicted 94014 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1575 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 95788 # Number of BTB lookups +system.physmem_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5188140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 617280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 32401650 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 11725440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 3565380 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 66265890 # Total energy per rank (pJ) +system.physmem_1.averagePower 530.849075 # Core power per rank (mW) +system.physmem_1.totalIdleTime 111659250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1125500 # Time in different power states +system.physmem_1.memoryStateTime::REF 4172000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 10253750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 30535250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 71064000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 98509 # Number of BP lookups +system.cpu0.branchPred.condPredicted 93993 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1599 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 95823 # Number of BTB lookups system.cpu0.branchPred.BTBHits 0 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1142 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 95788 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 88519 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 7269 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 1054 # Number of mispredicted indirect branches. +system.cpu0.branchPred.indirectLookups 95823 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 88367 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 7456 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 1077 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 247873 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 249661 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 23367 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 581451 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 98531 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 89661 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 193123 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3449 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.icacheStallCycles 22650 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 581099 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 98509 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89482 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 193985 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3497 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 78 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2208 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 2191 # Number of stall cycles due to pending traps system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7997 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 861 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.CacheLines 7995 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 871 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 220500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.636966 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.261585 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 220664 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.633411 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.264413 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33425 15.16% 15.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 91538 41.51% 56.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 694 0.31% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1015 0.46% 57.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 497 0.23% 57.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 87060 39.48% 97.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 731 0.33% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 514 0.23% 97.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5026 2.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33866 15.35% 15.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 91353 41.40% 56.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 668 0.30% 57.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 983 0.45% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 516 0.23% 57.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 86959 39.41% 97.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 734 0.33% 97.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 482 0.22% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5103 2.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 220500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.397506 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.345762 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17843 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18591 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 181526 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 816 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1724 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 563984 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1724 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18505 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1935 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15328 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 181668 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1340 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 558880 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 220664 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.394571 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.327552 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17658 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19166 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 181260 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1748 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 563638 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1748 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18349 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2015 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15764 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 181386 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1402 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 558452 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 382489 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1113780 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 841332 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 363591 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 18898 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1094 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1121 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5347 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 178321 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90063 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 86944 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 86670 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 466208 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1118 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 462266 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 16406 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13115 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 559 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 220500 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.096444 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.103875 # Number of insts issued each cycle +system.cpu0.rename.SQFullEvents 925 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 382172 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1112707 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 840550 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 362927 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 19245 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1073 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1102 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5312 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 178069 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 89965 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 86828 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 86540 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 465662 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1094 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 461556 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 16666 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13597 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 535 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 220664 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.091669 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.110492 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 36239 16.43% 16.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4459 2.02% 18.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 88275 40.03% 58.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 87972 39.90% 98.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 988 0.45% 99.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 572 0.26% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 195 0.09% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 101 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 36803 16.68% 16.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4402 1.99% 18.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 88094 39.92% 58.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 87764 39.77% 98.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 985 0.45% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 247 0.11% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 102 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 220500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 220664 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 126 38.77% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 78 24.00% 62.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 121 37.23% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 129 39.09% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 77 23.33% 62.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 124 37.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 195215 42.23% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 194924 42.23% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued @@ -450,94 +460,94 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 177740 38.45% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 89311 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 177454 38.45% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 89178 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 462266 # Type of FU issued -system.cpu0.iq.rate 1.864931 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 325 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000703 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1145469 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 483779 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 459725 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 461556 # Type of FU issued +system.cpu0.iq.rate 1.848731 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 330 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1144224 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 483466 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 458888 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 462591 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 461886 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 86430 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 86265 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2936 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 3016 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1932 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1933 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 554898 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 178321 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90063 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1001 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1748 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2015 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 554202 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 178069 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 89965 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1693 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1922 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 460834 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 177384 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1432 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1714 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1946 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 460023 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 177079 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1533 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 87572 # number of nop insts executed -system.cpu0.iew.exec_refs 266499 # number of memory reference insts executed -system.cpu0.iew.exec_branches 91565 # Number of branches executed -system.cpu0.iew.exec_stores 89115 # Number of stores executed -system.cpu0.iew.exec_rate 1.859154 # Inst execution rate -system.cpu0.iew.wb_sent 460184 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 459725 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 272583 # num instructions producing a value -system.cpu0.iew.wb_consumers 276120 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.854680 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.987190 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 17076 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 87446 # number of nop insts executed +system.cpu0.iew.exec_refs 266047 # number of memory reference insts executed +system.cpu0.iew.exec_branches 91396 # Number of branches executed +system.cpu0.iew.exec_stores 88968 # Number of stores executed +system.cpu0.iew.exec_rate 1.842591 # Inst execution rate +system.cpu0.iew.wb_sent 459364 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 458888 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 272127 # num instructions producing a value +system.cpu0.iew.wb_consumers 275688 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.838044 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987083 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 17379 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1575 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 217161 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.476218 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.140669 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1599 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 217244 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.470687 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.142582 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 36214 16.68% 16.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90367 41.61% 58.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2049 0.94% 59.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 624 0.29% 59.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 510 0.23% 59.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 86212 39.70% 99.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 445 0.20% 99.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 289 0.13% 99.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 451 0.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 36715 16.90% 16.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 90144 41.49% 58.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2018 0.93% 59.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 613 0.28% 59.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 486 0.22% 59.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 86051 39.61% 99.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 459 0.21% 99.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 294 0.14% 99.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 464 0.21% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 217161 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 537738 # Number of instructions committed -system.cpu0.commit.committedOps 537738 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 217244 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 536742 # Number of instructions committed +system.cpu0.commit.committedOps 536742 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 263584 # Number of memory references committed -system.cpu0.commit.loads 175385 # Number of loads committed +system.cpu0.commit.refs 263086 # Number of memory references committed +system.cpu0.commit.loads 175053 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 90086 # Number of branches committed +system.cpu0.commit.branches 89920 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 361922 # Number of committed integer instructions. +system.cpu0.commit.int_insts 361258 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 86818 16.15% 16.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 187252 34.82% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 86652 16.14% 16.14% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 186920 34.82% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction @@ -566,2071 +576,2071 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 175469 32.63% 83.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 88199 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 175137 32.63% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 88033 16.40% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 537738 # Class of committed instruction -system.cpu0.commit.bw_lim_events 451 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 770363 # The number of ROB reads -system.cpu0.rob.rob_writes 1113018 # The number of ROB writes -system.cpu0.timesIdled 321 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27373 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 450836 # Number of Instructions Simulated -system.cpu0.committedOps 450836 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.549807 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.549807 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.818819 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.818819 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 823745 # number of integer regfile reads -system.cpu0.int_regfile_writes 371341 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 536742 # Class of committed instruction +system.cpu0.commit.bw_lim_events 464 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 769740 # The number of ROB reads +system.cpu0.rob.rob_writes 1111721 # The number of ROB writes +system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 450006 # Number of Instructions Simulated +system.cpu0.committedOps 450006 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.554795 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.554795 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.802468 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.802468 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 822274 # number of integer regfile reads +system.cpu0.int_regfile_writes 370684 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 268638 # number of misc regfile reads +system.cpu0.misc_regfile_reads 268168 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.669467 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 177790 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.144997 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 177494 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 1033.662791 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1031.941860 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.669467 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278651 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.278651 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.144997 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277627 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277627 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 716504 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 716504 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 90267 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90267 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 87606 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 87606 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 177873 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 177873 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 177873 # number of overall hits -system.cpu0.dcache.overall_hits::total 177873 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 580 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 580 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 551 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 551 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1131 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1131 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1131 # number of overall misses -system.cpu0.dcache.overall_misses::total 1131 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15004000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15004000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35761990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35761990 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 487500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 487500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 50765990 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 50765990 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 50765990 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 50765990 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90847 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90847 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 88157 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 88157 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 715284 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 715284 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 90136 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90136 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 87436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 87436 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 24 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 24 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 177572 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 177572 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 177572 # number of overall hits +system.cpu0.dcache.overall_hits::total 177572 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 571 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 571 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 18 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 18 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1126 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1126 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1126 # number of overall misses +system.cpu0.dcache.overall_misses::total 1126 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16338000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16338000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35699989 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35699989 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 501500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 501500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 52037989 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 52037989 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 52037989 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 52037989 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 87991 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 87991 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 179004 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 179004 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 179004 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 179004 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006384 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006384 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006250 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006250 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006318 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006318 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006318 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006318 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25868.965517 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25868.965517 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64903.793103 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64903.793103 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 24375 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 24375 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 44885.932803 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 44885.932803 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 178698 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 178698 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 178698 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 178698 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006295 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006295 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006307 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006307 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.428571 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.428571 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006301 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006301 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006301 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006301 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28612.959720 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28612.959720 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64324.304505 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64324.304505 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27861.111111 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 27861.111111 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46214.910302 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46214.910302 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 885 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 383 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 383 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 761 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 761 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 761 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 761 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 369 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 385 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 385 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 168 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 168 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 370 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 370 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 370 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 370 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6835500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8076500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8076500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 467500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 467500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14912000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14912000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14912000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14912000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001906 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001906 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002067 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002067 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002067 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002067 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33839.108911 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33839.108911 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48074.404762 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48074.404762 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 23375 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 23375 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40302.702703 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40302.702703 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40302.702703 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40302.702703 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 413 # number of replacements -system.cpu0.icache.tags.tagsinuse 250.106503 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7058 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 712 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.912921 # Average number of references to valid blocks. +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 18 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 18 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 372 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 372 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7501000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7501000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8169500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8169500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 483500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 483500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15670500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15670500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15670500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15670500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002227 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002227 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001932 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001932 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.428571 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002082 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002082 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002082 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002082 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37133.663366 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37133.663366 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48055.882353 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48055.882353 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26861.111111 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26861.111111 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 393 # number of replacements +system.cpu0.icache.tags.tagsinuse 248.700617 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7078 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.184173 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 250.106503 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488489 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.488489 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.583984 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8709 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8709 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7058 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7058 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7058 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7058 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7058 # number of overall hits -system.cpu0.icache.overall_hits::total 7058 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 939 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 939 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 939 # number of overall misses -system.cpu0.icache.overall_misses::total 939 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 44243500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 44243500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 44243500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 44243500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 44243500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 44243500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7997 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7997 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7997 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7997 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7997 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7997 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117419 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117419 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117419 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117419 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117419 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117419 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47117.678381 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47117.678381 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47117.678381 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47117.678381 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.700617 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.485743 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.485743 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.589844 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8690 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8690 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7078 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7078 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7078 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7078 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7078 # number of overall hits +system.cpu0.icache.overall_hits::total 7078 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 917 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 917 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 917 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 917 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 917 # number of overall misses +system.cpu0.icache.overall_misses::total 917 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47775500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 47775500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 47775500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 47775500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 47775500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 47775500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7995 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7995 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7995 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7995 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114697 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114697 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114697 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114697 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114697 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114697 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52099.781897 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 52099.781897 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 52099.781897 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 52099.781897 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 151 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 413 # number of writebacks -system.cpu0.icache.writebacks::total 413 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 226 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 226 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 226 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 226 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 713 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 713 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 713 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 713 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34164500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 34164500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34164500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 34164500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34164500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 34164500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089158 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.089158 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.089158 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47916.549790 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency -system.cpu1.branchPred.lookups 73042 # Number of BP lookups -system.cpu1.branchPred.condPredicted 65659 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 2238 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 64943 # Number of BTB lookups +system.cpu0.icache.writebacks::writebacks 393 # number of writebacks +system.cpu0.icache.writebacks::total 393 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36615000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 36615000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36615000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 36615000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36615000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 36615000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087054 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.087054 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.087054 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52607.758621 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency +system.cpu1.branchPred.lookups 69942 # Number of BP lookups +system.cpu1.branchPred.condPredicted 62611 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2168 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 62876 # Number of BTB lookups system.cpu1.branchPred.BTBHits 0 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.usedRAS 1880 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 64943 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 55241 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 9702 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 1128 # Number of mispredicted indirect branches. -system.cpu1.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 192502 # number of cpu cycles simulated +system.cpu1.branchPred.indirectLookups 62876 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 52518 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 10358 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 1122 # Number of mispredicted indirect branches. +system.cpu1.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 191834 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 33710 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 406560 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 73042 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 57230 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 148689 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4633 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.icacheStallCycles 35275 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 386727 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 69942 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 54398 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 146033 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4493 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1669 # Number of stall cycles due to pending traps -system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 22180 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 918 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 186413 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 2.180964 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.381342 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1374 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 23469 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 905 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 184982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 2.090620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.368236 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 54977 29.49% 29.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 63721 34.18% 63.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5493 2.95% 66.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3499 1.88% 68.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 651 0.35% 68.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 47493 25.48% 94.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 995 0.53% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1355 0.73% 95.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 8229 4.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 58784 31.78% 31.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 61509 33.25% 65.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6216 3.36% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3423 1.85% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 694 0.38% 70.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43897 23.73% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1064 0.58% 94.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1288 0.70% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 8107 4.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 186413 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.379435 # Number of branch fetches per cycle -system.cpu1.fetch.rate 2.111978 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 22012 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48189 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 110683 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3203 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2316 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 375249 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2316 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23003 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 21046 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13565 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110960 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15513 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 369118 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 12808 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 184982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.364596 # Number of branch fetches per cycle +system.cpu1.fetch.rate 2.015946 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21795 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 53545 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 103882 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3504 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2246 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 357234 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2246 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22757 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 24349 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13357 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 104467 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 17796 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 350958 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15108 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 260404 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 717496 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 555302 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 234261 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 26143 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1622 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1759 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 20875 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 105786 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 51568 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 49714 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 45358 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 305985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5880 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 304555 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 23105 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 18122 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 1124 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 186413 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.633765 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.368784 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 246923 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 678000 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 525614 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 22 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 220975 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 25948 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1579 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1706 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 23252 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 99419 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 48107 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 46982 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41894 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 289725 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 288968 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 22905 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 18076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1082 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 184982 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.562141 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.375121 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 59464 31.90% 31.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19554 10.49% 42.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 50315 26.99% 69.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 50093 26.87% 96.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3572 1.92% 98.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1698 0.91% 99.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1008 0.54% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 406 0.22% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 303 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 62949 34.03% 34.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21563 11.66% 45.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46877 25.34% 71.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 46716 25.25% 96.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3504 1.89% 98.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1701 0.92% 99.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 999 0.54% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 396 0.21% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 277 0.15% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 186413 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 184982 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 182 38.89% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 58 12.39% 51.28% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 228 48.72% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 191 40.04% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 60 12.58% 52.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 226 47.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 145063 47.63% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 108861 35.74% 83.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 50631 16.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 138690 47.99% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 103154 35.70% 83.69% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 47124 16.31% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 304555 # Type of FU issued -system.cpu1.iq.rate 1.582087 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 468 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001537 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 796075 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 334945 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 300973 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 288968 # Type of FU issued +system.cpu1.iq.rate 1.506344 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 477 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 763491 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 319139 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 285378 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_writes 44 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 305023 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 289445 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 45252 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41785 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4194 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 25 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 2536 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4131 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2566 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2316 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6366 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 362764 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 105786 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 51568 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1528 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2246 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7047 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 344310 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 276 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 99419 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 48107 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1464 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2397 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 2840 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 302276 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 104291 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2279 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2268 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2730 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 286645 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 97925 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2323 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 50899 # number of nop insts executed -system.cpu1.iew.exec_refs 154635 # number of memory reference insts executed -system.cpu1.iew.exec_branches 61121 # Number of branches executed -system.cpu1.iew.exec_stores 50344 # Number of stores executed -system.cpu1.iew.exec_rate 1.570249 # Inst execution rate -system.cpu1.iew.wb_sent 301460 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 300973 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 172395 # num instructions producing a value -system.cpu1.iew.wb_consumers 179828 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.563480 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.958666 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 24140 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4756 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 2238 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 181815 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.862272 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.110451 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 48075 # number of nop insts executed +system.cpu1.iew.exec_refs 144750 # number of memory reference insts executed +system.cpu1.iew.exec_branches 58305 # Number of branches executed +system.cpu1.iew.exec_stores 46825 # Number of stores executed +system.cpu1.iew.exec_rate 1.494235 # Inst execution rate +system.cpu1.iew.wb_sent 285841 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 285378 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 162569 # num instructions producing a value +system.cpu1.iew.wb_consumers 170014 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.487630 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.956209 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 23932 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5428 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2168 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 180468 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.775063 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.087699 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 63682 35.03% 35.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 57506 31.63% 66.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5445 2.99% 69.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5412 2.98% 72.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1312 0.72% 73.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 45472 25.01% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 770 0.42% 98.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 999 0.55% 99.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1217 0.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 67886 37.62% 37.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 54714 30.32% 67.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5489 3.04% 70.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6162 3.41% 74.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1291 0.72% 75.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41971 23.26% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 718 0.40% 98.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1059 0.59% 99.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1178 0.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 181815 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 338589 # Number of instructions committed -system.cpu1.commit.committedOps 338589 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 180468 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 320342 # Number of instructions committed +system.cpu1.commit.committedOps 320342 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 150624 # Number of memory references committed -system.cpu1.commit.loads 101592 # Number of loads committed -system.cpu1.commit.membars 4041 # Number of memory barriers committed -system.cpu1.commit.branches 59040 # Number of branches committed +system.cpu1.commit.refs 140829 # Number of memory references committed +system.cpu1.commit.loads 95288 # Number of loads committed +system.cpu1.commit.membars 4715 # Number of memory barriers committed +system.cpu1.commit.branches 56221 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 231783 # Number of committed integer instructions. +system.cpu1.commit.int_insts 219172 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 49829 14.72% 14.72% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 134095 39.60% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 105633 31.20% 85.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 49032 14.48% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 47012 14.68% 14.68% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 127786 39.89% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 100003 31.22% 85.78% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 45541 14.22% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 338589 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1217 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 542741 # The number of ROB reads -system.cpu1.rob.rob_writes 730091 # The number of ROB writes -system.cpu1.timesIdled 236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 284719 # Number of Instructions Simulated -system.cpu1.committedOps 284719 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.676112 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.676112 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.479044 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.479044 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 527704 # number of integer regfile reads -system.cpu1.int_regfile_writes 245054 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 320342 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1178 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 522978 # The number of ROB reads +system.cpu1.rob.rob_writes 693117 # The number of ROB writes +system.cpu1.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6852 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 49387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 268615 # Number of Instructions Simulated +system.cpu1.committedOps 268615 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.714160 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.714160 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.400247 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.400247 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 497951 # number of integer regfile reads +system.cpu1.int_regfile_writes 231611 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 156484 # number of misc regfile reads +system.cpu1.misc_regfile_reads 146596 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.869792 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 56025 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1931.896552 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.433606 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 52423 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1747.433333 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.869792 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.052480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 432447 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 432447 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 58508 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 58508 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 48814 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 48814 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 107322 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 107322 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 107322 # number of overall hits -system.cpu1.dcache.overall_hits::total 107322 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 149 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 149 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 656 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 656 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 656 # number of overall misses -system.cpu1.dcache.overall_misses::total 656 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4815500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4815500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3532500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3532500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 364000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 364000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8348000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8348000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8348000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8348000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 59015 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 59015 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 48963 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 48963 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 107978 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 107978 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 107978 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 107978 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008591 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008591 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003043 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.840580 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.840580 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006075 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006075 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006075 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006075 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 9498.027613 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 9498.027613 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23708.053691 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23708.053691 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6275.862069 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 6275.862069 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 12725.609756 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12725.609756 # average overall miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.433606 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051628 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051628 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 406876 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 406876 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 55612 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 55612 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 45312 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 45312 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 100924 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 100924 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 100924 # number of overall hits +system.cpu1.dcache.overall_hits::total 100924 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 502 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 502 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 162 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 162 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses +system.cpu1.dcache.overall_misses::total 664 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5584500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5584500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3659500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3659500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 374500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 374500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9244000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9244000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9244000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9244000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 56114 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 56114 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 45474 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 45474 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 101588 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 101588 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 101588 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 101588 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008946 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008946 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003562 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003562 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.820896 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006536 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006536 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006536 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006536 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11124.501992 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11124.501992 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22589.506173 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22589.506173 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6809.090909 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 6809.090909 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13921.686747 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13921.686747 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 344 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 387 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 387 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 387 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 340 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 340 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 55 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 55 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 395 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 395 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 395 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 395 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1494500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1494500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1455500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1455500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 306000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 306000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2950000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2950000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002762 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002762 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002165 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002165 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.840580 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.840580 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002491 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002491 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9168.711656 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9168.711656 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13731.132075 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13731.132075 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 5275.862069 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 5275.862069 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2129000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2129000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1532000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1532000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 319500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 319500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3661000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3661000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3661000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3661000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002887 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.820896 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002648 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002648 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002648 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002648 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13141.975309 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13141.975309 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14317.757009 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14317.757009 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 5809.090909 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 5809.090909 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13609.665428 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13609.665428 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13609.665428 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13609.665428 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 556 # number of replacements -system.cpu1.icache.tags.tagsinuse 97.374754 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21335 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 687 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.055313 # Average number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 97.753950 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22636 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 690 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.805797 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.374754 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190185 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.190185 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 131 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.255859 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22867 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22867 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 21335 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21335 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21335 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21335 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21335 # number of overall hits -system.cpu1.icache.overall_hits::total 21335 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 845 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 845 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 845 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 845 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 845 # number of overall misses -system.cpu1.icache.overall_misses::total 845 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 18952000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 18952000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 18952000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 18952000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 18952000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 18952000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22180 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22180 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22180 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22180 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22180 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22180 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038097 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038097 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038097 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038097 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038097 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038097 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22428.402367 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22428.402367 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22428.402367 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22428.402367 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked +system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.753950 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190926 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.190926 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 24159 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 24159 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 22636 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22636 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22636 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22636 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22636 # number of overall hits +system.cpu1.icache.overall_hits::total 22636 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 833 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 833 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 833 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 833 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 833 # number of overall misses +system.cpu1.icache.overall_misses::total 833 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 20006500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 20006500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 20006500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 20006500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 20006500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 20006500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23469 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23469 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23469 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23469 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23469 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23469 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.035494 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.035494 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.035494 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.035494 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.035494 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.035494 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24017.406963 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24017.406963 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24017.406963 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24017.406963 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.writebacks::writebacks 556 # number of writebacks system.cpu1.icache.writebacks::total 556 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 158 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 158 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 158 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 158 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 158 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 687 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 687 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 687 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 687 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 14723000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 14723000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 14723000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 14723000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 14723000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 14723000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030974 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030974 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21430.858806 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency -system.cpu2.branchPred.lookups 66096 # Number of BP lookups -system.cpu2.branchPred.condPredicted 57926 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2486 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 57464 # Number of BTB lookups +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 143 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 143 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 143 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 143 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 690 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 690 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 690 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 690 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 690 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 690 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15540500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 15540500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15540500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 15540500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15540500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 15540500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029400 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.029400 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.029400 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22522.463768 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency +system.cpu2.branchPred.lookups 60250 # Number of BP lookups +system.cpu2.branchPred.condPredicted 52369 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2399 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 52178 # Number of BTB lookups system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 2115 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.usedRAS 1981 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 57464 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 46751 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 10713 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches. -system.cpu2.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 192112 # number of cpu cycles simulated +system.cpu2.branchPred.indirectLookups 52178 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 41452 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10726 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1295 # Number of mispredicted indirect branches. +system.cpu2.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 191431 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 39817 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 356778 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 66096 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 48866 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 146191 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 5129 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 42696 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 319764 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 60250 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43433 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 142400 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4955 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 28579 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 972 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 190509 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.872762 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.344982 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 31580 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 988 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 189804 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.684706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.290533 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 72004 37.80% 37.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 58377 30.64% 68.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8422 4.42% 72.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3406 1.79% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 670 0.35% 75.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36267 19.04% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1053 0.55% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 1474 0.77% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 8836 4.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 80855 42.60% 42.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 54436 28.68% 71.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 9994 5.27% 76.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3383 1.78% 78.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 680 0.36% 78.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 29156 15.36% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1157 0.61% 94.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1395 0.73% 95.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8748 4.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 190509 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.344049 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.857135 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 22990 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 70899 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 89451 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4595 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2564 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 324452 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2564 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 24019 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 34614 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13407 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 89996 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 25899 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 317685 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 22128 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 189804 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.314735 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.670388 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 22561 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 83775 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 75624 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5357 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2477 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 288545 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2477 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 23562 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 41928 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13956 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 76490 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 31381 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 281938 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 27181 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 221990 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 601950 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 469192 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 40 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 192480 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 29510 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1686 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1819 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 31415 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 86703 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 40578 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 41384 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34173 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 258235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8782 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 258833 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 25653 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 20039 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 1265 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 190509 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.358639 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.384430 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 195781 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 524561 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 411315 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 32 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 166026 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 29755 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1653 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1783 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 36818 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 74139 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33614 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 35848 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 27180 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 226553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10243 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 228568 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 140 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 25915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 20426 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1250 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 189804 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.204232 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.376602 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 76931 40.38% 40.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 28046 14.72% 55.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39341 20.65% 75.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 39028 20.49% 96.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3604 1.89% 98.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1759 0.92% 99.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1073 0.56% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 444 0.23% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 85980 45.30% 45.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 32313 17.02% 62.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 32235 16.98% 79.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 31990 16.85% 96.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3688 1.94% 98.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1698 0.89% 99.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1058 0.56% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 511 0.27% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 331 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 190509 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 189804 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 204 42.15% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 51 10.54% 52.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 229 47.31% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 232 44.96% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 58 11.24% 56.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 226 43.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 126867 49.02% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 92395 35.70% 84.71% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 39571 15.29% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114651 50.16% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 81333 35.58% 85.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 32584 14.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 258833 # Type of FU issued -system.cpu2.iq.rate 1.347303 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 484 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001870 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 708742 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 292626 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 254835 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 228568 # Type of FU issued +system.cpu2.iq.rate 1.193997 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 516 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.002258 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 647596 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 262684 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 224391 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 80 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 259317 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 229084 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34129 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 27120 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 4624 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 2677 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 4546 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 31 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2695 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2564 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9290 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 309688 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 288 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 86703 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 40578 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1561 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2477 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10821 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 273857 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 74139 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33614 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1537 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 2684 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3127 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 256258 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 85016 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 2575 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2611 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3072 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 225860 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 72453 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2708 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 42671 # number of nop insts executed -system.cpu2.iew.exec_refs 124288 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53042 # Number of branches executed -system.cpu2.iew.exec_stores 39272 # Number of stores executed -system.cpu2.iew.exec_rate 1.333899 # Inst execution rate -system.cpu2.iew.wb_sent 255341 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 254835 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 142252 # num instructions producing a value -system.cpu2.iew.wb_consumers 149928 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.326492 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.948802 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 26847 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7517 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 2486 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 185379 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.525604 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.006612 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 37061 # number of nop insts executed +system.cpu2.iew.exec_refs 104703 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47570 # Number of branches executed +system.cpu2.iew.exec_stores 32250 # Number of stores executed +system.cpu2.iew.exec_rate 1.179851 # Inst execution rate +system.cpu2.iew.wb_sent 224905 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 224391 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 122751 # num instructions producing a value +system.cpu2.iew.wb_consumers 130504 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.172177 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.940592 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 27003 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 8993 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2399 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 184731 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.336127 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.921991 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83888 45.25% 45.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 49216 26.55% 71.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5545 2.99% 74.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8151 4.40% 79.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1274 0.69% 79.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34338 18.52% 98.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 700 0.38% 98.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1066 0.58% 99.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1201 0.65% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 94349 51.07% 51.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43685 23.65% 74.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5440 2.94% 77.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 9609 5.20% 82.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1281 0.69% 83.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 27371 14.82% 98.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 737 0.40% 98.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1041 0.56% 99.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1218 0.66% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 185379 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 282815 # Number of instructions committed -system.cpu2.commit.committedOps 282815 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 184731 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 246824 # Number of instructions committed +system.cpu2.commit.committedOps 246824 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 119980 # Number of memory references committed -system.cpu2.commit.loads 82079 # Number of loads committed -system.cpu2.commit.membars 6800 # Number of memory barriers committed -system.cpu2.commit.branches 50664 # Number of branches committed +system.cpu2.commit.refs 100512 # Number of memory references committed +system.cpu2.commit.loads 69593 # Number of loads committed +system.cpu2.commit.membars 8278 # Number of memory barriers committed +system.cpu2.commit.branches 45154 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 192763 # Number of committed integer instructions. +system.cpu2.commit.int_insts 167790 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 41451 14.66% 14.66% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 114584 40.52% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 88879 31.43% 86.60% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 37901 13.40% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 35943 14.56% 14.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 102091 41.36% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 77871 31.55% 87.47% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 30919 12.53% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 282815 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1201 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 493254 # The number of ROB reads -system.cpu2.rob.rob_writes 624500 # The number of ROB writes -system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 234564 # Number of Instructions Simulated -system.cpu2.committedOps 234564 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.819017 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.819017 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.220975 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.220975 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 437605 # number of integer regfile reads -system.cpu2.int_regfile_writes 204427 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 246824 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1218 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 456754 # The number of ROB reads +system.cpu2.rob.rob_writes 552779 # The number of ROB writes +system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 49789 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 202603 # Number of Instructions Simulated +system.cpu2.committedOps 202603 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.944858 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.944858 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.058360 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.058360 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 379324 # number of integer regfile reads +system.cpu2.int_regfile_writes 178066 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 126238 # number of misc regfile reads +system.cpu2.misc_regfile_reads 106600 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.114184 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 45075 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1502.500000 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 24.613342 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38229 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1233.193548 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.114184 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051004 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051004 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.613342 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.048073 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.048073 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 355312 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 355312 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 50364 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50364 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 37691 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 37691 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 88055 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 88055 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 88055 # number of overall hits -system.cpu2.dcache.overall_hits::total 88055 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 498 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 637 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 637 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 637 # number of overall misses -system.cpu2.dcache.overall_misses::total 637 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3990000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3990000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2835500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2835500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 366500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 366500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6825500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6825500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6825500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6825500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 50862 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 50862 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 37830 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 37830 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 88692 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 88692 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 88692 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 88692 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009791 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009791 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003674 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003674 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007182 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007182 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007182 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007182 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8012.048193 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 8012.048193 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20399.280576 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20399.280576 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6318.965517 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 6318.965517 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 10715.070644 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 10715.070644 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 305153 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 305153 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.ReadReq_hits::cpu2.data 44839 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 44839 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 30714 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 30714 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 75553 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 75553 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 75553 # number of overall hits +system.cpu2.dcache.overall_hits::total 75553 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 467 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 136 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 136 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 603 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 603 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 603 # number of overall misses +system.cpu2.dcache.overall_misses::total 603 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3772500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3772500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3722500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3722500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 339500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 339500 # 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average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 331 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 301 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 34 # 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number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2581000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003283 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003283 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002776 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002776 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003067 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003067 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7143.712575 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7143.712575 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13219.047619 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13219.047619 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5318.965517 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5318.965517 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 578 # number of replacements -system.cpu2.icache.tags.tagsinuse 95.404705 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 27742 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 710 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 39.073239 # Average number of references to valid blocks. +system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 1 # number of SwapReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 335 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 335 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1217000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1217000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1941500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1941500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 286500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 286500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3158500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3158500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3158500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3158500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003664 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003664 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003306 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003306 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.753623 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003519 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003519 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003519 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003519 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7331.325301 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7331.325301 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19034.313725 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19034.313725 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5509.615385 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5509.615385 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.tags.replacements 564 # number of replacements +system.cpu2.icache.tags.tagsinuse 92.356205 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 30734 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 702 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 43.780627 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 95.404705 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.186337 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.186337 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 132 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 92.356205 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.180383 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.180383 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.257812 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 29289 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 29289 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 27742 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 27742 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 27742 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 27742 # 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number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 12852000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 28579 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 28579 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 28579 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 28579 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 28579 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 28579 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029287 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.029287 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029287 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.029287 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029287 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.029287 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15354.838710 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15354.838710 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15354.838710 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15354.838710 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15354.838710 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15354.838710 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu2.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 32282 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 32282 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.ReadReq_hits::cpu2.inst 30734 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 30734 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 30734 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 30734 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 30734 # number of overall hits +system.cpu2.icache.overall_hits::total 30734 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 846 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 846 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 846 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 846 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 846 # number of overall misses +system.cpu2.icache.overall_misses::total 846 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12713000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 12713000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 12713000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 12713000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 12713000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 12713000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 31580 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 31580 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 31580 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 31580 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 31580 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 31580 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.026789 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.026789 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.026789 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.026789 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.026789 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.026789 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15027.186761 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15027.186761 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15027.186761 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15027.186761 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15027.186761 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15027.186761 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 578 # number of writebacks -system.cpu2.icache.writebacks::total 578 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 127 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 127 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 127 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 127 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 127 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 127 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 710 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 710 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 710 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 710 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 710 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 710 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10853000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10853000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10853000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10853000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10853000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10853000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024843 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.024843 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.024843 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15285.915493 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency -system.cpu3.branchPred.lookups 58058 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50256 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 2406 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50211 # Number of BTB lookups +system.cpu2.icache.writebacks::writebacks 564 # number of writebacks +system.cpu2.icache.writebacks::total 564 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 144 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 144 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 144 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 144 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 702 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 702 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 702 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 702 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 702 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 702 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10591000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10591000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10591000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10591000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10591000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10591000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.022229 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.022229 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.022229 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15086.894587 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency +system.cpu3.branchPred.lookups 65607 # Number of BP lookups +system.cpu3.branchPred.condPredicted 57989 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2329 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 57945 # Number of BTB lookups system.cpu3.branchPred.BTBHits 0 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 1984 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.usedRAS 1972 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 50211 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 39339 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 10872 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 1290 # Number of mispredicted indirect branches. -system.cpu3.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 191755 # number of cpu cycles simulated +system.cpu3.branchPred.indirectLookups 57945 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 47394 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 10551 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1239 # Number of mispredicted indirect branches. +system.cpu3.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 191064 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 44345 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 305380 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 58058 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 41323 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 141573 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4965 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 38959 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 355945 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 65607 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 49366 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 146283 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4811 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1720 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 32940 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 190133 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.606139 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.261267 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1648 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 27872 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 954 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 189308 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.880243 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.334212 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 84706 44.55% 44.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53051 27.90% 72.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10689 5.62% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3433 1.81% 79.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 679 0.36% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 26352 13.86% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1085 0.57% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 1438 0.76% 95.42% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 8700 4.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 70601 37.29% 37.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 58551 30.93% 68.22% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8289 4.38% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3543 1.87% 74.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 620 0.33% 74.80% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 36795 19.44% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1123 0.59% 94.83% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1294 0.68% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8492 4.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 190133 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.302772 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.592553 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 22846 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 89002 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 70141 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5652 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2482 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 273868 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2482 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 23847 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 45287 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13384 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 70737 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 34386 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 267452 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 29592 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full -system.cpu3.rename.RenamedOperands 184677 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 492576 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 387264 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 20 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 155405 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 29272 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1682 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1811 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 39856 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69050 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 30771 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33750 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24332 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 213083 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 11008 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 216315 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 25213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 19048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 1289 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 190133 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.137704 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.357547 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 189308 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.343377 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.862962 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 22011 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 70196 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 90137 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4549 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2405 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 325577 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2405 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 23040 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 34162 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13425 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 90919 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 25347 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 318974 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 21885 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 222576 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 605183 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 471258 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 38 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 194403 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 28173 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1623 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1757 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 30798 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 87479 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 41118 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 41854 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 34728 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 259350 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8662 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 260097 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 24362 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 19655 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 189308 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.373936 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.388628 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 89784 47.22% 47.22% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 34463 18.13% 65.35% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29348 15.44% 80.78% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 29336 15.43% 96.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3681 1.94% 98.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1744 0.92% 99.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 1040 0.55% 99.61% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 432 0.23% 99.84% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 75622 39.95% 39.95% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 27531 14.54% 54.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 39579 20.91% 75.40% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 39359 20.79% 96.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3671 1.94% 98.13% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1727 0.91% 99.04% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1045 0.55% 99.59% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 450 0.24% 99.83% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 324 0.17% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 190133 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 189308 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 189 39.38% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 53 11.04% 50.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 238 49.58% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 198 41.42% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 48 10.04% 51.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 232 48.54% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 109511 50.63% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 77010 35.60% 86.23% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 29794 13.77% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 126919 48.80% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 93130 35.81% 84.60% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 40048 15.40% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 216315 # Type of FU issued -system.cpu3.iq.rate 1.128080 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 480 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.002219 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 623296 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 249298 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 212257 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 260097 # Type of FU issued +system.cpu3.iq.rate 1.361308 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 478 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001838 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 710080 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 292336 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 256163 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 40 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 216795 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 260575 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24283 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34620 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 4403 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 27 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 2689 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 4474 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2718 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2482 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 11408 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 259073 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 473 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69050 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 30771 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1541 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 26 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2405 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 9114 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 311067 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 87479 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 41118 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1508 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 490 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 2580 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 3070 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 213662 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 67471 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 2653 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 450 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2479 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2929 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 257518 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 85797 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2579 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34982 # number of nop insts executed -system.cpu3.iew.exec_refs 96956 # number of memory reference insts executed -system.cpu3.iew.exec_branches 45328 # Number of branches executed -system.cpu3.iew.exec_stores 29485 # Number of stores executed -system.cpu3.iew.exec_rate 1.114245 # Inst execution rate -system.cpu3.iew.wb_sent 212766 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 212257 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 115033 # num instructions producing a value -system.cpu3.iew.wb_consumers 122695 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.106918 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.937552 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 26335 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 9719 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2406 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 185183 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.256660 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.878907 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 43055 # number of nop insts executed +system.cpu3.iew.exec_refs 125534 # number of memory reference insts executed +system.cpu3.iew.exec_branches 53219 # Number of branches executed +system.cpu3.iew.exec_stores 39737 # Number of stores executed +system.cpu3.iew.exec_rate 1.347810 # Inst execution rate +system.cpu3.iew.wb_sent 256666 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 256163 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 143359 # num instructions producing a value +system.cpu3.iew.wb_consumers 150866 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.340718 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.950241 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 25509 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7449 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2329 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 184454 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.547985 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.017686 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 99076 53.50% 53.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 41559 22.44% 75.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5388 2.91% 78.85% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 10319 5.57% 84.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1252 0.68% 85.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24567 13.27% 98.37% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 787 0.42% 98.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1025 0.55% 99.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1210 0.65% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 82386 44.66% 44.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 49463 26.82% 71.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5369 2.91% 74.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8071 4.38% 78.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1252 0.68% 79.45% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 34869 18.90% 98.35% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 786 0.43% 98.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1015 0.55% 99.33% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1243 0.67% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 185183 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 232712 # Number of instructions committed -system.cpu3.commit.committedOps 232712 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 184454 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 285532 # Number of instructions committed +system.cpu3.commit.committedOps 285532 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 92729 # Number of memory references committed -system.cpu3.commit.loads 64647 # Number of loads committed -system.cpu3.commit.membars 9005 # Number of memory barriers committed -system.cpu3.commit.branches 43044 # Number of branches committed +system.cpu3.commit.refs 121405 # Number of memory references committed +system.cpu3.commit.loads 83005 # Number of loads committed +system.cpu3.commit.membars 6731 # Number of memory barriers committed +system.cpu3.commit.branches 51096 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 157897 # Number of committed integer instructions. +system.cpu3.commit.int_insts 194617 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33834 14.54% 14.54% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 97144 41.74% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 73652 31.65% 87.93% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 28082 12.07% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 41882 14.67% 14.67% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 115514 40.46% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 89736 31.43% 86.55% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 38400 13.45% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 232712 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1210 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 442434 # The number of ROB reads -system.cpu3.rob.rob_writes 523106 # The number of ROB writes -system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1622 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 189873 # Number of Instructions Simulated -system.cpu3.committedOps 189873 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.009912 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.009912 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.990185 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.990185 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 355771 # number of integer regfile reads -system.cpu3.int_regfile_writes 167240 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 285532 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1243 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 493666 # The number of ROB reads +system.cpu3.rob.rob_writes 626988 # The number of ROB writes +system.cpu3.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1756 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 50157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 236919 # Number of Instructions Simulated +system.cpu3.committedOps 236919 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.806453 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.806453 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.239998 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.239998 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 440410 # number of integer regfile reads +system.cpu3.int_regfile_writes 205469 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 98845 # number of misc regfile reads +system.cpu3.misc_regfile_reads 127408 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.519752 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 35385 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1179.500000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.184575 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 45468 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1567.862069 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.519752 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047890 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047890 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.184575 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.049189 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.049189 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 285185 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 285185 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 42713 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 42713 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 27877 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 27877 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 16 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 70590 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 70590 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 70590 # number of overall hits -system.cpu3.dcache.overall_hits::total 70590 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 439 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 439 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 576 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 576 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 576 # number of overall misses -system.cpu3.dcache.overall_misses::total 576 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3185500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3185500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2743000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2743000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 334000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 334000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5928500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5928500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5928500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5928500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 43152 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 43152 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 28014 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 28014 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 71166 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 71166 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 71166 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 71166 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010173 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010173 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004890 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004890 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.764706 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008094 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008094 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008094 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008094 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7256.264237 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 7256.264237 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20021.897810 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20021.897810 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6423.076923 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 6423.076923 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 10292.534722 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 10292.534722 # average overall miss latency +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 358446 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 358446 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.ReadReq_hits::cpu3.data 50650 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 50650 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 38188 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 38188 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 88838 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 88838 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 88838 # number of overall hits +system.cpu3.dcache.overall_hits::total 88838 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 496 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 496 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 140 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 140 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 636 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 636 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 636 # number of overall misses +system.cpu3.dcache.overall_misses::total 636 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3601500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 3601500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2913500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2913500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 356500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 356500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 6515000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 6515000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 6515000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 6515000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 51146 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 51146 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 38328 # 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miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.833333 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007108 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007108 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007108 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007108 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7261.088710 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 7261.088710 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20810.714286 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20810.714286 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5941.666667 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 5941.666667 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 10243.710692 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 10243.710692 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 281 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 281 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 326 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 326 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 314 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 314 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 314 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 314 # 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number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1390500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1390500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 282000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 282000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2474500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2474500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2474500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2474500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003661 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003661 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003712 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.750000 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003682 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003682 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003682 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003682 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6860.759494 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6860.759494 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13370.192308 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13370.192308 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5529.411765 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5529.411765 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 578 # number of replacements -system.cpu3.icache.tags.tagsinuse 92.680953 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 32101 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 713 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 45.022440 # Average number of references to valid blocks. +system.cpu3.dcache.demand_mshr_hits::cpu3.data 361 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 361 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 170 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 275 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 275 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1125000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1125000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1450500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 296500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 296500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2575500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2575500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2575500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2575500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003324 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003324 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002740 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.819444 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.819444 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003074 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003074 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6617.647059 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6617.647059 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13814.285714 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13814.285714 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5025.423729 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5025.423729 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9365.454545 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9365.454545 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9365.454545 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9365.454545 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.tags.replacements 586 # number of replacements +system.cpu3.icache.tags.tagsinuse 96.347148 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 27016 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 724 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 37.314917 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 92.680953 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.181017 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.181017 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 33653 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 33653 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 32101 # 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number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 11633500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 11633500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 11633500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 11633500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 32940 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 32940 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 32940 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 32940 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 32940 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 32940 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.025471 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.025471 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.025471 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.025471 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.025471 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.025471 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13865.911800 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13865.911800 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13865.911800 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13865.911800 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.tags.occ_blocks::cpu3.inst 96.347148 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.188178 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.188178 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 28596 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 28596 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.ReadReq_hits::cpu3.inst 27016 # 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number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 12888000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 12888000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 12888000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 12888000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 27872 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 27872 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 27872 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 27872 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 27872 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 27872 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.030712 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69857.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69369.718310 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67790.450928 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72035.294118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65696.629213 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70857.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 94071.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76450 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69857.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69369.718310 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 957 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 248 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74702.127660 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 73958.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78145.038168 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75697.580645 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78513.157895 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133611.111111 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84311.111111 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76405.882353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98386.363636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 108300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 74785.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 77225.941423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76405.882353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98386.363636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 108300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 74785.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 77225.941423 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 969 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 578 # Transaction distribution -system.membus.trans_dist::UpgradeReq 196 # Transaction distribution -system.membus.trans_dist::ReadExReq 183 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 585 # Transaction distribution +system.membus.trans_dist::UpgradeReq 194 # Transaction distribution +system.membus.trans_dist::ReadExReq 190 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 578 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1666 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45376 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 248 # Total snoops (count) +system.membus.trans_dist::ReadSharedReq 585 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1685 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1685 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 253 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957 # Request fanout histogram +system.membus.snoop_fanout::samples 969 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 969 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957 # Request fanout histogram -system.membus.reqLayer0.occupancy 877500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 969 # Request fanout histogram +system.membus.reqLayer0.occupancy 889500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3778750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 6322 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1727 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.respLayer1.occupancy 3809250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.1 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 6292 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1720 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3250 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 3509 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadResp 3503 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 8 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2125 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2099 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2823 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 690 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1838 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 378 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2004 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9484 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 72000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2812 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 700 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 599 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1936 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1968 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2034 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9446 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 81024 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 83840 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 332800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1032 # Total snoops (count) -system.toL2Bus.snoopTraffic 53504 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4195 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.291538 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.103863 # Request fanout histogram +system.toL2Bus.pkt_size::total 330496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1036 # Total snoops (count) +system.toL2Bus.snoopTraffic 53888 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4191 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.288475 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.109326 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1306 31.13% 31.13% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1176 28.03% 59.17% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 897 21.38% 80.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 816 19.45% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1322 31.54% 31.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1164 27.77% 59.32% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 879 20.97% 80.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 826 19.71% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2870,24 +2880,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4195 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5296980 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1068997 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 528987 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4191 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5261968 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1043496 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 528992 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1032995 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1037993 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 438456 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1069486 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 439965 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1070997 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 434459 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1056988 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 424982 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1087497 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 415480 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 445966 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |