diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 2902 |
1 files changed, 2902 insertions, 0 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index e69de29bb..3f4ff4c5a 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -0,0 +1,2902 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000125 # Number of seconds simulated +sim_ticks 124523000 # Number of ticks simulated +final_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 139641 # Simulator instruction rate (inst/s) +host_op_rate 139640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15068671 # Simulator tick rate (ticks/s) +host_mem_usage 262532 # Number of bytes of host memory used +host_seconds 8.26 # Real time elapsed on the host +sim_insts 1153943 # Number of instructions simulated +sim_ops 1153943 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory +system.physmem.bytes_read::total 45632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31488 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory +system.physmem.num_reads::total 713 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 192735479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 87373417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47284437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11307148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 7195458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7709419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 5653574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7195458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 366454390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192735479 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47284437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 7195458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 5653574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252868948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192735479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 87373417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47284437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11307148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 7195458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7709419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 5653574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7195458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 366454390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 713 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 713 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 45632 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 45632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 120 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 31 # Per bank write bursts +system.physmem.perBankRdBursts::3 62 # Per bank write bursts +system.physmem.perBankRdBursts::4 69 # Per bank write bursts +system.physmem.perBankRdBursts::5 28 # Per bank write bursts +system.physmem.perBankRdBursts::6 19 # Per bank write bursts +system.physmem.perBankRdBursts::7 28 # Per bank write bursts +system.physmem.perBankRdBursts::8 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 31 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 13 # Per bank write bursts +system.physmem.perBankRdBursts::12 70 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts +system.physmem.perBankRdBursts::14 19 # Per bank write bursts +system.physmem.perBankRdBursts::15 101 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 124288000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 713 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.637427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.941235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.016459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 63 36.84% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41 23.98% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 16.37% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 13 7.60% 84.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 4.68% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 4.68% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.75% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.58% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 171 # Bytes accessed per row activation +system.physmem.totQLat 6387250 # Total ticks spent queuing +system.physmem.totMemAccLat 19756000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8958.27 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27708.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 366.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 366.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.86 # Data bus utilization in percentage +system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 530 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 174316.97 # Average gap between requests +system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 816480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 445500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2917200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46677870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29286750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87772200 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.845263 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 50196500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3900000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 64717500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2215200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 50794695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25675500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 86979840 # Total energy per rank (pJ) +system.physmem_1.averagePower 743.076065 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 46915750 # Time in different power states +system.physmem_1.memoryStateTime::REF 3900000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 98739 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 96047 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 0 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 1131 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 96047 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 88694 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 7353 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.numCycles 249047 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.fetch.icacheStallCycles 23160 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 582455 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 98739 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89825 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 194593 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3423 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps +system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7952 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 853 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 221760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.626511 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.263155 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34377 15.50% 15.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 91683 41.34% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 679 0.31% 57.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1006 0.45% 57.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 517 0.23% 57.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 87238 39.34% 97.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 730 0.33% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 482 0.22% 97.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5048 2.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 221760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.396467 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.338735 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17619 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19820 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 181778 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1711 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 564879 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1711 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18296 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2376 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16107 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 181922 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1348 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 559910 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 383145 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1115796 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 842870 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 364171 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 18974 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1067 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1095 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5253 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 178633 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90222 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 87104 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 86835 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 467056 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1095 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 463006 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 16506 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13395 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 536 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 221760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.087870 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.110825 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 37234 16.79% 16.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4446 2.00% 18.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 88426 39.87% 58.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 88102 39.73% 98.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1676 0.76% 99.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 983 0.44% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 225 0.10% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 100 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 221760 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 134 40.48% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 76 22.96% 63.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 121 36.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 195503 42.22% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 178044 38.45% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 89459 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 463006 # Type of FU issued +system.cpu0.iq.rate 1.859111 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 331 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1148221 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 484707 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 460421 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 463337 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 86583 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 2958 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 52 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1878 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 1711 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2375 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 555874 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 178633 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90222 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 52 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1679 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1911 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 461536 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 177679 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1470 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 87723 # number of nop insts executed +system.cpu0.iew.exec_refs 266935 # number of memory reference insts executed +system.cpu0.iew.exec_branches 91696 # Number of branches executed +system.cpu0.iew.exec_stores 89256 # Number of stores executed +system.cpu0.iew.exec_rate 1.853208 # Inst execution rate +system.cpu0.iew.wb_sent 460886 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 460421 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 273043 # num instructions producing a value +system.cpu0.iew.wb_consumers 276596 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.848731 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987155 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 17182 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 1562 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 218398 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.466176 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.142349 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 37197 17.03% 17.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 90473 41.43% 58.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2051 0.94% 59.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 612 0.28% 59.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 499 0.23% 59.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 86381 39.55% 99.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 448 0.21% 99.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 288 0.13% 99.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 449 0.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 218398 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 538608 # Number of instructions committed +system.cpu0.commit.committedOps 538608 # Number of ops (including micro ops) committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 264019 # Number of memory references committed +system.cpu0.commit.loads 175675 # Number of loads committed +system.cpu0.commit.membars 84 # Number of memory barriers committed +system.cpu0.commit.branches 90231 # Number of branches committed +system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 362502 # Number of committed integer instructions. +system.cpu0.commit.function_calls 223 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 86963 16.15% 16.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 187542 34.82% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 175759 32.63% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 88344 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 538608 # Class of committed instruction +system.cpu0.commit.bw_lim_events 449 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 772578 # The number of ROB reads +system.cpu0.rob.rob_writes 1114998 # The number of ROB writes +system.cpu0.timesIdled 315 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27287 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 451561 # Number of Instructions Simulated +system.cpu0.committedOps 451561 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.551525 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.551525 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.813156 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.813156 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 825039 # number of integer regfile reads +system.cpu0.int_regfile_writes 371919 # number of integer regfile writes +system.cpu0.fp_regfile_reads 192 # number of floating regfile reads +system.cpu0.misc_regfile_reads 269052 # number of misc regfile reads +system.cpu0.misc_regfile_writes 564 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1035.337209 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.724931 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.278760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 87748 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 178161 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 178161 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 178161 # number of overall hits +system.cpu0.dcache.overall_hits::total 178161 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 578 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 578 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 554 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 554 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1132 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1132 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1132 # number of overall misses +system.cpu0.dcache.overall_misses::total 1132 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18168000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18168000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36152490 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36152490 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 521000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 521000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 54320490 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 54320490 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 54320490 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 54320490 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90991 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90991 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 88302 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 88302 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 179293 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 179293 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179293 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179293 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006352 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006352 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006274 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006274 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006314 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006314 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006314 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006314 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31432.525952 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31432.525952 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65257.202166 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65257.202166 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27421.052632 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 27421.052632 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47986.298587 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47986.298587 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 385 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 385 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 387 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 387 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 772 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 772 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 772 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 772 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 167 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 167 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7230000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7230000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8425000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8425000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 502000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 502000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15655000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15655000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15655000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15655000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002121 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002121 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001891 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001891 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002008 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002008 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37461.139896 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37461.139896 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50449.101796 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50449.101796 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26421.052632 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26421.052632 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency +system.cpu0.icache.tags.replacements 394 # number of replacements +system.cpu0.icache.tags.tagsinuse 248.905102 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7041 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.130935 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.905102 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.486143 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.486143 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8647 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7041 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7041 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7041 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7041 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7041 # number of overall hits +system.cpu0.icache.overall_hits::total 7041 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 911 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 911 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 911 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 911 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 911 # number of overall misses +system.cpu0.icache.overall_misses::total 911 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43691000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 43691000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 43691000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 43691000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 43691000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 43691000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7952 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7952 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7952 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7952 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7952 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7952 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114562 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114562 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114562 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114562 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114562 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114562 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47959.385291 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47959.385291 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47959.385291 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47959.385291 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 394 # number of writebacks +system.cpu0.icache.writebacks::total 394 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33693000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 33693000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33693000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 33693000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33693000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 33693000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087525 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.087525 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.087525 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48409.482759 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency +system.cpu1.branchPred.lookups 70381 # Number of BP lookups +system.cpu1.branchPred.condPredicted 62763 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2321 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 62113 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 0 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 1978 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 62113 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches. +system.cpu1.numCycles 193493 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.fetch.icacheStallCycles 35625 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 388406 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 70381 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 54174 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 147522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4799 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1696 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 23532 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 933 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 187271 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 2.074032 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.377312 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 61181 32.67% 32.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 61333 32.75% 65.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6091 3.25% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3354 1.79% 70.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 663 0.35% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43826 23.40% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1093 0.58% 94.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1351 0.72% 95.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 8379 4.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 187271 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.363739 # Number of branch fetches per cycle +system.cpu1.fetch.rate 2.007339 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 22629 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 55115 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 103585 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3533 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2399 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 358317 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2399 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23637 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 25102 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14378 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 104390 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 17355 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 351725 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 14900 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 247787 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 679105 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 526513 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 34 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 220167 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 27620 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1612 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1735 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 22764 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 99432 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 48003 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 46782 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41727 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 289849 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 288395 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 24134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 20047 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1135 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 187271 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.539988 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.388620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 65886 35.18% 35.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21449 11.45% 46.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46526 24.84% 71.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 46214 24.68% 96.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3599 1.92% 98.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1752 0.94% 99.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1124 0.60% 99.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 416 0.22% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 187271 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 198 39.68% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 73 14.63% 54.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 228 45.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 138505 48.03% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 102963 35.70% 83.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 46927 16.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 288395 # Type of FU issued +system.cpu1.iq.rate 1.490467 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 499 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001730 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 764671 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 320465 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 284383 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 288894 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 41593 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 4579 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 2399 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8044 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 344307 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 270 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 99432 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 48003 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1487 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2454 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2900 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 285809 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 97701 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2586 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 47948 # number of nop insts executed +system.cpu1.iew.exec_refs 144318 # number of memory reference insts executed +system.cpu1.iew.exec_branches 58093 # Number of branches executed +system.cpu1.iew.exec_stores 46617 # Number of stores executed +system.cpu1.iew.exec_rate 1.477103 # Inst execution rate +system.cpu1.iew.wb_sent 284919 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 284383 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 161989 # num instructions producing a value +system.cpu1.iew.wb_consumers 169394 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.469733 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.956285 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 25278 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5375 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2321 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 182469 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.748204 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.087021 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 70580 38.68% 38.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 54368 29.80% 68.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5362 2.94% 71.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6062 3.32% 74.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1316 0.72% 75.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41726 22.87% 98.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 809 0.44% 98.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1001 0.55% 99.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1245 0.68% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 182469 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 318993 # Number of instructions committed +system.cpu1.commit.committedOps 318993 # Number of ops (including micro ops) committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 140209 # Number of memory references committed +system.cpu1.commit.loads 94853 # Number of loads committed +system.cpu1.commit.membars 4659 # Number of memory barriers committed +system.cpu1.commit.branches 55980 # Number of branches committed +system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 218308 # Number of committed integer instructions. +system.cpu1.commit.function_calls 322 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 46768 14.66% 14.66% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 127357 39.92% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 99512 31.20% 85.78% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 45356 14.22% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 318993 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1245 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 524909 # The number of ROB reads +system.cpu1.rob.rob_writes 693389 # The number of ROB writes +system.cpu1.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6222 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 267566 # Number of Instructions Simulated +system.cpu1.committedOps 267566 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.723160 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.723160 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.382820 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.382820 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 496242 # number of integer regfile reads +system.cpu1.int_regfile_writes 230976 # number of integer regfile writes +system.cpu1.fp_regfile_writes 64 # number of floating regfile writes +system.cpu1.misc_regfile_reads 146210 # number of misc regfile reads +system.cpu1.misc_regfile_writes 648 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1693.032258 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.604916 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051963 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051963 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 45140 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 100708 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 100708 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 100708 # number of overall hits +system.cpu1.dcache.overall_hits::total 100708 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 146 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 146 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 653 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 653 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 653 # number of overall misses +system.cpu1.dcache.overall_misses::total 653 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9264000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9264000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3726500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3726500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 796000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 796000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12990500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12990500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12990500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12990500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 56075 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 56075 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 45286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 45286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 101361 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 101361 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 101361 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 101361 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009041 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009041 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003224 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003224 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.828571 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006442 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006442 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006442 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006442 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18272.189349 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18272.189349 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25523.972603 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25523.972603 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13724.137931 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 13724.137931 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19893.568147 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19893.568147 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 40 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 2 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 381 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 381 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 381 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2098000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1657500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1657500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 738000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 738000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3755500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3755500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3755500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3755500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002341 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002341 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002683 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002683 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12638.554217 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12638.554217 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15636.792453 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15636.792453 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 13178.571429 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 13178.571429 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency +system.cpu1.icache.tags.replacements 579 # number of replacements +system.cpu1.icache.tags.tagsinuse 98.515696 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22662 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 713 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.784011 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 98.515696 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.192413 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.192413 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 8 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 24245 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 24245 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 22662 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22662 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22662 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22662 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22662 # number of overall hits +system.cpu1.icache.overall_hits::total 22662 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 870 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 870 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 870 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 870 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 870 # number of overall misses +system.cpu1.icache.overall_misses::total 870 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19533000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 19533000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 19533000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 19533000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 19533000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 19533000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23532 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23532 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23532 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23532 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23532 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23532 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036971 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.036971 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036971 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.036971 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036971 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.036971 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22451.724138 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 22451.724138 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 22451.724138 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 22451.724138 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 579 # number of writebacks +system.cpu1.icache.writebacks::total 579 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 157 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 157 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 713 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 713 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 713 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 713 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15250000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 15250000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15250000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 15250000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15250000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 15250000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030299 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030299 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030299 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21388.499299 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency +system.cpu2.branchPred.lookups 63667 # Number of BP lookups +system.cpu2.branchPred.condPredicted 55684 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2455 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 55606 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 0 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 2018 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 55606 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches. +system.cpu2.numCycles 193104 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.fetch.icacheStallCycles 40968 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 342539 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 63667 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 46663 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 146022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 5067 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1848 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 29416 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 951 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 191398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.789669 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.326327 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 76889 40.17% 40.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 56601 29.57% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8825 4.61% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3447 1.80% 76.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 694 0.36% 76.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 33672 17.59% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 980 0.51% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1389 0.73% 95.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8901 4.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 191398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.329703 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.773858 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 22836 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 76803 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 84446 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4770 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2533 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 310490 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2533 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 23870 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 37657 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 14813 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 85216 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 27299 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 303538 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 23577 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 211726 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 571973 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 446566 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 182781 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 28945 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1674 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1822 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 33085 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82000 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37987 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 39268 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 31634 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 245836 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 9182 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 247097 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 25038 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1244 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 191398 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.291011 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.381781 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 81765 42.72% 42.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29268 15.29% 58.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 36754 19.20% 77.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 36522 19.08% 96.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3555 1.86% 98.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1723 0.90% 99.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1061 0.55% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 446 0.23% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 304 0.16% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 191398 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 203 40.76% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 64 12.85% 53.61% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 231 46.39% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 121951 49.35% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 88101 35.65% 85.01% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 37045 14.99% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 247097 # Type of FU issued +system.cpu2.iq.rate 1.279606 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 498 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.002015 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 686175 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 280041 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 243170 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 247595 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 31591 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 4554 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2621 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 2533 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10681 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 295617 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 336 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82000 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37987 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1539 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2642 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3088 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 244561 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 80330 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2536 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 40599 # number of nop insts executed +system.cpu2.iew.exec_refs 117071 # number of memory reference insts executed +system.cpu2.iew.exec_branches 50931 # Number of branches executed +system.cpu2.iew.exec_stores 36741 # Number of stores executed +system.cpu2.iew.exec_rate 1.266473 # Inst execution rate +system.cpu2.iew.wb_sent 243660 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 243170 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 134852 # num instructions producing a value +system.cpu2.iew.wb_consumers 142392 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.259270 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.947048 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 26266 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7938 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2455 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 186363 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.445163 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.976076 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 89147 47.84% 47.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 47087 25.27% 73.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5442 2.92% 76.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8636 4.63% 80.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1280 0.69% 81.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 31787 17.06% 98.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 722 0.39% 98.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1037 0.56% 99.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1225 0.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 186363 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 269325 # Number of instructions committed +system.cpu2.commit.committedOps 269325 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 112812 # Number of memory references committed +system.cpu2.commit.loads 77446 # Number of loads committed +system.cpu2.commit.membars 7225 # Number of memory barriers committed +system.cpu2.commit.branches 48554 # Number of branches committed +system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 183489 # Number of committed integer instructions. +system.cpu2.commit.function_calls 322 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 39345 14.61% 14.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 109943 40.82% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 84671 31.44% 86.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 35366 13.13% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 269325 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1225 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 480143 # The number of ROB reads +system.cpu2.rob.rob_writes 596277 # The number of ROB writes +system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1706 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222755 # Number of Instructions Simulated +system.cpu2.committedOps 222755 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.866890 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.866890 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.153549 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.153549 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 415553 # number of integer regfile reads +system.cpu2.int_regfile_writes 194388 # number of integer regfile writes +system.cpu2.fp_regfile_writes 64 # number of floating regfile writes +system.cpu2.misc_regfile_reads 119022 # number of misc regfile reads +system.cpu2.misc_regfile_writes 648 # number of misc regfile writes +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1416.666667 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.641689 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050081 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.050081 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 35154 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 83369 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 83369 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 83369 # number of overall hits +system.cpu2.dcache.overall_hits::total 83369 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 500 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 500 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 145 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 145 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 645 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 645 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 645 # number of overall misses +system.cpu2.dcache.overall_misses::total 645 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8163500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 8163500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3144500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3144500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 806000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 806000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11308000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11308000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11308000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11308000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 48715 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 48715 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 35299 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 35299 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 84014 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 84014 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 84014 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 84014 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010264 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010264 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004108 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004108 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.805970 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007677 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007677 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007677 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007677 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16327 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16327 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21686.206897 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 21686.206897 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 14925.925926 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 14925.925926 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17531.782946 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17531.782946 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 338 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 338 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 39 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 39 # number of WriteReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 2 # number of SwapReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 377 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 377 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 377 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 377 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1730500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1730500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1679500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1679500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 752000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 752000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3410000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3410000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3410000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3410000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003325 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003325 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003003 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003003 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.776119 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003190 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003190 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10682.098765 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10682.098765 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15844.339623 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15844.339623 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14461.538462 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14461.538462 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency +system.cpu2.icache.tags.replacements 598 # number of replacements +system.cpu2.icache.tags.tagsinuse 95.853337 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 28564 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.968622 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 95.853337 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.187214 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.187214 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 30149 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 30149 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 28564 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 28564 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 28564 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 28564 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 28564 # number of overall hits +system.cpu2.icache.overall_hits::total 28564 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 852 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 852 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 852 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 852 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 852 # number of overall misses +system.cpu2.icache.overall_misses::total 852 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12789500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 12789500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 12789500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 12789500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 12789500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 12789500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 29416 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 29416 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 29416 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 29416 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 29416 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 29416 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028964 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028964 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.028964 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028964 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.028964 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15011.150235 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15011.150235 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15011.150235 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15011.150235 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 111 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 22.200000 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.writebacks::writebacks 598 # number of writebacks +system.cpu2.icache.writebacks::total 598 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 119 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 119 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 119 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 119 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 733 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 733 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 733 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 733 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10899500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10899500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10899500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10899500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10899500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10899500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024918 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.024918 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14869.713506 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency +system.cpu3.branchPred.lookups 61800 # Number of BP lookups +system.cpu3.branchPred.condPredicted 53939 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2339 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 53501 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 0 # Number of BTB hits +system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 53501 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches. +system.cpu3.numCycles 192748 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.fetch.icacheStallCycles 41262 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 329189 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 61800 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45098 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 145688 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing +system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1762 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 30337 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 926 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 191141 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.722231 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.297340 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 79632 41.66% 41.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55527 29.05% 70.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 9457 4.95% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3401 1.78% 77.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 679 0.36% 77.79% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 31347 16.40% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1154 0.60% 94.80% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1382 0.72% 95.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8562 4.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 191141 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.320626 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.707872 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 22425 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 81552 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 79630 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5108 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2416 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 297344 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2416 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 23427 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 40476 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14673 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 80471 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 29668 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 290876 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 25659 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 201895 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 544124 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 425656 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 36 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 173837 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 28058 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1657 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1795 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 35428 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 77674 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 35638 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 37571 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 29275 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 234657 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 236528 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 24579 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 19470 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1266 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 191141 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.237453 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.372875 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 84630 44.28% 44.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 31019 16.23% 60.50% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 34273 17.93% 78.44% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 34156 17.87% 96.30% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3613 1.89% 98.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1675 0.88% 99.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1066 0.56% 99.63% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 400 0.21% 99.84% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 309 0.16% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 191141 # Number of insts issued each cycle +system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 176 38.18% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 50 10.85% 49.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 235 50.98% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 117496 49.68% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 84415 35.69% 85.36% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 34617 14.64% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::total 236528 # Type of FU issued +system.cpu3.iq.rate 1.227136 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 461 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001949 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 664726 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 269047 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 232596 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 236989 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 29180 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.squashedLoads 4384 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2661 # Number of stores squashed +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu3.iew.iewSquashCycles 2416 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 11113 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 283276 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 77674 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 35638 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1522 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2483 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2954 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 233943 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 76012 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2585 # Number of squashed instructions skipped in execute +system.cpu3.iew.exec_swp 0 # number of swp insts executed +system.cpu3.iew.exec_nop 38771 # number of nop insts executed +system.cpu3.iew.exec_refs 110309 # number of memory reference insts executed +system.cpu3.iew.exec_branches 49060 # Number of branches executed +system.cpu3.iew.exec_stores 34297 # Number of stores executed +system.cpu3.iew.exec_rate 1.213725 # Inst execution rate +system.cpu3.iew.wb_sent 233093 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 232596 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 128296 # num instructions producing a value +system.cpu3.iew.wb_consumers 135910 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.206736 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.943978 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 25736 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8582 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2339 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 186297 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.382277 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.944418 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 92574 49.69% 49.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 45329 24.33% 74.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5460 2.93% 76.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9239 4.96% 81.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1287 0.69% 82.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 29468 15.82% 98.42% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 712 0.38% 98.80% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1036 0.56% 99.36% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1192 0.64% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 186297 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 257514 # Number of instructions committed +system.cpu3.commit.committedOps 257514 # Number of ops (including micro ops) committed +system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu3.commit.refs 106267 # Number of memory references committed +system.cpu3.commit.loads 73290 # Number of loads committed +system.cpu3.commit.membars 7865 # Number of memory barriers committed +system.cpu3.commit.branches 46801 # Number of branches committed +system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 175188 # Number of committed integer instructions. +system.cpu3.commit.function_calls 322 # Number of function calls committed. +system.cpu3.commit.op_class_0::No_OpClass 37588 14.60% 14.60% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 105794 41.08% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 81155 31.51% 87.19% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 32977 12.81% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::total 257514 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1192 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 467769 # The number of ROB reads +system.cpu3.rob.rob_writes 571412 # The number of ROB writes +system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1607 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 212061 # Number of Instructions Simulated +system.cpu3.committedOps 212061 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.908927 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.908927 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.100198 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.100198 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 395124 # number of integer regfile reads +system.cpu3.int_regfile_writes 185063 # number of integer regfile writes +system.cpu3.fp_regfile_writes 64 # number of floating regfile writes +system.cpu3.misc_regfile_reads 112177 # number of misc regfile reads +system.cpu3.misc_regfile_writes 648 # number of misc regfile writes +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1381.689655 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.465247 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047784 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047784 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 32769 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 79122 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 79122 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 79122 # number of overall hits +system.cpu3.dcache.overall_hits::total 79122 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 454 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 454 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 591 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 591 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 591 # number of overall misses +system.cpu3.dcache.overall_misses::total 591 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 6996500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 6996500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2957500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2957500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 770500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 770500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 9954000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 9954000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 9954000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 9954000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 46807 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 46807 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 32906 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 32906 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 79713 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 79713 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 79713 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 79713 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009699 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009699 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004163 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004163 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007414 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007414 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007414 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007414 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15410.792952 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15410.792952 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21587.591241 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 21587.591241 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 13758.928571 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 13758.928571 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16842.639594 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16842.639594 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 292 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 3 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::total 3 # number of SwapReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 327 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 327 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 327 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 327 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 162 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1605500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1605500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1601500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1601500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 714500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 714500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3207000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3207000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3207000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3207000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003461 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003461 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003100 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003100 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.746479 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003312 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003312 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9910.493827 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9910.493827 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15700.980392 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15700.980392 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 13481.132075 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 13481.132075 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency +system.cpu3.icache.tags.replacements 563 # number of replacements +system.cpu3.icache.tags.tagsinuse 93.764815 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 29516 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 701 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 42.105563 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.764815 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183134 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.183134 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 31038 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 31038 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 29516 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 29516 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 29516 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 29516 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 29516 # number of overall hits +system.cpu3.icache.overall_hits::total 29516 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 821 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 821 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 821 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 821 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 821 # number of overall misses +system.cpu3.icache.overall_misses::total 821 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11709000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 11709000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 11709000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 11709000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 11709000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 30337 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 30337 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 30337 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 30337 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 30337 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 30337 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.027063 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.027063 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.027063 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.027063 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.027063 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.027063 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14261.875761 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14261.875761 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14261.875761 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14261.875761 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.writebacks::writebacks 563 # number of writebacks +system.cpu3.icache.writebacks::total 563 # number of writebacks +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 120 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 120 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 120 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 120 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 701 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 701 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 701 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 701 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 701 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10046500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 10046500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10046500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 10046500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10046500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 10046500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023107 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.023107 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.023107 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14331.669044 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 455.287968 # Cycle average of tags in use +system.l2c.tags.total_refs 3075 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 580 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.301724 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.808056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 302.503225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.822483 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 70.101034 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.583860 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 9.384250 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1.286758 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 5.637625 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1.160677 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000898 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001070 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000085 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000020 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000086 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000018 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006947 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 580 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008850 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 31874 # Number of tag accesses +system.l2c.tags.data_accesses 31874 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 709 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 709 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 319 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 617 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 711 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 686 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 2333 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 319 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 617 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 686 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::total 2365 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 319 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 617 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu2.inst 711 # number of overall hits +system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu3.inst 686 # number of overall hits +system.l2c.overall_hits::cpu3.data 11 # number of overall hits +system.l2c.overall_hits::total 2365 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 24 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 377 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 22 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 15 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 510 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 3 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 377 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 96 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 22 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses +system.l2c.demand_misses::total 731 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 377 # number of overall misses +system.l2c.overall_misses::cpu0.data 170 # number of overall misses +system.l2c.overall_misses::cpu1.inst 96 # number of overall misses +system.l2c.overall_misses::cpu1.data 22 # number of overall misses +system.l2c.overall_misses::cpu2.inst 22 # number of overall misses +system.l2c.overall_misses::cpu2.data 15 # number of overall misses +system.l2c.overall_misses::cpu3.inst 15 # number of overall misses +system.l2c.overall_misses::cpu3.data 14 # number of overall misses +system.l2c.overall_misses::total 731 # number of overall misses +system.l2c.ReadExReq_miss_latency::cpu0.data 7826000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1039500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 940000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 937500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10743000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 29108500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 7180500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 1748500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 1200000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 39237500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 6133500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 728000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 251500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 195000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 7308000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 29108500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 13959500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 7180500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1767500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 1748500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1191500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 1200000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1132500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 57288500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 29108500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 13959500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 7180500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1767500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 1748500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1191500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 1200000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1132500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 57288500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 709 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 709 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 696 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 713 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 733 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 701 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 2843 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 713 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 701 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3096 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 713 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 733 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 701 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3096 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.965909 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.541667 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.134642 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.030014 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.021398 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.179388 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.214286 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.737705 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.134642 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.030014 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.576923 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.021398 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.236111 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.134642 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.030014 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.576923 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.021398 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.236111 # miss rate for overall accesses +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83255.319149 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79961.538462 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 78333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 82007.633588 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77210.875332 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74796.875000 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 79477.272727 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 80000 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 76936.274510 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80703.947368 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 80888.888889 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83833.333333 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 97500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 81200 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 80000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78370.041040 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 80000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78370.041040 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 24 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 85 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 376 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 11 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 493 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 3 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 376 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 92 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 714 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 376 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 92 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 714 # number of overall MSHR misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 419500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 400000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 480000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 398000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1697500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6886000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 909500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 820000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 817500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9433000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 25321000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6077500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1080000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 797000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 33275500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5373500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 638000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 221500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 175000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 6408000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 25321000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12259500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 6077500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1547500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 1080000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1041500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 797000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 992500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 49116500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 25321000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12259500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 6077500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1547500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 1080000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1041500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 797000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 992500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 49116500 # number of overall MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.965909 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173408 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.214286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.737705 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.230620 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.230620 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19976.190476 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19970.588235 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73255.319149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69961.538462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68333.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 68125 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72007.633588 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67495.943205 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70703.947368 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70888.888889 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73833.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 87500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71200 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 1042 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 329 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadResp 582 # Transaction distribution +system.membus.trans_dist::UpgradeReq 274 # Transaction distribution +system.membus.trans_dist::ReadExReq 186 # Transaction distribution +system.membus.trans_dist::ReadExResp 131 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 582 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1755 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45632 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 244 # Total snoops (count) +system.membus.snoop_fanout::samples 1042 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1042 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1042 # Request fanout histogram +system.membus.reqLayer0.occupancy 989502 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3800250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.1 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 6343 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1724 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3317 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2134 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2843 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 684 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1785 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2005 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1965 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9526 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 80896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 334720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4207 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.289042 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.099056 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1302 30.95% 30.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1193 28.36% 59.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 906 21.54% 80.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 806 19.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4207 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5321969 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1043498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 522987 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1072493 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 443462 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1103489 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 430971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1053495 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 426466 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |