1 files changed, 32 insertions, 25 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 90b4c4184..a47e5e15d 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[2]
+system_port=system.membus.slave[1]
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu0.interrupts
@@ -62,7 +62,7 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -83,7 +83,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.port[2]
+mem_side=system.toL2Bus.slave[1]
 
 [system.cpu0.dtb]
 type=SparcTLB
@@ -91,7 +91,7 @@ size=64
 
 [system.cpu0.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -112,7 +112,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.port[1]
+mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.interrupts]
 type=SparcInterrupts
@@ -154,6 +154,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu1.interrupts
@@ -177,7 +178,7 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -198,7 +199,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.port[4]
+mem_side=system.toL2Bus.slave[3]
 
 [system.cpu1.dtb]
 type=SparcTLB
@@ -206,7 +207,7 @@ size=64
 
 [system.cpu1.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -227,7 +228,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.port[3]
+mem_side=system.toL2Bus.slave[2]
 
 [system.cpu1.interrupts]
 type=SparcInterrupts
@@ -250,6 +251,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu2.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu2.interrupts
@@ -273,7 +275,7 @@ icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -294,7 +296,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.port[6]
+mem_side=system.toL2Bus.slave[5]
 
 [system.cpu2.dtb]
 type=SparcTLB
@@ -302,7 +304,7 @@ size=64
 
 [system.cpu2.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -323,7 +325,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.port[5]
+mem_side=system.toL2Bus.slave[4]
 
 [system.cpu2.interrupts]
 type=SparcInterrupts
@@ -346,6 +348,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu3.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu3.interrupts
@@ -369,7 +372,7 @@ icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
 forward_snoops=true
@@ -390,7 +393,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.port[8]
+mem_side=system.toL2Bus.slave[7]
 
 [system.cpu3.dtb]
 type=SparcTLB
@@ -398,7 +401,7 @@ size=64
 
 [system.cpu3.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
 forward_snoops=true
@@ -419,7 +422,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.port[7]
+mem_side=system.toL2Bus.slave[6]
 
 [system.cpu3.interrupts]
 type=SparcInterrupts
@@ -433,7 +436,7 @@ type=ExeTracer
 
 [system.l2c]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
 forward_snoops=true
@@ -453,8 +456,8 @@ tgts_per_mshr=16
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[0]
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
 
 [system.membus]
 type=Bus
@@ -464,17 +467,20 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.mem_side system.physmem.port[0] system.system_port
+master=system.physmem.port[0]
+slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:1073741823
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
 [system.toL2Bus]
 type=Bus
@@ -484,5 +490,6 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side