diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt | 478 |
1 files changed, 239 insertions, 239 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 42fbfc6a4..8179c99d9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1256528 # Simulator instruction rate (inst/s) -host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162691956 # Simulator tick rate (ticks/s) -host_mem_usage 1160656 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 170274 # Simulator instruction rate (inst/s) +host_op_rate 170274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22048637 # Simulator tick rate (ticks/s) +host_mem_usage 246052 # Number of bytes of host memory used +host_seconds 3.98 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -60,6 +60,184 @@ system.physmem.bw_total::total 407903588 # To system.membus.throughput 407903588 # Throughput (bytes/s) system.membus.data_through_bus 35776 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 185 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 296 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits +system.l2c.overall_hits::cpu2.inst 356 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 357 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::total 423 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::total 559 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 282 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 62 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 2 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses +system.l2c.overall_misses::total 559 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) system.toL2Bus.data_through_bus 166080 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -86,15 +264,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 175415 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -128,15 +306,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -210,15 +388,15 @@ system.cpu1.num_idle_cycles 7873.724337 # Nu system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits @@ -252,15 +430,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits @@ -332,15 +510,15 @@ system.cpu2.num_idle_cycles 7936.951217 # Nu system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits @@ -374,15 +552,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits @@ -454,15 +632,15 @@ system.cpu3.num_idle_cycles 8001.119846 # Nu system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits @@ -496,15 +674,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits @@ -554,183 +732,5 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 356 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 357 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 2 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |