diff options
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt')
| -rw-r--r-- | tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt | 848 |
1 files changed, 411 insertions, 437 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 0cc0a830c..71dd904a3 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1650324 # Simulator instruction rate (inst/s) -host_tick_rate 213702670 # Simulator tick rate (ticks/s) -host_mem_usage 1140448 # Number of bytes of host memory used +host_inst_rate 1664146 # Simulator instruction rate (inst/s) +host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215483439 # Simulator tick rate (ticks/s) +host_mem_usage 1139232 # Number of bytes of host memory used host_seconds 0.41 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated +sim_ops 677340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 35776 # Number of bytes read from this memory system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls 89 # Nu system.cpu0.numCycles 175428 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 175339 # Number of instructions executed +system.cpu0.committedInsts 175339 # Number of instructions committed +system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured @@ -46,24 +49,30 @@ system.cpu0.icache.total_refs 174934 # To system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 222.757301 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.435073 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 174934 # number of ReadReq hits -system.cpu0.icache.demand_hits 174934 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 174934 # number of overall hits -system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses -system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 467 # number of overall misses -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 175401 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 175401 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.002662 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.002662 # miss rate for overall accesses -system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 222.757301 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.435073 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.435073 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 174934 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 174934 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 174934 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 174934 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 174934 # number of overall hits +system.cpu0.icache.overall_hits::total 174934 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -72,22 +81,6 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use @@ -95,32 +88,44 @@ system.cpu0.dcache.total_refs 61599 # To system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.284595 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 54431 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 27578 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu0.dcache.demand_hits 82009 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 82009 # number of overall hits -system.cpu0.dcache.ReadReq_misses 151 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses 177 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses -system.cpu0.dcache.demand_misses 328 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 328 # number of overall misses -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 82337 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.003984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.003984 # miss rate for overall accesses -system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 82009 # number of overall hits +system.cpu0.dcache.overall_hits::total 82009 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses +system.cpu0.dcache.overall_misses::total 328 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 54582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 54582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,27 +134,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks +system.cpu0.dcache.writebacks::total 6 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173308 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 167398 # Number of instructions executed +system.cpu1.committedInsts 167398 # Number of instructions committed +system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 633 # number of times a function call or return occured @@ -173,24 +165,30 @@ system.cpu1.icache.total_refs 167072 # To system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 76.746014 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.149895 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 167072 # number of ReadReq hits -system.cpu1.icache.demand_hits 167072 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 167072 # number of overall hits -system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 358 # number of overall misses -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 167430 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 167430 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.002138 # miss rate for overall accesses -system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 76.746014 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.149895 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.149895 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits +system.cpu1.icache.overall_hits::total 167072 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses +system.cpu1.icache.overall_misses::total 358 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,22 +197,6 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use @@ -222,32 +204,44 @@ system.cpu1.dcache.total_refs 26889 # To system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 40468 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 12563 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits 53031 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 53031 # number of overall hits -system.cpu1.dcache.ReadReq_misses 176 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses 282 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 282 # number of overall misses -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 12669 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 53313 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 53313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.004330 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses -system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits +system.cpu1.dcache.overall_hits::total 53031 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses +system.cpu1.dcache.overall_misses::total 282 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,27 +250,14 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu1.dcache.writebacks::total 1 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173308 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.num_insts 167334 # Number of instructions executed +system.cpu2.committedInsts 167334 # Number of instructions committed +system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 633 # number of times a function call or return occured @@ -300,24 +281,30 @@ system.cpu2.icache.total_refs 167008 # To system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 74.775474 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.146046 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 167008 # number of ReadReq hits -system.cpu2.icache.demand_hits 167008 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 167008 # number of overall hits -system.cpu2.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu2.icache.demand_misses 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 358 # number of overall misses -system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 167366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 167366 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 167366 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.002139 # miss rate for overall accesses -system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 74.775474 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.146046 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.146046 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits +system.cpu2.icache.overall_hits::total 167008 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses +system.cpu2.icache.overall_misses::total 358 # number of overall misses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,22 +313,6 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use @@ -349,32 +320,44 @@ system.cpu2.dcache.total_refs 33771 # To system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 42192 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 15998 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits 58190 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 58190 # number of overall hits -system.cpu2.dcache.ReadReq_misses 162 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 271 # number of overall misses -system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 16107 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 58461 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 58461 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses -system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits +system.cpu2.dcache.overall_hits::total 58190 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses +system.cpu2.dcache.overall_misses::total 271 # number of overall misses +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,27 +366,14 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu2.dcache.writebacks::total 1 # number of writebacks system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173307 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.num_insts 167269 # Number of instructions executed +system.cpu3.committedInsts 167269 # Number of instructions committed +system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 633 # number of times a function call or return occured @@ -427,24 +397,30 @@ system.cpu3.icache.total_refs 166942 # To system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 72.869097 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.142322 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 166942 # number of ReadReq hits -system.cpu3.icache.demand_hits 166942 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 166942 # number of overall hits -system.cpu3.icache.ReadReq_misses 359 # number of ReadReq misses -system.cpu3.icache.demand_misses 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 359 # number of overall misses -system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 167301 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 167301 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 167301 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.002146 # miss rate for overall accesses -system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 72.869097 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.142322 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.142322 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits +system.cpu3.icache.overall_hits::total 166942 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses +system.cpu3.icache.overall_misses::total 359 # number of overall misses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,22 +429,6 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use @@ -476,32 +436,44 @@ system.cpu3.dcache.total_refs 30309 # To system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 41299 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 14260 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits 55559 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 55559 # number of overall hits -system.cpu3.dcache.ReadReq_misses 159 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 102 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses 261 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 261 # number of overall misses -system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 14362 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 55820 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 55820 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses -system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits +system.cpu3.dcache.overall_hits::total 55559 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses +system.cpu3.dcache.overall_misses::total 261 # number of overall misses +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,22 +482,8 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu3.dcache.writebacks::total 1 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 371.980910 # Cycle average of tags in use @@ -533,124 +491,164 @@ system.l2c.total_refs 1223 # To system.l2c.sampled_refs 426 # Sample count of references to valid blocks. system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 294.613840 # Average occupied blocks per context -system.l2c.occ_blocks::1 66.228089 # Average occupied blocks per context -system.l2c.occ_blocks::2 2.865859 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.883074 # Average occupied blocks per context -system.l2c.occ_blocks::4 6.390048 # Average occupied blocks per context -system.l2c.occ_percent::0 0.004495 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.001011 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000044 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000029 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000098 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 190 # number of ReadReq hits -system.l2c.ReadReq_hits::1 301 # number of ReadReq hits -system.l2c.ReadReq_hits::2 367 # number of ReadReq hits -system.l2c.ReadReq_hits::3 368 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.720647 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.930518 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::0 190 # number of demand (read+write) hits -system.l2c.demand_hits::1 301 # number of demand (read+write) hits -system.l2c.demand_hits::2 367 # number of demand (read+write) hits -system.l2c.demand_hits::3 368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 357 # 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number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::0 447 # number of demand (read+write) misses -system.l2c.demand_misses::1 82 # number of demand (read+write) misses -system.l2c.demand_misses::2 15 # number of demand (read+write) misses -system.l2c.demand_misses::3 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::0 447 # number of overall misses -system.l2c.overall_misses::1 82 # number of overall misses -system.l2c.overall_misses::2 15 # number of overall misses -system.l2c.overall_misses::3 15 # number of overall misses +system.l2c.overall_misses::cpu0.inst 282 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 62 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 2 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.646840 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.186486 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.008108 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.008086 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.849521 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.935484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 3.935484 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.701727 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.214099 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.039267 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.039164 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.994258 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.701727 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.214099 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.039267 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.039164 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.994258 # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -659,30 +657,6 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 0 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |